mipi devcon 2016: mipi c-phy - introduction from basic theory to practical implementation
TRANSCRIPT
MIPI C-PHY℠: Introduction
From Basic Theory to Practical Implementation
Mohamed Hafed Introspect Technology
Original Spark: Three Phase Encoding!
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GeorgeWiley,Qualcomm
1UnitIntervalofData
2.285BitsofInforma?on
Basic Concept of Three Phase Encoding
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Three Voltage Levels Per Wire Ensure Proper Differential Reception
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Always-Toggle Design Allows for Simple Clock Recovery (100% Transition Density)
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Key Takeaways
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Three-level single-ended signaling
Non-deterministic transitions based on self-clocked mapping and encoding algorithm
Evolution from D-PHY (1 Lane, 4 Wires)
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Evolution from D-PHY (1 Lane, 4 Wires)
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Evolution from D-PHY (1 Lane, 4 Wires)
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Evolution from D-PHY (1 Lane, 4 Wires)
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Architecturally Flexible
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Source:MIPIAlliance
Mapping and Encoding
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C-PHY Data Types
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ANALOG DIGITAL
A
B
C
• 3wiresperlane• 3-levelwires(LOW,MID,HIGH)• Everyunitintervalmustcontain
LOW,MID,andHIGHwires• Notwoconsecu?veiden?cal
wirestates
Symbols(3bits)
Integers(16bits)
A>B
B>C
C>A
WireStates(3bits)
Wiredifferen?al
7-symbolto16-bitmapping
Wires Wirestates
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6 3 4 6 5 3 6
-z -y -z -x +x -z -z-y -x
02
2 4 1 0 0 0
0x7290
Wire States
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A B C A>B B>C C>AWirestatename
HIGH LOW MID 1 0 0 +x
LOW HIGH MID 0 1 1 -x
MID HIGH LOW 0 1 0 +y
MID LOW HIGH 1 0 1 -y
LOW MID HIGH 0 0 1 +z
HIGH MID LOW 1 1 0 -z
ANALOG DIGITAL(3bits)
• Awirestateisthecollec?onofA,B,andC• 6possiblewirestates
Symbols: Now We’re Transmitting!
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• Asymbolrepresentsatransi?onbetweentwowirestates• 5possiblesymbols
Symbol(3bits)
Flip Rotate Polarity
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 DC DC
Rotate
0 Decr.le_er
1 Incr.le_er
Polarity
0 -
1 Togglesign
Flip
0 -
1 Samele_er,togglesign.
-z+x
Example:
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Mapping 7 Symbols 16-bit Integers
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• C-PHYdefinesamappingbetween7-symbolwordsand16-bitintegers
Numberof7-symbolwords: Numberof16-bitintegers:
65536
7-symbolwords 16-bitintegers
65536
12589unmappedwords
1-to-1mapping
{0224100} 0x7290
{3444443}
{4444444}
SyncWord(Alignmentmarker)
Post(End-of-Packetmarker)
Well Defined Algorithms from MIPI Alliance
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“Don’t Even Worry
About It”
Eco-System Is Developed for Tools
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Three-PhaseSignals
DecodedData
Anatomy of a Packet Transmission
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Practical Experiences
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Tx: Both Mapping and Encoding Before Serializer
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Rx: Avoiding False Sync Detection (Problem Statement)
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Rx: Avoiding False Sync Detection (Solution)
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DetectSYNCwithPre-EndasMarkerforStartofTransmission
CSI-2 Long Packets in C-PHY
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CSI-2 Long Packets in C-PHY
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CSI-2 Long Packets in C-PHY
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CSI-2 Long Packets in C-PHY
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CSI-2 Long Packets in C-PHY: The Invisible SYNC
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DSI-2 Long Packets in C-PHY
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DSI-2 Long Packets in C-PHY
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DSI-2 Long Packets in C-PHY
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DSI-2 Long Packets in C-PHY
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DSI-2 Sample Protocol Analyzer Trace
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DSI-2 Sample Protocol Analyzer Trace
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Key Takeaways
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Tx mapping and encoding in parallel domain
Rx false sync avoidance required pre-begin monitoring
Packet header definition required careful design of SYNC manipulation (both Tx and Rx)
CSI-2 & DSI-2 treat SYNC insertion differently
April 10, 2014: World’s First C-PHY Interoperability!
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Leading Image Sensor Manufacturer Test Chip
(Tx)
2.0 Gsps
First Packet Received First Eye Diagram