Troubleshooting MIPI M-PHY Link

and Protocol Issues

Gordon Getty Application Engineer

Teledyne LeCroy

Objective

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A major component of the "Internet of Things" is mobile device support. The MIPI M-PHY specification is designed to allow mobile devices to have a low power, high performance interface. Several higher level protocols use the M-PHY physical layer for storage, I/O and memory in mobile devices. This paper will discuss how higher layer protocols such as MIPI UniPro, and UFS use the M-PHY physical layer to allow traditional PC type protocols to be enabled on mobile platforms.

Internet of Things “IoT”

MIPI/Mobile Market Overview

“Internet of Things”

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New Markets Reaching 1 Billion Milestone Quickly

•  Cell phones sold 1 Billion units in 7.5 years, PCs took 21 years.

• Mobile shipped 4 Billion units in 12.5 years, PC market will take over 33 years.

•  Tablets will hit 1 Billion in 6 years.

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Mobility Driving Growth

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• Mobile market will be >8 times the size of the PC market

•  Notebook PCs evolving into large tablets

Market Trends

•  Smartphone market driving innovation •  Large volumes, fast design cycles •  Personal, always at hand

• Other markets will leverage smartphone designs •  •   Increasing number of MEMS per system

•   Eroding ASPs

•  Sensor Hub will become more specialized •  32-bit MCU will be challenged

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MIPI Technologies

Physical Layer Interconnects

•  Low Speed Interconnects •  MIPI SlimBus

•  Audio •  MIPI SoundWire

•  Audio •  CMOS I/O

•  Chip to Chip

•  High Speed Interconnects •  MIPI D-PHY

•  Camera, Display •  MIPI M-PHY

•  MIPI UniPro/UniPort •  Camera (Unipro), Storage (UniPro), Modem, Interchip

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MIPI M-PHY Protocols • MIPI M-PHY protocols are used based on interface

used in each application. • Multiple protocols can be used in a single device.

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MIPI M-PHY

Why MIPI M-PHY? From the M-PHY Specification V4.0:

“Mobile devices face increasing bandwidth demands for each of its functions as well as an increase of the number of functions integrated into the system. This requires wide bandwidth, low-pin count (serial) and highly power-efficient (network) interfaces that provides sufficient flexibility to be attractive for multiple applications, but which can also be covered with one physical layer technology. M-PHY is the successor of D-PHY, requiring less pins and providing more bandwidth per pin (pair) with improved power efficiency.”

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M-PHY Lane Example - Terminology

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Line States •  M-PHY technology exploits only differential signaling. a LINE can show the

following states: •  A positive differential voltage, driven by the M-TX, which is denoted by LINE state DIF-P •  A negative differential voltage, driven by the M-TX, which is denoted by LINE state DIF-N •  A weak zero differential voltage, maintained by M-RX, which is denoted by LINE state DIF-Z •  An unknown, floating LINE voltage, or no LINE drive, which is denoted by LINE state DIF-Q

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Signal Amplitudes •  All communication is based on low-swing, DC-coupled,

differential signaling •  The LINE driver in an M-TX may support two drive

strengths, resulting in different signal amplitudes. •  Large Amplitude (LA) is about 400 mVPK_NT (and roughly 200

mVPK_RT) •  Small Amplitude (SA) is about 240 mVPK_NT (and roughly 120

mVPK_RT)

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Signaling Schemes •  LS and HS Speed (Optional) • May use a shared clock or different reference clocks •  Uses NRZ signaling

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Data Rates •  LS-MODE

•  Gears 0-7 •  HS-MODE

•  Gears 1-3 •  All Modules (Host and Device) must support LS

•  Default for PWM is Gear1 3-9Mbs •  Each Gear supports 2x higher speeds •  one GEAR below the default speed range (PWM-G0)

•  HS-Mode is Optional •  HS-MODE includes a default GEAR (HS-G1) •  Two optional GEARs (HS-G2 and HS-G3) at incremental 2x higher rates •  Each GEAR includes two data rates for EMI mitigation reasons •  HS-G1 supports 1.25 Gbps and 1.45 Gbps •  These two data rates are known as A & B

•  Support for a LS or a HS GEAR requires support for all GEARs below

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M-PHY Data Rates

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Low-SpeedGears-Pulse-Width-Modula0on(PWM)-Self-Clocking

High-SpeedGears-Non-Return-to-Zero(NRZ)-Smallandlargeamplitudemodes

Clock Rate Differences

•  Clock Rate A or B

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State Machine

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•  Two operating modes, •  HS-MODE •  LS-MODE

•  A data transmission (BURST) state and a MODE-specific power saving (SAVE) state

•  STALL is the SAVE state of HS-MODE •  SLEEP is the SAVE state of LS-MODE

•  HS-MODE: STALL, HS-BURST •  LS-MODE (Type-I MODULE): SLEEP, PWM-

BURST, LINE-CFG •  LS-MODE (Type-II MODULE): SLEEP, SYS-

BURST

Data Bursts •  Data transmission occurs in

BURSTs with power saving states between BURSTs

•  BURST starts from the SAVE state

•  Transition from DIF-N to DIF-P for period called PREPARE

•  Generate SYNC Pattern •  Send Marker0 followed by mix of

DATA0 - 255, Markers, FILLER •  Marker0 used for receiver

alignment, similar to SKIP ordered sets in PCIe

•  Burst ends with TAIL-OF-Burst Symbol

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HIBERN8 •  HIBERN8 state enables ultra-low power consumption, while

maintaining the configuration settings. •  A MODULE shall support HIBERN8.

•  The M-TX shall be high-impedance in HIBERN8, •  M-RX shall hold the LINE at DIF-Z.

•  Under these conditions, the M-RX is considered to be in squelch.

•  When entering HIBERN8 from LS-MODE or HS-MODE, the Protocol Layer shall not request a MODULE exit HIBERN8 before a minimum period in HIBERN8 of THIBERN8,

•  THIBERN8, is the larger of local TX_Hibern8Time_Capability and remote RX_Hibern8Time_Capability. •  Optional calculations of HIBERN8 based on the implementation

•  (see the spec for additional details)

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MIPI Universal Protocol (UniPro)

MIPI UniPro •  MIPI specification to the define protocol

used to transfer data between Devices that implement the UniPro Specification.

•  This includes definitions of data structures, such as Packets and Frames, used to convey information across the Network.

•  Flow control, error handling, power and state management, and connection services are also defined in this specification

•  UniPro version 1.61, the use of M-PHY is mandated for chip-to-chip interconnections

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Phy Adapter Layer - L1.5 •  PHY Adapter Layer is responsible for

abstracting the details of the PHY technology, thus providing a PHY-independent interface (PA_SAP) to higher protocol layers.

•  The PHY Adapter Layer provides bandwidth scalability by supporting up to four PHY Data Lanes per direction.

•  Supports Asymmetrical Data Lanes •  When multiple Data Lanes are available, they

are assumed to have identical capabilities. •  Lanes are assumed to be in the same state,

and L1.5 handles all details of how the Lanes are used autonomously.

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L1.5 Protocol

•  The L1.5 for M-PHY automates a significant part of the required steps used for Power Modes control, utilizing an L1.5-to-L1.5 communication protocol known as PACP (PHY Adapter Control Protocol).

•  PDUs (“PACP frames”) generated by L1.5 are multiplexed with the symbol stream received from L2 and can be recognized by a unique header pattern.

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L1.5 Power States and Power Modes

•  The difference between Power States and Power Modes are as follows:

•  An Application can set only a Power Mode, but cannot set a Power State

•  An Application can get a Power Mode and get a Power State •  the gettable value of a Power Mode simply reflects the value

that was set •  the gettable value of a Power State may change

spontaneously when in FastAuto_Mode or SlowAuto_Mode

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PACP Capability Exchange

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Layer 1.5 Example – PACP_PWR_REQ

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Usedforpowermodechanges

Data Link Layer – L2 •  The Data Link Layer provides reliable Links between a transmitter

and a directly attached receiver •  Multiplexes and arbitrates multiple types of data traffic (priorities) •  Data Link Layer clusters the 17-bit PA_PDU symbols into Data

Frames •  Every Data Frame consists of a 1-symbol header, a payload of up

to 144 symbols and a 2-symbol trailer including a 16-bit CRC.

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•  Network Layer is to allow data to be routed to the proper destination in a networked environment.

•  Network Layer introduces a new PDU known as a Packet •  When a Packet is passed down to L2, the Packet is

encapsulated between an L2 header and an L2 trailer to form a single L2 Frame

•  UniPro supports Networks of up to 128 Devices

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Network Layer – L3

Transport Layer L4 •  Transport Layer is the highest UniPro protocol layer •  Transport Layer mechanisms allow a single physical Packet stream

between two Devices to support multiple, independent, logical Packet streams or “Connections”.

•  Transport Layer supports multiple bidirectional Connections •  Connections can span a single hop or multiple hops using Switches

•  Switches not yet defined by the UniPro spec •  UniPro guarantees that data sent over a single Connection arrives

in the order in which it was sent

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Preemption (UniPro) •  In order to reduce delays in the transmission of high

priority Frames and to improve QoS in conjunction with upper layers, the DL Layer can insert high priority Frames within a low-priority Data Frame if the latter one is already in transmission.

•  This functionality is known as preemption of a Frame. Support of preemption functionality is optional for the transmitter, whereas the receiver shall always be able to receive preempted and non-preempted Frames.

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Preemption (UniPro) •  Uses COF – Continuation of Frame header

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ThisFrameconsistsof2fragments,thesecondfragmentstar0ngwithCOF

Universal Flash Storage (UFS)

JEDEC

UFS – Universal Flash Storage •  Universal Flash Storage – JEDEC Standard JESD220C •  Universal Flash Storage (UFS) is a simple, high performance,

mass storage device with a serial interface. •  It is primarily used in mobile systems, between host

processing and mass storage memory devices. •  M-PHY and UniPro make up the interconnect for UFS •  UFS is architected on SCSI SAM •  UFS uses the command layers from SCSI SPC and SBC

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Why UFS? 1.Be5erUserExperience:

•  Higherperformance,efficiency&responsiveness-LeadingtoInstantON,Mul0-Tasking,Fastapploadingandswapping

•  LowPower–LongerBaQerylifeevenwithlargerscreensandmul0-tasking•  SecurityandReliability–Enterpriseapplica0onsupportandSecureMobileshopping

•  SmallandScalable–Thinnerandlighterdevices

2.Easiertechnologicalintegra>on:•  SoTwarecompa0bilitywiththewidespreadSCSIframework-UFS2.0Specifica0onfollowstheSCSI

programmingmodelenablingsoTwarereuse

•  SimplerHostdesignduetothewell-definedUFSHostcontrollerinterface(UFSHCI)specifica0on•  ApartfromtheseUFS2.0requiresonlysingleUniProTransportlayerCPortanddoesnotusethebuiltin

end-to-endflowcontrolcapabili0esofUniPro.ItdoesnotrequirethelowlatencyTC1supportorPre-emp0on.Thisleadstosimplifica0onoftheMIPIUniProcontrollerdesignaswell.

3.Be5eru>liza>onofbandwidth:•  JEDECUFSisabletofullyu0lizetheduplexbandwidthprovidedbytheMIPIUniProtransport.

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UFS Architecture

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Physical Layer •  UFS interface can support multiple lanes. •  Each lane consists of a differential pair. •  Basic configuration is based on one transmit lane and

one receive lane. • Optionally, a UFS device may support two downstream

lanes and two upstream lanes. An equal number of downstream and upstream lanes shall be provided in each link. •  Links must be symmetrical

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Application Layer •  The application layer consists of the UFS Command

Set layer (UCS), the device manager and the Task Manager

•  The UCS will handle the normal commands like read, write, and so on.

•  UFS may support multiple command sets. •  UFS is designed to be protocol agnostic. This version

UFS standard uses SCSI as the baseline protocol layer.

•  A simplified SCSI command set was selected for UFS. •  UFS Native command set can be supported when it is

needed to extend the UFS functionalities. •  The Task Manager handles commands meant for

command queue control. •  The Device Manager will provide device level control

like Query Request and lower level link-layer control.

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SCSI Read Command

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SCSILevel

UTPLevel

SCSI Write Command

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SCSILevel

UTPLevel

Debugging M-PHY Problems

Debug process for Serial Protocols

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Analyzeandfindrootcause

Pickthecorrecttool

Iden0fytheLayer

Debugging M-PHY problems

•  Typically M-PHY production systems are chip to chip, no connector

•  Development systems may have SMA connections between devices

•  First challenge is to access link •  Probing Type:

•  SMA •  Multi Lead •  Midbus

•  Check electrical first before debugging protocol problem

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Probing Options

•  Identify the appropriate probing solution •  SMA •  Multi-Lead – Solder Down

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Mul0-LeadSolderDown SMA

Using the correct tool

•  Is problem related to Signal Integrity? •  Are devices physically connected? •  Are both devices providing M-PHY compliant

signaling? •  Use an Oscilloscope to verify

•  Is problem related to Connectivity •  Is a link established between the 2 devices? •  Is the data rate as expected? •  Can software see the devices –

•  for UFS, can the storage be seen? •  Use a Protocol analyzer to verify

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Which Layer is causing the problem?

•  Same principle applies regardless of MIPI M-PHY upper layer protocol

•  Identify the layer •  Performance? •  Reliability? •  Errors?

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Protocol Analyzer sees nothing? •  Is there a signal present?

•  Connect the analyzer probe output to an Oscilloscope to verify.

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•  Is there a signal present? •  Connect the analyzer probe output to an Oscilloscope to verify.

Protocol Analyzer sees nothing?

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DUT

•  Is there a signal present? •  Connect the analyzer probe output to an Oscilloscope to verify.

Protocol Analyzer sees nothing?

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DUT

Set Up Trigger • What to trigger on?

•  Depending on layer, trigger condition may vary •  Look for PACP on Boot to see initialization •  Higher level SCSI trigger for looking at software problem

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SCSIOpCode

Protocol Issues – Look at upper layers

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References • M-PHY Specification v4.0 • MIPI UniPro Specification v1.61 •  JEDEC Spec JESD220C (UFS) rev 2.1

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