draft - not for publication 14 july 2004 – itrs public conference 2004 itrs update ortc overview...

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference

2004 ITRS UpdateORTC Overview

Nodes, Chip Size, Transistors, Capacity, $ Trends

Alan Allan/Intel Corp 7/14/04 2004 ITRS Interim Status Review

[Presentation Rev Version 5b]


2004(2004 ITRS Exec. Summary and ORTC”) – it’s all

about:

• Economics + Technology…and• Customers, who Buy • Products (emulated and mapped to chips)which, though the customers don’t know or appreciate

it, need Semiconductor:• Nodes• Chip Sizes• Transistors• Capacity• $


90’s 21st Century

Semiconductor Industry

TechnologyEconomics

Semiconductor Industry

Clear Both Economics + Technology Hurdles = Growth


Wanted: CUSTOMERS, who breathe, eat, and live in…..

Materials

Semiconductor

Equipment

SemiconductorsSemiconductors

Electronic End EquipmentElectronic End Equipment

Sources: NASA.gov ; SEMI

Customer Demand

Global & Regional Political & Macro-Economic Environments

Ecosystem or Foodchain?

…and who BUY, based on varying

levels of Purchasing

Power, PRODUCTS

SemiconductorEquipm

ent

&

Mat

eria

ls


Products(As Defined by NEMI PEGs*)

* Product [Need] Emulator Groups


Drivers

MPU DSPAMS Memory

Network PortableOffice

SIP/SOC(ITRS)

Applications (NEMI)

Chips /Fabrics(ITRS)

Medical Automotive Defense

ArchitecturesA1A2A3A4

Figure 1: Potential mapping approach between NEMI and ITRS roadmaps

Source: ITRS Design TWG

SIP/SOC


Nodes


Production Ramp-up Model and Technology NodeV

olu

me

(Par

ts/M

on

th)

1K

10K

100K

Months0-24

1M

10M

100M

Alpha

Tool

12 24-12

Development Production

Beta

Tool

Production

Tool

First

Conf.

Papers

First Two Companies

Reaching Production

Vo

lum

e (W

afer

s/M

on

th)

2

20

200

2K

20K

200K

Source: 2003 ITRS - Exec. Summary Fig 2

Fig 2


Source: 2003 ITRS - Exec. Summary Table C

hp22hp32hp45hp65hp90

20182016

20152013

20122010

20092007

20062004

20032002[Actual]

Year of Production

hp130Technology Node

[DRAM] (nm)

Technology Nodes: Back to 3-year cycle

3-Year Technology Cycle2-Year Technology Cycle [1998-2002actual]

Near Term Long Term


Source: STRJ, ITRS PIDS ITWG Survey, ca. 2Q03

3-year Node-Cycle

2-year Node-Cycle

3-year Node-Cycle

2020

ITRS 2003: 2003/100(-110nm?) - 2019/16nm: Average 0.5x/2.5years

Company ACompany BCompany C

[DR

AM

Hal

f-P

itch

] [DRAM]

03 04


2003 ITRS Renewal ORTC Table Header/”Targets”:

2003 ITRS Technology Node Header (**Unchanged from 2001/2002 ITRS):Near-Term Long Term

Notes ---------------------------------- -------------------------------- -----

2003 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018 hp90 hp65 hp45 hp32 hp22

DRAM Unchanged 100 90 80 70 65 57* 50* 45 35* 32 25* 22 18*

Other ORTC Tracked Technology Trends (optional - use by TWG Tables as needed):Poly Unchanged 107 90 80 70 65 57* 50* 45 35* 32 25* 22 18*

NEW Logic M1: 120 107 95 85 76 67 60 54 48 42 38 34 30 27 24 21

UNCHANGED:

MPU Pr GL: 65 53 45 40 35 32* 28* 25 22 20* 18 16 15* 13 11 10*

MPU Ph GL: 45 37 32 28 25 22* 20* 18 16 14* 13 11 10* 9 8 7*

* Not visible in 2001 ITRS due to no annual columns between "Near Term" and "Long Term" column ranges. The 2001 ITRS Long Term columns are retained for continuity of technology nodes.

** DRAM Half-Pitch Nodes unchanged, however cell design factor improvement has been significantly delayed in the 2003 ITRS. Node timing is based on original 2001 ITRS glossary definition of 10Ku/mo manufacturing with Production-Capable Equipment and Materials.

*** Note: Logic Half-Pitch (HP) was based on Un-contacted Logic Poly HP in 2001 ITRS. In the 2003 ITRS, Logic “Metal 1” (M1) was added and correlated with IC TWG “Local Wiring” Pitch/2 [120nm/2003, plus a 3-year target cycle trend].

**

***


Chip Sizes


2003 ITRS DRAM Chip Size Model(Rev 1, 07/23/03)

0

100

200

300

400

500

600

700

1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025

Year of Introduction and Production

(mm

2)

Intro Chip Size (mm2)

Prod Chip Size (mm2)

Max Affordable Litho Field 2001 ITRS:

572mm2 (22x26)

Max Affordable Litho Field 2003 ITRS:

704mm2 (22x32)

4 chips per Max Affordable Litho Field @

572mm2 = 143mm2 (22x6.5)

512M

1G 2G 4G 8G 32G 64G16G

Bits/

chip:

256M

128G64M 128M

Bits/

chip:

256M

128G

1G 2G

4G

8G 32G 64G

16G

256G 1T

512M

Cell Area Efficiency (CAE) = 63-73%

Cell Area Efficiency (CAE) = 63%

128 90 64 45 22 1632Node: 180 11255360 8

8.0 7.5 6.011 8.0 8.0 7.0 6.0 5.0 5.06.0

Cell

Factor: 11 5.0 5.0

5 chips per Max Affordable Litho Field @

704mm2 = 141mm2 (22x6.4)


572mm2 Litho Field Size

286mm2 2 per Field Size

800mm2 Litho Field Size

MPU Chip size (mm2) – Historical Trends vs Unchanged 2001-03 ITRS Model*

1000

100

101980 1985 1990 1995 2000 2005 2010 2015 2020

CP MPU 140mm2

HP MPU 310mm2

CP Shrink 70mm2

* ITRS Design TWG MPU Transistors/Chip Model: ~2x/Node = 2x/2yrs from 1999 - 2001; then 2x/3yrs from 2001- 2016

*1999 Leading-Edge .18u CP MPU:

512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2

*1999 Leading- Edge .18u HP MPU:

2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x 5.19u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2

New: 704mm2 Litho Field Size


Transistors


Transistors – VLSI Research May’03 [source: tci030509graphicsSPCL2.xls]

Worldwide Transistor Production

1000000

10000000

1E+08

1E+09

1E+10

1E+11

1E+12

1E+13

1E+14

1E+15

1E+16

1E+17

1E+18

19

55

19

57

19

59

19

61

19

63

19

65

19

67

19

69

19

71

19

73

19

75

19

77

19

79

19

81

19

83

19

85

19

87

19

89

19

91

19

93

19

95

19

97

19

99

20

01

Un

its

RESTRICTED DATA: for access and use only w ithin your company, as per your company's agreement w ith VLSI Research Inc. Copyright © 2003 by VLSI Research Inc.

There's no slowing of Moore's Law here!

[Tra

nsis

tors

]

[1971-2003 (1e3)^(1/16yrs) = 54% Ave CAGR]


1949

1952

1955

1958

1961

1964

1967

1946

…In the beginning…Bell Labs ca. 1947

Transistors – VLSI Research May’03 [source: tci030509graphicsSPCL2.xls]

Worldwide Transistor Production

1000000

10000000

1E+08

1E+09

1E+10

1E+11

1E+12

1E+13

1E+14

1E+15

1E+16

1E+17

1E+18

19

55

19

57

19

59

19

61

19

63

19

65

19

67

19

69

19

71

19

73

19

75

19

77

19

79

19

81

19

83

19

85

19

87

19

89

19

91

19

93

19

95

19

97

19

99

20

01

Un

its

RESTRICTED DATA: for access and use only w ithin your company, as per your company's agreement w ith VLSI Research Inc. Copyright © 2003 by VLSI Research Inc.

There's no slowing of Moore's Law here!

2003

2006

2009

2012

2015

2018

2021

2000

Exa-Transistors (Et) 1e18

Tera-Transistors (Tt) 1e12

Mega-Transistors (Mt) 1e06

Giga-Transistors (Gt) 1e09

Peta-Transistors (Pt) 1e15

Zeta-Xistors (1e21)

One-a-Transistor (t) 1e00

Kilo-Transistors (Kt) 1e03

“Moore’s Law” @ 2x/1yr

Integrated Circuit (IC) …

TI & Fairchild ca. 1959

“Moore’s Law” @ 2x/1.5-2yrs

ITRS -- Near Term“Moore’s Law” @ 2x/2yrs

ITRS -- Long Term“Moore’s Law” @ 2x/3yrs

[Tra

nsis

tors

]

50Pt

You are Here!

Semico (SIA): 1997Product Units (B)Discrete 197.00Analog 25.90Other Memory 3.90Other Logic 14.80SubTotal: 241.60

SubTotal: 241.60MCU 4.20MPR 1.80DRAM 3.30Flash 0.57MPU 0.26Total: 251.73

Est. from Semico: 1997Product Transistors (Pt)Discrete 0.0002Analog 0.130Other Memory 0.98Other Logic 1.78SubTotal: 2.88

SubTotal: 2.88MCU 0.84MPR 0.36DRAM 42.9Flash 1.71MPU 0.78Total: 49.47

[1971-2019 (1e3)^(1/16yrs) = 54% Ave CAGR]


Capacity


Technology Node Compared to Actual Wafer Production Capacity Technology Node Distribution

Fig 3F

eatu

re S

ize

(Hal

f P

itch)

(m

)

Year

1997 1998 1999 2000 2001 2002 2003 20062005

Fea

ture

Siz

e o

f T

ech

no

log

y

0.01

0.1

1

10

W.P.CW.P.CW.P.CW.P.CW.P.CW.P.C >0.7m

0.7-0.4m

0.4-0.3m

0.3- 0.2m

<0.16m

0.2- 0.16m

Source: SICAS**W.P.C.= Total Worldwide Wafer Production Capacity (Relative Value *)

W.P.C* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2003. The area of each of the production capacity bars corresponds to the relative share of the Total MOS IC production start silicon area for that range of the feature size (y-axis). Data is based upon capacity if fully utilized.

<0.

4m

<0.

4m

<0.

3m

<0.

3m

<0.

2m

<0.

2m

<0.

16m

2004 2007

ITRS Technology Node

25% 25

%

25% 25

%

** Source: Semiconductor Industry Capacity Statistics (SICAS) – collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2003

Source: 2003 ITRS - Exec. Summary Fig 3

hp350Actual hp90 hp65hp250

Actualhp180Actual

hp130Actual

3-Yr3-Yr 2-Yr

SIA/SICAS Data:1-yr delay from ITRS

Timing to 25% of MOS IC Capacity

25%?

hp127nm

hp180nm

hp255nm

hp360nm

hp510nm

hp720nm

hp90nm

<0.11um F’cast


ISMT/IEM [Semico] IC Product Technology Profile

140nm

180nm

255nm

360nm

650nm

690nm

820nm

225nm

770nm

910nm

127nm

90nm

65nm

45nm

290nm

400nm

560nm

460nm

* SICAS Most Leading Edge Node Range** = 25-30% of MOS IC Area, Actual ** Examples: “180nm” = 0.22u-0.18u-0.15u; “130nm” = 0.15u-0.13u-0.11u; “90nm” = 107nm-90nm-75nm

SICAS Node*

>25% of MOS IC Capacity

2003 ITRS hpXX (Actual);PrGl ; PhGL

Leading Edge Mfg Roadmap “Node”

1994 1995 1996 1997 1998 1999 2000 2001 2002 2003

1.00

0.40

0.10

0.20

OIC: EPROM; Mass Storage; Gate Arrays; Voice and Other; EEPROM; Std Logic; Analog / Linear

LEM: DRAM Flash LEL: MPU DSP OLE: Graphics ; Std Cell; PLD; MROM; Chipsets; SRAM; Comm; MCU

LEM, LEL L.EdgeAverage

All Leading Edge

Average

Other IC Average


$, Gestalt


World Electronics, Semi, Tools, Si Area, #Fabs, Wafer Units vs. GWP ($B)

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+0519

58

1960

1962

1964

1966

1968

1970

1972

1974

1976

1978

1980

1982

1984

1986

1988

1990

1992

1994

1996

1998

2000

2002

2004

2006

Bil

ion

Do

llar

s ($

B);

Sil

ico

n S

q.I

n.

(Msi

/1e4

);

#Waf

ers

(w /

NP

W) (

Mu

/1e4

)

Tool Sales ($B) Chip Sales ($B) Electronics Sales ($B)GWP ($B) Silicon Sq. Inches (Msi/1e4) Silicon Wafers (Mu/1e4) Total # Fabs (20Kwspm - #/1e04)

Source: VLSIR, April, Sept 2001

History <- 2000 -> F'cast

0-1%?

8.26%

29%47%

4.2%2.8%

47%

1%

10%

7.5% 6-8%?

7.5-10%?

15.5 %

15.5 %

5-8%?

Macro Overview – GWP, Revenue, Capacity DemandSnapshot As of 10/23/02

USA GDP AVE ~3-4%

2010

2020

$

$

$

$10% CAGR?

1 Tera-Dollar

‘00 WAS:


Hi-Tech Revenues Worldwide

10

100

1000

10000

100000

1000000

10000000

1960

1962

1964

1966

1968

1970

1972

1974

1976

1978

1980

1982

1984

1986

1988

1990

1992

1994

1996

1998

2000

(Re

ve

nu

es

in $

M)

Electronics

Chips

Chip Equipment

RESTRICTED DATA: for access and use only w ithin your company, as per your company's agreement w ith VLSI Research Inc.Copyright © 2003 by VLSI Research Inc.

Chips and Equipment have been tracking Electronics growth rates since

1995, albeit with higher volatility.

[VLSIR ca May’03]

[~7.5% CAGR]

[~15.5% CAGR]

Past < -- 2002‘02 WAS:


Revenue

1000

10000

100000

1000000

10000000

1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010

Year

($M

)

Semiconductor Equipment Semiconductor Electronics

Sources: VLSI Research (1990-2002), Electronics Consultant (2003-2008)

Past Future

VLSIR History:CAGR ’90-’00 = 6.8%CAGR ’90-’01 = 5.6%

Estimate:CAGR’02-’08 = 5.8%

10% CAGR

7% -7.5%CAGR


ITRS Ave Cost per Function vs. Industry Ave Price per Functionvs. Estimated #Industry Transistors (Final Packaged Unit)

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020

Year

Mic

roc

en

ts

DRAM cost/bit -intro

DRAM cost/bit -prod

Cost-perf MPU -intro

Cost-perf MPU -prod

High-perf MPU -prod

Past <---> Future

1e+19

1e+18

1e+20

1e+17

1e+16

1e+15

1e+14

1e+13

1e+12

Micro- Dollar (u$)

Sources: Past: VLSI Research ca May '03 Future: ITRS

Nano- Dollar (n$)

Peta-Transistors (Pt)

Tera-Transistors (Tt)

MPU Ave Price/Xistor

(Estimated @ 65%Gross

Margin)

(@ 35% Ave Gross

(@ 35% Ave Gross

(@ 65% Ave Gross

(@ 65% Ave Gross

(@ 65% Ave Gross

DRAM Ave Price/bit (VLSIR) Industry Ave

Price/Xistor (VLSIR)

-29.3%ave CARR

Industry Est. Xistor Demand

(VLSIR)

46.8%CAGR

66.8%CAGR

Milli- Dollar (m$)

# Transistors

Exa-Transistors (Et)

Zetta-Xistors (Zt)

46.8% - 66.8 % CAGR ??

DRAM Ave Price/Bit (Estimated @ 35%

Gross Margin)

$

$

1e+21

2019/16nm Node $1T, ~10% CAGR from $145B/1999.18u 90n 45n 22n 16n.36u

m1.4u .72u5.6u 2.8uNode:

-25.0%ave CARR'75-'99 then

-29.3%ave

54.6%aveCAGR

$

$


What Can History Teach Us?

Portability & Connectivity WaveMultiple Wireless Devices

Fuel Cells, Rich Media

Source: Semico Research Corp, May’04

Internet WaveInternet Boom, Cell Phones

Digital Content

Personal ComputingAnalog WaveTV, VCR

20202020

$1T$1T

$0.5T$0.5T55thth Wave? Wave?

66thth Wave? Wave?

77thth Wave? Wave?

Growing to $1T will require a few more “Waves” of emerging Applications, Economies, and Customers!

(and, yes, a couple more wafer generations or equivalent productivity improvements!)

7.5%10%

3” / 4 ” 5” / 6 ” 200mm 300mm “450mm” “675mm”

YouAre

Here!

Total Semi 2003: $166BSource SIA/WSTS

To

tal S

emi R

even

ue

To

tal

Sem

i R

even

ue

Digital Wave


Summary• ITRS Node timing [DRAM Half-Pitch based] is based on the first

two leading-edge companies beginning manufacturing ramp• ITRS Nodes [DRAM Half-Pitch based] are forecast to slow from the

present 2-year to a 3-year pace after 2003, and slowing design factors are causing density to double only every technology node

• Leading-edge DRAM Product first production start Chip Sizes are targeted to remain flat at about 140mm2 for affordability, but will shrink further in size

• To keep chip sizes affordable [ie “flat”], the ITRS target “Moore’s Law” DRAM functionality per chip is slowing from 2x/1.5-2yrs to 2x/2.5-3yrs

• Leading-edge volume Capacity Demand, as monitored by SICAS, is on the same 2-year pace as the ITRS nodes, with the 130nm technology range (<150nm to >110nm) reaching >25% of MOS IC capacity in 2003


Summary (cont.)

• There appears to be no slowing in the overall demand for transistors, which has averaged over 50% compound growth since the 70’s – a pace which increases demand 1000 times every 16 years

• To keep the cost per transistor and per bit affordable to end-use applications and consumers, the cost to manufacture transistors inside finished semiconductor devices must decrease at a -29% compound rate

• The ITRS targets the affordable cost per function reduction target is based on a historical target of -29%, and if this cost reduction can be maintained as demand for total transistors grows at a 53-55% rate, the revenue of the industry could grow at 7.5-10% per year, reaching $1T by 2019-2025 from the 1999 level of $145B

• Of course, growing to $1T will require more emerging “Waves” of demand and a couple more wafer generations or equivalent productivity improvements!


2003/2004 ITRS Technology Node Trends

2003 ITRS Technology Trends - 1/2 Pitch

1

10

100

1000

1995 2000 2005 2010 2015 2020

Year

Te

ch

no

log

y N

od

e -

DR

AM

Ha

lf-P

itc

h (

nm

)

DRAM 1/2 Pitch - Node

MPU M1 1/2 Pitch

2003 ITRS Period: Near-term: 2003-2009; Long-term: 2010-2018

hp90

hp65

hp45

hp32

hp22

2-year Node Cycle

3-year Node Cycle

Figure 7 2003 ITRS—Half Pitch Trends

[2004 Update – Unchanged]


2003/2004 ITRS Technology Node Trends

Figure 8 2003 ITRS—Gate Length Trends

2003 ITRS Technology Trends - Gate Length

1

10

100

1000

1995 2000 2005 2010 2015 2020

Year

Ga

te L

en

gth

(n

m)

MPU Hi-PerformanceGate Length - Printed

MPU Hi-PerformanceGate Length - Physical

Nano-technology (<100nm) Era Begins - 1999

2003 ITRS Period: Near-term: 2003-2009; Long-term: 2010-2018

2-year Node Cycle

3-year Node Cycle



Table 1a Product Generations and Chip Size Model Technology Nodes—Near-term Years

Year of Production 2003 2004 2005 2006 2007 2008 2009

Technology Node hp90 hp65

DRAM ½ Pitch (nm) 100 90 80 70 65 57 50

MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 120 107 95 85 76 67 60

MPU/ASIC ½ Pitch (nm) (Un-contacted Poly) 107 90 80 70 65 57 50

MPU Printed Gate Length (nm) †† 65 53 45 40 35 32 28

MPU Physical Gate Length (nm) 45 37 32 28 25 22 20

ASIC/Low Operating Power Printed Gate Length (nm) †† 90 75 65 53 45 40 35

ASIC/Low Operating Power Physical Gate Length (nm) 65 53 45 37 32 28 25



Table 1b Product Generations and Chip Size Model Technology Nodes—Long-term Years

Year of Production 2010 2012 2013 2015 2016 2018

Technology Node hp45 hp32 hp22

DRAM ½ Pitch (nm) 45 35 32 25 22 18

MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 54 42 38 30 27 21

MPU/ASIC ½ Pitch (nm) (Un-contacted Poly) 45 35 32 25 22 18

MPU Printed Gate Length (nm) †† 25 20 18 14 13 10

MPU Physical Gate Length (nm) 18 14 13 10 9 7

ASIC/Low Operating Power Printed Gate Length (nm) ††

32 25 22 18 16 13

ASIC/Low Operating Power Physical Gate Length (nm)

22 18 16 13 11 9



ISMT IEM Wafer Generations

Sc. “C” - ITRS 2001 (3/2/3 year)

300mm 530 wo 450mm

360370

730

133mm 540 wo 200mm

370

835

89mm 540 wo 133mm

770

200mm 430 wo 300mm

340

745

430 200mm@20Kwspm= 32Bcm2

200 133mm@20Kwspm= 6.7Bcm2=89 equiv200mm“fabs”


540 89mm@20Kwspm

= 8Bcm2


160 133mm@20Kwspm= 12Bcm2=71 equiv300mm“fabs”

Lead-Time to Evaluate Potential Solutions: ~7yrs ahead of 2011-’12

Source: International SEMATECH Industry Economic Model (IEM) Version 3 ca 2001; “High Scenario”; VLSI Research, Inc.

xxx = # 20Kwspm Fabs without next Wafer Generations

draft - not for publication 14 july 2004 – itrs public conference 2004 itrs update ortc overview...

Documents

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