dual 10-bit, 20msps, 3v, low-power adc with internal ... · general description the max1184 is a...

General DescriptionThe MAX1184 is a 3V, dual 10-bit analog-to-digital con-verter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving two pipelined, 9-stageADCs. The MAX1184 is optimized for low-power, high-dynamic performance applications in imaging, instru-mentation, and digital communication applications. ThisADC operates from a single 2.7V to 3.6V supply, con-suming only 105mW while delivering a typical signal-to-noise ratio (SNR) of 59.5dB at an input frequency of7.5MHz and a sampling rate of 20Msps. The T/H driveninput stages incorporate 400MHz (-3dB) input amplifiers.The converters may also be operated with single-endedinputs. In addition to low operating power, the MAX1184features a 2.8mA sleep mode as well as a 1µA power-down mode to conserve power during idle periods.

An internal 2.048V precision bandgap reference setsthe full-scale range of the ADC. A flexible referencestructure allows the use of the internal or an externallyderived reference, if desired for applications requiringincreased accuracy or a different input voltage range.

The MAX1184 features parallel, CMOS-compatiblethree-state outputs. The digital output format is set totwo’s complement or straight offset binary through a sin-gle control pin. The device provides for a separate out-put power supply of 1.7V to 3.6V for flexible interfacing.The MAX1184 is available in a 7mm x 7mm, 48-pinTQFP package, and is specified for the extendedindustrial (-40°C to +85°C) temperature range.

Pin-compatible higher speed versions of the MAX1184are also available. See Table 2 at end of data sheet for alist of pin-compatible versions. Refer to the MAX1180data sheet for 105Msps, the MAX1181 data sheet for80Msps, the MAX1182 data sheet for 65Msps, and theMAX1183 data sheet for 40Msps. In addition to thesespeed grades, this family includes a 20Msps multi-plexed output version (MAX1185), for which digital datais presented time-interleaved on a single, parallel 10-bitoutput port.

ApplicationsHigh-Resolution Imaging

I/Q Channel Digitization

Multchannel IF Undersampling

Instrumentation

Video Application

Features♦ Single 3V Operation♦ Excellent Dynamic Performance:

59.5dB SNR at fIN = 7.5MHz 74dB SFDR at fIN = 7.5MHz

♦ Low Power: 35mA (Normal Operation)2.8mA (Sleep Mode)1µA (Shutdown Mode)

♦ 0.02dB Gain and 0.25° Phase Matching (typ)♦ Wide ±1VP-P Differential Analog Input

Voltage Range♦ 400MHz -3dB Input Bandwidth♦ On-Chip 2.048V Precision Bandgap Reference♦ User-Selectable Output Format—Two’s

Complement or Offset Binary♦ 48-Pin TQFP Package with Exposed Paddle for

Improved Thermal Dissipation♦ Evaluation Kit Available

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Dual 10-Bit, 20Msps, 3V, Low-Power ADC withInternal Reference and Parallel Outputs

________________________________________________________________ Maxim Integrated Products 1

D1AD0AOGNDOVDD

OVDD

OGNDD0BD1BD2BD3BD4BD5B

COMVDD

GNDINA+INA-VDD

GNDINB-INB+GNDVDD

CLK

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

48 TQFP-EP

MAX1184

EP

GND

V DD

GND

V DD

T/B

SLEE

P PD OE D9B

D8B

D7B

D6B

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

REFN

REFP

REFI

NRE

FOUT

D9A

D8A

D7A

D6A

D5A

D4A

D3A

D2A

Pin Configuration

19-2174; Rev 1; 7/06

Ordering InformationPART TEMP RANGE PIN-PACKAGE

MAX1184ECM -40°C to +85°C 48 TQFP-EP*

MAX1184ECM+ -40°C to +85°C 48 TQFP-EP*

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*EP = Exposed paddle.

+Denotes lead-free package.

NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGE IS REPLACED BY A “+” SIGN.

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ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(VDD = 3V, OVDD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX,unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

VDD, OVDD to GND...............................................-0.3V to +3.6VOGND to GND.......................................................-0.3V to +0.3VINA+, INA-, INB+, INB- to GND ...............................-0.3V to VDDREFIN, REFOUT, REFP, REFN, CLK,

COM to GND ..........................................-0.3V to (VDD + 0.3V)OE, PD, SLEEP, T/B, D9A–D0A,

D9B–D0B to OGND .............................-0.3V to (OVDD + 0.3V)

Continuous Power Dissipation (TA = +70°C)48-Pin TQFP-EP (derate 30.4mW/°C above +70°C).......................................................................2430mW

Operating Temperature Range ...........................-40°C to +85°CJunction Temperature ......................................................+150°CStorage Temperature Range .............................-60°C to +150°CLead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity INL fIN = 7.5MHz ±0.5 ±1.5 LSB

Differential Nonlinearity DNL fIN = 7.5MHz, no missing codes guaranteed ±0.25 ±1.0 LSB

Offset Error < ±1 ±1.8 % FS

Gain Error 0 ±2 % FS

ANALOG INPUT

Differential Input VoltageRange

VDIFF Differential or single-ended inputs ±1.0 V

Common-Mode Input VoltageRange

VCMVDD/2± 0.5

V

Input Resistance RIN Switched capacitor load 100 kΩInput Capacitance CIN 5 pF

CONVERSION RATE

Maximum Clock Frequency fCLK 20 MHz

Data Latency 5ClockCycles

DYNAMIC CHARACTERISTICS

fINA or B = 7.5MHz, TA = +25°C 57.3 59.5Signal-to-Noise Ratio(Note 3)

SNRfINA or B = 12MHz 59.4

dB

fINA or B = 7.5MHz, TA = +25°C 57 59.4Signal-to-Noise and Distortion(Note 3)

SINADfINA or B = 12MHz 59.2

dB

fINA or B = 7.5MHz, TA = +25°C 64 74Spurious-Free Dynamic Range(Note 3)

SFDRfINA or B = 12MHz 72

dBc

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ELECTRICAL CHARACTERISTICS (continued)(VDD = 3V, OVDD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX,unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)


fINA or B = 7.5MHz -74Third-Harmonic Distortion(Note 3)

HD3fINA or B = 12MHz -72

dBc

fINA or B = 7.5MHz, TA = +25°C -72 -64Total Harmonic Distortion(First 4 harmonics) (Note 3)

THDfINA or B = 12MHz -71

dBc

fINA or B = 11.985MHz at -6.5dBFSIntermodulation Distortion IMD

fI N A o r B = 12.893M H z at - 6.5d BFS ( N ote 4) -76 dBc

Small-Signal Bandwidth Input at -20dBFS, differential inputs 500 MHz

Full-Power Bandwidth FPBW Input at -0.5dBFS, differential inputs 400 MHz

Aperture Delay tAD 1 ns

Aperture Jitter tAJ 2 psRMS

Overdrive Recovery Time For 1.5 x full-scale input 2 ns

Differential Gain ±1 %

Differential Phase ±0.25 d egr ees

Output Noise INA+ = INA- = INB+ = INB- = COM 0.2 LSBRMS

INTERNAL REFERENCE

Reference Output Voltage REFOUT2.048±3%

V

Reference TemperatureCoefficient

TCREF 60 ppm/°C

Load Regulation 1.25 mV/mA

BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V)

REFIN Input Voltage VREFIN 2.048 V

Positive Reference OutputVoltage

VREFP 2.012 V

Negative Reference OutputVoltage

VREFN 0.988 V

Differential Reference OutputVoltage Range

∆VREF ∆VREF = VREFP - VREFN 0.95 1.024 1.10 V

REFIN Resistance RREFIN >50 MΩ

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ELECTRICAL CHARACTERISTICS (continued)(VDD = 3V, OVDD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a10kΩ resistor, VIN = 2VP-P (differential with respect to. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN toTMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)


Maximum REFP, COM SourceCurrent

ISOURCE 5 mA

Maximum REFP, COM SinkCurrent

ISINK -250 µA

Maximum REFN Source Current ISOURCE 250 µA

Maximum REFN Sink Current ISINK -5 mA

UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM)

REFP, REFN Input ResistanceRREFP,RREFN

Measured between REFP and COM, andREFN and COM

4 kΩ

Differential Reference InputVoltage

∆VREF ∆VREF = VREFP - VREFP1.024±10%

V

COM Input Voltage VCOMVDD/2±10%

V

REFP Input Voltage VREFPV C OM +

∆V RE F / 2V

REFN Input Voltage VREFNV C OM -

∆V RE F / 2V

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B))

CLK 0.8 x VDDInput High Threshold VIH

PD, OE, SLEEP, T/B 0.8 x OVDDV

CLK 0.2 x VDDInput Low Threshold VIL

PD, OE, SLEEP, T/B 0.2 x OVDDV

Input Hysteresis VHYST 0.1 V

IIH VIH = OVDD or VDD (CLK) ±5Input Leakage

IIL VIL = 0V ±5µA

Input Capacitance CIN 5 pF

DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)

Output Voltage Low VOL ISINK = 200µA 0.2 V

Output Voltage High VOH ISOURCE = 200µA OVDD - 0.2 V

Three-State Leakage Current ILEAK OE = OVDD ±10 µA

Three-State Output Capacitance COUT OE = OVDD 5 pF

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ELECTRICAL CHARACTERISTICS (continued)(VDD = 3V, OVDD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a10kΩ resistor, VIN = 2VP-P (differential with respect to. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN toTMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)


POWER REQUIREMENTS

Analog Supply Voltage Range VDD 2.7 3.0 3.6 V

Output Supply Voltage Range OVDD 1.7 2.5 3.6 V

Operating, fINA or B = 7.5MHz at -0.5dBFS 35 50

Sleep mode 2.8mA

Analog Supply Current IVDD

Shutdown, clock idle, PD = OE = OVDD 1 15 µA

Operating, CL = 15pF, fINA or B = 7.5MHz at-0.5dBFS

3.8 mA

Sleep mode 100Output Supply Current IOVDD

Shutdown, clock idle, PD = OE = OVDD 2 10µA

Operating, fINA or B = 7.5MHz at -0.5dBFS 105 150

Sleep mode 8.4mW

Power Dissipation PDISS

Shutdown, clock idle, PD = OE = OVDD 3 45 µW

Offset ±0.2 mV/VPower-Supply Rejection Ratio PSRR

Gain ±0.1 %/V

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid tDO Figure 3 (Note 5) 5 8 ns

Output Enable Time tENABLE Figure 4 10 ns

Output Disable Time tDISABLE Figure 4 1.5 ns

CLK Pulse Width High tCH Figure 3, clock period: 50ns 25 ± 7.5 ns

CLK Pulse Width Low tCL Figure 3, clock period: 50ns 25 ± 7.5 ns

Wake up from sleep mode (Note 6) 0.51Wake-Up Time tWAKE

Wake up from shutdown (Note 6) 1.5µs

CHANNEL-TO-CHANNEL MATCHING

Crosstalk fINA or B = 7.5MHz at -0.5dBFS -70 dB

Gain Matching fINA or B = 7.5MHz at -0.5dBFS 0.02 ±0.2 dB

Phase Matching fINA or B = 7.5MHz at -0.5dBFS 0.25 d eg r ees

Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale

input voltage range. Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is

6dB or better, if referenced to the two-tone envelope.Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.

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6 _______________________________________________________________________________________

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 2 3 41 5 6 7 98 10

FFT PLOT CHA (DIFFERENTIAL INPUT,8192-POINT DATA RECORD)

MAX

1184

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1

ANALOG INPUT FREQUENCY (MHz)

AMPL

ITUD

E (d

B)

fCLK = 20.0006MHzfINA = 5.9743MHzfINB = 7.5344MHzAINA = -0.525dBFS

HD3

HD2

CHA

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 2 3 41 5 6 7 98 10

FFT PLOT CHB (DIFFERENTIAL INPUT,8192-POINT DATA RECORD)

MAX

1184

toc0

2


AMPL

ITUD

E (d

B)

fCLK = 20.0006MHzfINA = 5.9743MHzfINB = 7.5244MHzAINB = -0.462dBFS

HD3

HD2

CHB

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 2 3 41 5 6 7 98 10

FFT PLOT CHA (DIFFERENTIAL INPUT,8192-POINT DATA RECORD)

MAX

1184

toc0

3


AMPL

ITUD

E (d

B)

fCLK = 20.0006MHzfINA = 7.5344MHzfINB = 11.9852MHzAINA = -0.489dBFS

HD3

HD2

CHA

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 2 3 41 5 6 7 98 10

FFT PLOT CHB (DIFFERENTIAL INPUT,8192-POINT DATA RECORD)

MAX

1184

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4


AMPL

ITUD

E (d

B)

fCLK = 20.0006MHzfINA = 7.5344MHzfINB = 11.9852MHzAINB = -0.471dBFS

HD3

HD2

CHB

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 4 6 82 10 12 14 1816 20

TWO-TONE IMD PLOT DIFFERENTIALINPUT, 8192-POINT DATA RECORD

MAX

1184

toc0

5


AMPL

ITUD

E (d

B)

IM2 IM3IM3

fCLK = 20.0006MHzfIN1 = 11.9852MHzfIN2 = 12.8934MHzAIN1 = AIN2 = -6.5dBFS

fIN2

fIN1

57

56

59

58

60

61

0 10 20 30 40 50

SIGNAL-TO-NOISE RATIO vs.ANALOG INPUT FREQUENCY

MAX

1184

toc0

6


SNR

(dB)

CHA

CHB

61

60

59

58

57

560 10 20 30 40 50

SIGNAL-TO-NOISE PLUS DISTORTIONvs. ANALOG INPUT FREQUENCY

MAX

1184

toc0

7


SINA

D (d

B)

CHB

CHA-73

-75

-77

-71

-67

-69

-65

-63

TOTAL HARMONIC DISTORTION vs.ANALOG INPUT FREQUENCY

MAX

1184

toc0

8


THD

(dBc

)

0 10 20 30 40 50

CHB

CHA

60

64

72

68

76

80

SPURIOUS-FREE DYNAMIC RANGE vs.ANALOG INPUT FREQUENCY

MAX

1184

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9


SFDR

(dBc

)

0 10 20 30 40 50

CHA

CHB

Typical Operating Characteristics(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 20MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.)

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_______________________________________________________________________________________ 7

-8

-4

-6

0

-2

4

2

6

1 10 100 1000

FULL-POWER INPUT BANDWIDTH vs.ANALOG INPUT FREQUENCY, SINGLE-ENDED

MAX

1184

toc1

0


GAIN

(dB)

-8

-4

-6

0

-2

4

2

6

1 10 100 1000

SMALL-SIGNAL INPUT BANDWIDTH vs.ANALOG INPUT FREQUENCY, SINGLE-ENDED

MAX

1184

toc1

1


GAIN

(dB)

VIN = 100mVP-P

35

45

40

55

50

60

65

-20 0

SIGNAL-TO-NOISE RATIO vs.ANALOG INPUT POWER (fIN = 7.5344MHz)

MAX

1184

toc1

2

ANALOG INPUT POWER (dBFS)

SNR

(dB)

-12-16 -8 -4

35

45

40

55

50

60

65

-20 0

SIGNAL-TO-NOISE PLUS DISTORTION vs.ANALOG INPUT POWER (fIN = 7.5344MHz)

MAX

1184

toc1

3


SINA

D (d

B)

-12-16 -8 -4-78

-74

-66

-70

-62

-58

-20 -12-16 -8 -4 0

TOTAL HARMONIC DISTORTION vs.ANALOG INPUT POWER (fIN = 7.5344MHz)

MAX

1184

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4


THD

(dBc

)

50

40

60

80

70

90

100

-20 -12-16 -8 -4 0

SPURIOUS-FREE DYNAMIC RANGE vs.ANALOG INPUT POWER (fIN = 7.5344MHz)

MAX

1184

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5


SFDR

(dBc

)

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 256128 384 512 640 768 896 1024

INTEGRAL NONLINEARITY

MAX

1184

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6

DIGITAL OUTPUT CODE

INL

(LSB

)

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 256128 384 512 640 768 896 1024

DIFFERENTIAL NONLINEARITY

MAX

1184

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7

DIGITAL OUTPUT CODE

DNL

(LSB

)

-0.1

0.1

0

0.3

0.2

0.4

0.5

0.6

-40 85

GAIN ERROR vs. TEMPERATURE

MAX

1184

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8

TEMPERATURE (°C)

GAIN

ERR

OR (%

FS)

10-15 35 60

CHB

CHA

Typical Operating Characteristics (continued)(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 20MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.)

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-0.4

-0.2

-0.3

0

-0.1

0.1

-40 85

OFFSET ERROR vs. TEMPERATURE

MAX

1184

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9

TEMPERATURE (°C)

OFFS

ET E

RROR

(%FS

)

10-15 35 60

CHB

CHA31

32

34

33

35

36

2.70 3.002.85 3.15 3.30 3.45 3.60

ANALOG SUPPLY CURRENT vs.ANALOG SUPPLY VOLTAGE

MAX

1184

toc2

0

VDD (V)

I VDD

(mA)

28

30

34

32

36

38

-40 10-15 35 60 85

ANALOG SUPPLY CURRENT vs.TEMPERATURE

MAX

1184

toc2

1

TEMPERATURE (°C)

I VDD

(mA)

0

0.04

0.12

0.08

0.16

0.20

2.70 3.002.85 3.15 3.30 3.45 3.60

ANALOG POWER-DOWN CURRENTvs. ANALOG SUPPLY VOLTAGE

MAX

1184

toc2

2

VDD (V)

I VDD

(µA)

OE = PD = OVDD

50

56

68

62

74

80

35 40 45 50 55 60 65

SNR/SINAD, -THD/SFDR vs.CLOCK DUTY CYCLE

MAX

1184

toc2

3

CLOCK DUTY CYCLE (%)

SNR/

SINA

D, -T

HD/S

FDR

(dB,

dBc

)

SFDR fINA/B = 7.5344MHz

-THD

SNR

SINAD

2.0040

2.0050

2.0070

2.0060

2.0080

2.0090

2.70 3.002.85 3.15 3.30 3.45 3.60

INTERNAL REFERENCE VOLTAGEvs. ANALOG SUPPLY VOLTAGE

MAX

1184

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4

VDD (V)

V REF

OUT (

V)


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1.990

2.000

1.995

2.005

2.010

2.015

-40 85

INTERNAL REFERENCE VOLTAGEvs. TEMPERATURE

MAX

1184

toc2

5

TEMPERATURE (°C)

V REO

UT (V

)

10-15 35 600

21,000

14,000

7,000

28,000

35,000

42,000

49,000

56,000

63,000

70,000OUTPUT NOISE HISTOGRAM (DC INPUT)

MAX

1184

toc2

6

DIGITAL OUTPUT CODE

COUN

TS

64,515

N

869

N-1

152

N+1

0

N+2

0

N-2


Pin Description

PIN NAME FUNCTION

1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.

2, 6, 11, 14, 15 VDDAnalog Supply Voltage. Bypass each pin to GND with a 0.1µF capacitor. The analog supplyaccepts an input range of 2.7V to 3.6V.

3, 7, 10, 13, 16 GND Analog Ground

4 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.

5 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.

8 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.

9 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.

12 CLK Converter Clock Input

17 T/BT/B selects the ADC digital output format.High: Two’s complement.Low: Straight offset binary.

18 SLEEPSleep Mode Input.High: Deactivates the two ADCs, but leaves the reference bias circuit active.Low: Normal operation.

19 PDPower-Down Input.High: Power-down modeLow: Normal operation

20 OEOutput Enable Input.High: Digital outputs disabledLow: Digital outputs enabled

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Pin Description (continued)

PIN NAME FUNCTION

21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B

22 D8B Three-State Digital Output, Bit 8, Channel B








30 D0B Three-State Digital Output, Bit 0 (LSB), Channel B

31, 34 OGND Output Driver Ground

32, 33 OVDDOutput Driver Supply Voltage. Bypass each pin to OGND with a 0.1µF capacitor. The outputdriver supply accepts an input range of 1.7V to 3.6V.

35 D0A Three-State Digital Output, Bit 0 (LSB), Channel A

36 D1A Three-State Digital Output, Bit 1, Channel A








44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A

45 REFOUTInternal Reference Voltage Output. May be connected to REFIN through a resistor or a resistordivider.

46 REFIN Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a >1nF capacitor.

47 REFPPositive Reference Input/Output. Conversion range is ± (VREFP - VREFN). Bypass to GND with a> 0.1µF capacitor.

48 REFNNegative Reference Input/Output. Conversion range is ± (VREFP - VREFN). Bypass to GND witha > 0.1µF capacitor.

— EP Exposed Pad. Connect to analog ground.

Detailed DescriptionThe MAX1184 uses a 9-stage, ful ly-differentialpipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consump-tion. Samples taken at the inputs move progressivelythrough the pipeline stages every half clock cycle.Counting the delay through the output latch, the clock-cycle latency is five clock cycles.

1.5-bit (2-comparator) flash ADCs convert the held-input voltages into a digital code. The digital-to-analog

converters (DACs) convert the digitized results backinto analog voltages, which are then subtracted fromthe original held input signals. The resulting error sig-nals are then multiplied by two and the residues arepassed along to the next pipeline stages, where theprocess is repeated until the signals have beenprocessed by all nine stages. Digital error correctioncompensates for ADC comparator offsets in each ofthese pipeline stages and ensures no missing codes.

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______________________________________________________________________________________ 11

VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)

T/HVOUTx2Σ

FLASHADC DAC

1.5 BITS

10

VINB

VIN

STAGE 1 STAGE 2

D9B–D0B

DIGITAL CORRECTION LOGIC

STAGE 8 STAGE 9

2-BIT FLASHADC

T/H

T/HVOUTx2Σ

FLASHADC DAC

1.5 BITS

10

VINB

STAGE 1 STAGE 2

D9B–D0B

DIGITAL CORRECTION LOGIC

STAGE 8 STAGE 9

2-BIT FLASHADC

T/H

Figure 1. Pipelined Architecture—Stage Blocks

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Input Track-and-Hold (T/H) CircuitsFigure 2 displays a simplified functional diagram of theinput track-and-hold (T/H) circuits in both track-and-hold mode. In track mode, switches S1, S2a, S2b, S4a,S4b, S5a, and S5b are closed. The fully differential cir-cuits sample the input signals onto the two capacitors(C2a and C2b) through switches S4a and S4b. S2a and

S2b set the common mode for the amplifier input, andopen simultaneously with S1, sampling the input wave-form. Switches S4a and S4b are then opened beforeswitches S3a and S3b, connect capacitors C1a andC1b to the output of the amplifier, and switch S4c isclosed. The resulting differential voltages are held oncapacitors C2a and C2b. The amplifiers are used tocharge capacitors C1a and C1b to the same valuesoriginally held on C2a and C2b. These values are thenpresented to the first-stage quantizers and isolate thepipelines from the fast-changing inputs. The wide inputbandwidth T/H amplifiers allow the MAX1184 to track-and-sample/hold analog inputs of high frequencies (>Nyquist). The ADC inputs (INA+, INB+, INA-, and INB-)can be driven either differentially or single-ended.Match the impedance of INA+ and INA-, as well asINB+ and INB- and set the common-mode voltage tomidsupply (VDD/2) for optimum performance.

Analog Inputs and ReferenceConfigurations

The full-scale range of the MAX1184 is determined by theinternally generated voltage difference between REFP(VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). Thefull-scale range for both on-chip ADCs is adjustablethrough the REFIN pin, which is provided for this purpose.

REFOUT, REFP, COM (VDD/2), and REFN are internallybuffered low-impedance outputs.

The MAX1184 provides three modes of reference operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, connect the internal refer-ence output REFOUT to REFIN through a resistor (e.g.,10kΩ) or resistor-divider, if an application requires areduced full-scale range. For stability and noise filteringpurposes, bypass REFIN with a >10nF capacitor toGND. In internal reference mode, REFOUT, COM,REFP, and REFN become low-impedance outputs.

In buffered external reference mode, adjust the refer-ence voltage levels externally by applying a stable andaccurate voltage at REFIN. In this mode, COM, REFP,and REFN become outputs. REFOUT may be left openor connected to REFIN through a >10kΩ resistor.

In unbuffered external reference mode, connect REFINto GND. This deactivates the on-chip reference buffersfor REFP, COM, and REFN. With their buffers shutdown, these nodes become high impedance and maybe driven through separate external reference sources.


12 ______________________________________________________________________________________

S3b

S3a

COM

S5b

S5a

INB+

INB-

S1

OUT

OUT

C2a

C2b

S4c

S4a

S4b C1b

C1a

INTERNALBIAS

INTERNALBIAS

COM

HOLD HOLDCLK

INTERNALNONOVERLAPPINGCLOCK SIGNALS

TRACK TRACK

S2a

S2b

S3b

S3a

COM

S5b

S5a

INA+

INA-

S1

OUT

OUT

C2a

C2b

S4c

S4a

S4b C1b

C1a

INTERNALBIAS

INTERNALBIAS

COM

S2a

S2b

MAX1184

Figure 2. MAX1184 T/H Amplifiers

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______________________________________________________________________________________ 13

Clock Input (CLK)The MAX1184’s CLK input accepts CMOS-compatibleclock signals. Since the interstage conversion of thedevice depends on the repeatability of the rising andfalling edges of the external clock, use a clock with lowjitter and fast rise and fall times (< 2ns). In particular,sampling occurs on the rising edge of the clock signal,requiring this edge to provide lowest possible jitter. Anysignificant aperture jitter would limit the SNR perfor-mance of the on-chip ADCs as follows:

where fIN represents the analog input frequency and tAJis the time of the aperture jitter.

Clock jitter is especially critical for undersamplingapplications. The clock input should always be consid-ered as an analog input and routed away from any ana-log input or other digital signal lines.

The MAX1184 clock input operates with a voltage thresh-old set to VDD/2. Clock inputs with a duty cycle other than50%, must meet the specifications for high and low peri-ods as stated in the Electrical Characteristics.

System Timing RequirementsFigure 3 depicts the relationship between the clockinput, analog input, and data output. The MAX1184samples at the rising edge of the input clock. Outputdata for channels A and B is valid on the next risingedge of the input clock. The output data has an internallatency of five clock cycles. Figure 4 also determinesthe relationship between the input clock parametersand the valid output data on channels A and B.

Digital Output Data, Output Data FormatSelection (T/B), Output Enable (OE)

All digital outputs, D0A–D9A (Channel A) andD0B–D9B (Channel B), are TTL/CMOS logic-compati-ble. There is a five-clock-cycle latency between anyparticular sample and its corresponding output data.

SNRf tIN AJ

= ×× × ×

⎛⎝⎜

⎞⎠⎟

201

2 log

)π

N - 6

N

N - 5

N + 1

N - 4

N + 2

N - 3

N + 3

N - 2

N + 4

N - 1

N + 5

N

N + 6

N + 1

5-CLOCK-CYCLE LATENCY

ANALOG INPUT

CLOCK INPUT

DATA OUTPUTD9A–D0A

tDO tCH tCL

N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N N + 1DATA OUTPUTD9B–D0B

Figure 3. System Timing Diagram

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14 ______________________________________________________________________________________

Table 1. MAX1184 Output Codes For Differential Inputs

*VREF = VREFP - VREFN

DIFFERENTIAL INPUTVOLTAGE*

DIFFERENTIALINPUT

STRAIGHT OFFSETBINARYT/B = 0

TWO’S COMPLEMENTT/B = 1

VREF x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111

VREF x 1/512 + 1 LSB 10 0000 0001 00 0000 0001

0 Bipolar Zero 10 0000 0000 00 0000 0000

- VREF x 1/512 - 1 LSB 01 1111 1111 11 1111 1111

-VREF x 511/512 - FULL SCALE + 1 LSB 00 0000 0001 10 0000 0001

-VREF x 512/512 - FULL SCALE 00 0000 0000 10 0000 0000

The output coding can be chosen to be either straightoffset binary or two’s complement (Table 1) controlledby a single pin (T/B). Pull T/B low to select offset binaryand high to activate two’s complement output coding.The capacitive load on the digital outputs D0A–D9Aand D0B–D9B should be kept as low as possible(<15pF) to avoid large digital currents that could feedback into the analog portion of the MAX1184, therebydegrading its dynamic performance. Using buffers onthe digital outputs of the ADCs can further isolate thedigital outputs from heavy capacitive loads. To furtherimprove the dynamic performance of the MAX1184,small-series resistors (e.g., 100Ω) may be added to thedigital output paths close to the MAX1184.

Figure 4 displays the timing relationship between out-put enable and data output valid as well as power-down/wake-up and data output valid.

Power-Down (PD) and Sleep (SLEEP) Modes

The MAX1184 offers two power-save modes—sleep andfull power-down mode. In sleep mode (SLEEP = 1), onlythe reference bias circuit is active (both ADCs are dis-abled), and current consumption is reduced to 2.8mA.

To enter full power-down mode, pull PD high. With OEsimultaneously low, all outputs are latched at the lastvalue prior to the power down. Pulling OE high forcesthe digital outputs into a high-impedance state.

Applications InformationFigure 5 depicts a typical application circuit containingtwo single-ended to differential converters. The internalreference provides a VDD/2 output voltage for level-shift-ing purposes. The input is buffered and then split to avoltage follower and inverter. One lowpass filter per ADCsuppresses some of the wideband noise associated withhigh-speed op amps follows the amplifiers. The user mayselect the RISO and CIN values to optimize the filter per-formance, to suit a particular application. For the applica-tion in Figure 5, a RISO of 50Ω is placed before thecapacitive load to prevent ringing and oscillation. The22pF CIN capacitor acts as a small bypassing capacitor.

OUTPUTD9A–D0A

OE

tDISABLEtENABLE

HIGH-ZHIGH-ZVALID DATA

OUTPUTD9B–D0B

HIGH-ZHIGH-ZVALID DATA

Figure 4. Output Timing Diagram

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______________________________________________________________________________________ 15

Figure 5. Typical Application for Single-Ended to Differential Conversion

INPUT

300Ω

-5V

+5V

0.1µF

0.1µF

0.1µF

-5V

600Ω

300Ω

300Ω

INA+

INA-

LOWPASS FILTER

COM

600Ω

+5V

-5V

0.1µF

600Ω

300Ω

600Ω

300Ω

0.1µF

0.1µF

0.1µF

+5V

0.1µF

300Ω

MAX4108

MAX1184

INB+

INB-

MAX4108

MAX4108

LOWPASS FILTER

INPUT

300Ω

-5V

+5V

0.1µF

0.1µF

0.1µF

CIN22pF

-5V

600Ω

300Ω

300Ω

LOWPASS FILTER

600Ω

+5V

-5V

0.1µF

600Ω

300Ω

600Ω

300Ω

0.1µF

0.1µF

0.1µF

+5V

0.1µF

300Ω

MAX4108

MAX4108

MAX4108

300Ω

LOWPASS FILTER

RIS050Ω

CIN22pF

RIS050Ω

CIN22pF

RIS050Ω CIN

22pF

RIS050Ω

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16 ______________________________________________________________________________________

MAX1184

0.1µF

1kΩ

1kΩ100Ω

100Ω

CIN22pF

CIN22pF

INB+

INB-

COM

INA+

INA-

0.1µFRISO50Ω

RISO50Ω

REFP

REFN

VIN

MAX4108

0.1µF

1kΩ

1kΩ100Ω

100Ω

CIN22pF

CIN22pF

0.1µFRISO50Ω

RISO50Ω

REFP

REFN

VIN

MAX4108

Figure 7: Using an Op Amp for Single-Ended, AC-CoupledInput Drive

Using Transformer CouplingA RF transformer (Figure 6) provides an excellent solu-tion to convert a single-ended source signal to a fullydifferential signal, required by the MAX1184 for opti-mum performance. Connecting the center tap of thetransformer to COM provides a VDD/2 DC level shift tothe input. Although a 1:1 transformer is shown, a step-up transformer may be selected to reduce the driverequirements. A reduced signal swing from the inputdriver, such as an op amp, may also improve the over-all distortion.

In general, the MAX1184 provides better SFDR andTHD with fully-differential input signals than single-

ended drive, especially for very high input frequencies.In differential input mode, even-order harmonics arelower as both inputs (INA+, INA- and/or INB+, INB-) arebalanced, and each of the ADC inputs only requires halfthe signal swing compared to a single-ended mode.

Single-Ended AC-Coupled Input SignalFigure 7 shows an AC-coupled, single-ended applica-tion. Amplifiers like the MAX4108 provide high speed,high bandwidth, low noise, and low distortion to main-tain the integrity of the input signal.

Figure 6. Transformer-Coupled Input Drive

MAX1184

T1

N.C.

VIN61

52

43

22pF

22pF

0.1µF

0.1µF

2.2µF

25Ω

25Ω

MINICIRCUITSTT1–6

T1

N.C.

VIN61

52

43

22pF

22pF

0.1µF

0.1µF

2.2µF

25Ω

25Ω

MINICIRCUITSTT1–6

INA-

INA+

INB-

INB+

COM

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______________________________________________________________________________________ 17

Typical QAM Demodulation ApplicationThe most frequently used modulation technique for digi-tal communications applications is probably the quadra-ture amplitude modulation (QAM). Typically found inspread-spectrum-based systems, a QAM signal repre-sents a carrier frequency modulated in both amplitudeand phase. At the transmitter, modulating the basebandsignal with quadrature outputs, a local oscillator followedby subsequent up-conversion can generate the QAMsignal. The result is an in-phase (I) and a quadrature (Q)carrier component, where the Q component is 90 degreephase-shifted with respect to the in-phase component. Atthe receiver, the QAM signal is divided down into it’s Iand Q components, essentially representing the modula-tion process reversed. Figure 8 displays the demodula-tion process performed in the analog domain, using thedual matched 3V, 10-bit ADC (MAX1184), and theMAX2451 quadrature demodulator to recover and digi-tize the I and Q baseband signals. Before being digitizedby the MAX1184, the mixed down-signal componentsmay be filtered by matched analog filters, such asNyquist or pulse-shaping filters, which remove anyunwanted images from the mixing process, therebyenhancing the overall signal-to-noise (SNR) performanceand minimizing intersymbol interference.

Grounding, Bypassing, and Board Layout

The MAX1184 requires high-speed board layout designtechniques. Locate all bypass capacitors as close to thedevice as possible, preferably on the same side as theADC, using surface-mount devices for minimum induc-tance. Bypass VDD, REFP, REFN, and COM with two

parallel 0.1µF ceramic capacitors and a 2.2µF bipolarcapacitor to GND. Follow the same rules to bypass thedigital supply (OVDD) to OGND. Multilayer boards withseparated ground and power planes produce the high-est level of signal integrity. Consider the use of a splitground plane arranged to match the physical location ofthe analog ground (GND) and the digital output driverground (OGND) on the ADC’s package. The two groundplanes should be joined at a single point such that thenoisy digital ground currents do not interfere with theanalog ground plane. The ideal location of this connec-tion can be determined experimentally at a point alongthe gap between the two ground planes, which pro-duces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead,or a direct short. Alternatively, all ground pins couldshare the same ground plane, if the ground plane is suf-ficiently isolated from any noisy, digital systems groundplane (e.g., downstream output buffer or DSP groundplane). Route high-speed digital signal traces awayfrom the sensitive analog traces of either channel. Makesure to isolate the analog input lines to each respectiveconverter to minimize channel-to-channel crosstalk.Keep all signal lines short and free of 90 degree turns.

Static Parameter DefinitionsIntegral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on anactual transfer function from a straight line. This straightline can be either a best straight-line fit or a line drawnbetween the endpoints of the transfer function, onceoffset and gain errors have been nullified. The static lin-earity parameters for the MAX1184 are measured usingthe best straight-line fit method.

0°90°

÷8

DOWNCONVERTER

MAX2451 INA+

MAX1184

INA-

INB+INB-

DSP POST

PROCESSING

Figure 8. Typical QAM Application, Using the MAX1184

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18 ______________________________________________________________________________________

Differential Nonlinearity (DNL)Differential nonlinearity is the difference between anactual step width and the ideal value of 1LSB. A DNLerror specification of less than 1LSB guarantees nomissing codes and a monotonic transfer function.

Dynamic Parameter DefinitionsAperture Jitter

Figure 9 depicts the aperture jitter (tAJ), which is thesample-to-sample variation in the aperture delay.

Aperture DelayAperture delay (tAD) is the time defined between thefalling edge of the sampling clock and the instant whenan actual sample is taken (Figure 9).

Signal-to-Noise Ratio (SNR)For a waveform perfectly reconstructed from digitalsamples, the theoretical maximum SNR is the ratio of thefull-scale analog input (RMS value) to the RMS quantiza-tion error (residual error). The ideal, theoretical minimumanalog-to-digital noise is caused by quantization erroronly and results directly from the ADC’s resolution (N-Bits):

SNRdB[max] = 6.02 x N + 1.76

In reality, there are other noise sources besides quanti-zation noise (e.g. thermal noise, reference noise, clockjitter, etc.). SNR is computed by taking the ratio of theRMS signal to the RMS noise, which includes all spec-tral components minus the fundamental, the first fiveharmonics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)SINAD is computed by taking the ratio of the RMS sig-nal to all spectral components minus the fundamentaland the DC offset.

Total Harmonic Distortion (THD)THD is typically the ratio of the RMS sum of the first fourharmonics of the input signal to the fundamental itself.This is expressed as:

where V1 is the fundamental amplitude, and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics.

Spurious-Free Dynamic Range (SFDR)SFDR is the ratio expressed in decibels of the RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next largest spuriouscomponent, excluding DC offset.

Intermodulation Distortion (IMD)The two-tone IMD is the ratio expressed in decibels ofeither input tone to the worst 3rd-order (or higher) inter-modulation products. The individual input tone levelsbacked off by 6.5dB from full scale.

THDV V V V

V= ×

+ + +⎛

⎝

⎜⎜

⎞

⎠

⎟⎟20 10

22

32

42

52

1log

HOLD

ANALOGINPUT

SAMPLEDDATA (T/H)

T/H

tADtAJ

TRACK TRACK

CLK

Figure 9. T/H Aperture Timing

PARTRESOLUTION

(BITS)SPEED GRADE

(Msps)OUTPUT

BUS

MAX1190 10 120 Full-Duplex





MAX1186 10 40 Half-Duplex







Table 2. Pin-Compatible Versions


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GND

REFERENCE

OUTPUTDRIVERS

CONTROL

T/H

T/HPIPELINE

ADC DECOUTPUTDRIVERS

REFOUTREFN COM REFP REFIN

INA+

INA-

CLK

INB+

INB-

VDD

DECPIPELINEADC

OGNDOVDD

D9A–D0A

OE

D9B–D0B

T/BPDSLEEPMAX1184

10

10 10

10

Functional Diagram

19 ______________________________________________________________________________________

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20 ______________________________________________________________________________________

48L,

TQFP

.EP

S

G1

221-0065

PACKAGE OUTLINE,48L TQFP, 7x7x1.0mm EP OPTION

Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline informationgo to www.maxim-ic.com/packages.)


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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

21 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

Revision HistoryPages changed at Rev 1: Title change—all pages, 1–21

G2

221-0065

PACKAGE OUTLINE,48L TQFP, 7x7x1.0mm EP OPTION

Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline informationgo to www.maxim-ic.com/packages.)

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