ltc2294 - dual 12-bit, 80msps low power 3v adc

LTC2294

12294fa

, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

FEATURES DESCRIPTIO

U

APPLICATIO SU

TYPICAL APPLICATIO

U

Integrated Dual 12-Bit ADCs Sample Rate: 80Msps Single 3V Supply (2.7V to 3.4V) Low Power: 422mW 70.6dB SNR at 70MHz Input 90dB SFDR at 70MHz Input 110dB Channel Isolation at 100MHz Multiplexed or Separate Data Bus Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family

105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)

64-Pin (9mm × 9mm) QFN Package

Dual 12-Bit, 80MspsLow Power 3V ADC

The LTC®2294 is a 12-bit 80Msps, low power dual 3VA/D converter designed for digitizing high frequency, widedynamic range signals. The LTC2294 is perfect fordemanding imaging and communications applicationswith AC performance that includes 70.6dB SNR and 90dBSFDR for signals well beyond the Nyquist frequency.

DC specs include ±0.4LSB INL (typ), ±0.2LSB DNL (typ)and no missing codes over temperature. The transitionnoise is a low 0.3LSBRMS.

A single 3V supply allows low power operation. A separateoutput supply allows the outputs to drive 0.5V to 3.6Vlogic. An optional multiplexer allows both channels toshare a digital output bus.

A single-ended CLK input controls converter operation. Anoptional clock duty cycle stabilizer allows high perfor-mance at full speed for a wide range of clock duty cycles.

–

+INPUT

S/HANALOGINPUT A

ANALOGINPUT B

CLK A

CLK B

12-BITPIPELINEDADC CORE

CLOCK/DUTY CYCLECONTROL

OUTPUTDRIVERS

•••

OVDD

OGND

MUX

D11A

D0A

•••

OVDD

OGND

2294 TA01

D11B

D0B

–

+ OUTPUTDRIVERSINPUT

S/H

12-BITPIPELINEDADC CORE

CLOCK/DUTY CYCLECONTROL

INPUT FREQUENCY (MHz)0

65

SNR

(dBF

S)

66

68

69

70

75

72

50 100

2294 TA02

67

73

74

71

150 200

Wireless and Wired Broadband Communication Imaging Systems Spectral Analysis Portable Instrumentation

SNR vs Input Frequency,–1dB, 2V Range

www.BDTIC.com/Linear

2

LTC2294

2294fa

PARAMETER CONDITIONS MIN TYP MAX UNITSResolution (No Missing Codes) 12 BitsIntegral Linearity Error Differential Analog Input (Note 5) –1.4 ±0.4 1.4 LSBDifferential Linearity Error Differential Analog Input –0.8 ±0.2 0.8 LSBOffset Error (Note 6) –12 ±2 12 mVGain Error External Reference –2.5 ±0.5 2.5 %FSOffset Drift ±10 µV/°CFull-Scale Drift Internal Reference ±30 ppm/°C

External Reference ±5 ppm/°CGain Matching External Reference ±0.3 %FSOffset Matching ±2 mVTransition Noise SENSE = 1V 0.3 LSBRMS

ABSOLUTE AXI U RATI GS

W WW U

PACKAGE/ORDER I FOR ATIOU UW

OVDD = VDD (Notes 1, 2)Supply Voltage (VDD) ................................................. 4VDigital Output Ground Voltage (OGND) ....... –0.3V to 1VAnalog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)Digital Input Voltage .................... –0.3V to (VDD + 0.3V)Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)Power Dissipation ............................................ 1500mWOperating Temperature Range

LTC2294C ............................................... 0°C to 70°CLTC2294I .............................................–40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

ORDER PARTNUMBER

QFN PART*MARKING

LTC2294UPLTC2294IUPLTC2294CUP

Consult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.

TOP VIEW

UP PACKAGE64-LEAD (9mm × 9mm) PLASTIC QFN

TJMAX = 125°C, θJA = 20°C/WEXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB

AINA+

1AINA

– 2REFHA 3REFHA 4REFLA 5REFLA 6

VDD 7CLKA 8CLKB 9VDD 10

REFLB 11REFLB 12REFHB 13REFHB 14AINB

– 15AINB

+ 16

48 DA5 47 DA4 46 DA345 DA244 DA1 43 DA042 NC41 NC40 OFB 39 DB1138 DB1037 DB936 DB835 DB734 DB633 DB5

64 G

ND63

VDD

62 S

ENSE

A61

VCM

A60

MOD

E59

SHD

NA58

OEA

57 O

FA56

DA1

155

DA1

054

DA9

53 D

A852

DA7

51 D

A650

OGN

D49

OV D

D

GND

17V D

D 18

SENS

EB 1

9VC

MB

20M

UX 2

1SH

DNB

22OE

B 23

NC 2

4NC

25

DB0

26DB

1 27

DB2

28DB

3 29

DB4

30OG

ND 3

1OV

DD 3

2

65

The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. (Note 4)CO VERTER CHARACTERISTICS

U

Order Options Tape and Reel: Add #TRLead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBFLead Free Part Marking: http://www.linear.com/leadfree/


http://www.linear.com/leadfree/

LTC2294

32294fa

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input 70.6 dB

40MHz Input 69.1 70.6 dB

70MHz Input 70.6 dB

140MHz Input 70.3 dB

SFDR 5MHz Input 90 dB

40MHz Input 74 90 dB

70MHz Input 90 dB

140MHz Input 85 dB

SFDR 5MHz Input 90 dB

40MHz Input 79 90 dB

70MHz Input 90 dB

140MHz Input 90 dB

S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 70.6 dB

40MHz Input 68.7 70.5 dB

70MHz Input 70.5 dB

140MHz Input 70 dB

IMD Intermodulation Distortion fIN = 40MHz, 41MHz 90 dB

Crosstalk fIN = 100MHz –110 dB

Spurious Free Dynamic Range2nd or 3rd Harmonic

Spurious Free Dynamic Range4th Harmonic or Higher


VIN Analog Input Range (AIN+ –AIN

–) 2.7V < VDD < 3.4V (Note 7) ±0.5 to ±1 V

VIN,CM Analog Input Common Mode (AIN+ +AIN

–)/2 Differential Input (Note 7) 1 1.5 1.9 V

Single Ended Input (Note 7) 0.5 1.5 2 V

IIN Analog Input Leakage Current 0V < AIN+, AIN

– < VDD –1 1 µA

ISENSE SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V –3 3 µA

IMODE MODE Input Leakage Current 0V < MODE < VDD –3 3 µA

tAP Sample-and-Hold Acquisition Delay Time 0 ns

tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS

CMRR Analog Input Common Mode Rejection Ratio 80 dB

Full Power Bandwidth Figure 8 Test Circuit 575 MHz

The denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)

A ALOG I PUT

U U

DY A IC ACCURACY

U W

The denotes the specifications which apply over the full operating temperature range, otherwisespecifications are at TA = 25°C. (Note 4)


4

LTC2294

2294fa

DIGITAL I PUTS A D DIGITAL OUTPUTS

U U

The denotes the specifications which apply over thefull operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)

I TER AL REFERE CE CHARACTERISTICSU U U

(Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V

VCM Output Tempco ±25 ppm/°C

VCM Line Regulation 2.7V < VDD < 3.4V 3 mV/V

VCM Output Resistance –1mA < IOUT < 1mA 4 Ω


LOGIC INPUTS (CLK, OE, SHDN, MUX)

VIH High Level Input Voltage VDD = 3V 2 V

VIL Low Level Input Voltage VDD = 3V 0.8 V

IIN Input Current VIN = 0V to VDD –10 10 µA

CIN Input Capacitance (Note 7) 3 pF

LOGIC OUTPUTS

OVDD = 3V

COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF

ISOURCE Output Source Current VOUT = 0V 50 mA

ISINK Output Sink Current VOUT = 3V 50 mA

VOH High Level Output Voltage IO = –10µA 2.995 VIO = –200µA 2.7 2.99 V

VOL Low Level Output Voltage IO = 10µA 0.005 VIO = 1.6mA 0.09 0.4 V

OVDD = 2.5V

VOH High Level Output Voltage IO = –200µA 2.49 V

VOL Low Level Output Voltage IO = 1.6mA 0.09 V

OVDD = 1.8V

VOH High Level Output Voltage IO = –200µA 1.79 V

VOL Low Level Output Voltage IO = 1.6mA 0.09 V


LTC2294

52294fa


fs Sampling Frequency (Note 9) 1 80 MHz

tL CLK Low Time Duty Cycle Stabilizer Off 5.9 6.25 500 nsDuty Cycle Stabilizer On (Note 7) 5 6.25 500 ns

tH CLK High Time Duty Cycle Stabilizer Off 5.9 6.25 500 nsDuty Cycle Stabilizer On (Note 7) 5 6.25 500 ns

tAP Sample-and-Hold Aperture Delay 0 ns

tD CLK to DATA Delay CL = 5pF (Note 7) 1.4 2.7 5.4 ns

tMD MUX to DATA Delay CL = 5pF (Note 7) 1.4 2.7 5.4 ns

Data Access Time After OE↓ CL = 5pF (Note 7) 4.3 10 ns

BUS Relinquish Time (Note 7) 3.3 8.5 ns

Pipeline Latency 5 Cycles


VDD Analog Supply Voltage (Note 9) 2.7 3 3.4 V

OVDD Output Supply Voltage (Note 9) 0.5 3 3.6 V

IVDD Supply Current Both ADCs at fS(MAX) 141 165 mA

PDISS Power Dissipation Both ADCs at fS(MAX) 422 495 mW

PSHDN Shutdown Power (Each Channel) SHDN = H, OE = H, No CLK 2 mW

PNAP Nap Mode Power (Each Channel) SHDN = H, OE = L, No CLK 15 mW

POWER REQUIRE E TS

W U

The denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. (Note 8)

TI I G CHARACTERISTICSUW

The denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. (Note 4)

Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliability and lifetime.Note 2: All voltage values are with respect to ground with GND and OGNDwired together (unless otherwise noted).Note 3: When these pin voltages are taken below GND or above VDD, theywill be clamped by internal diodes. This product can handle input currentsof greater than 100mA below GND or above VDD without latchup.Note 4: VDD = 3V, fSAMPLE = 80MHz, input range = 2VP-P with differentialdrive, unless otherwise noted.

Note 5: Integral nonlinearity is defined as the deviation of a code from astraight line passing through the actual endpoints of the transfer curve.The deviation is measured from the center of the quantization band.Note 6: Offset error is the offset voltage measured from –0.5 LSB whenthe output code flickers between 0000 0000 0000 and 1111 1111 1111.Note 7: Guaranteed by design, not subject to test.Note 8: VDD = 3V, fSAMPLE = 80MHz, input range = 1VP-P with differentialdrive. The supply current and power dissipation are the sum total for bothchannels with both channels active.Note 9: Recommended operating conditions.


6

LTC2294

2294fa

8192 Point 2-Tone FFT,fIN = 28.2MHz and 26.8MHz,–1dB, 2V Range

TYPICAL PERFOR A CE CHARACTERISTICS

UW

Typical INL, 2V Range, 80Msps Typical DNL, 2V Range, 80Msps

8192 Point FFT, fIN = 5MHz, –1dB,2V Range, 80Msps

8192 Point FFT, fIN = 30MHz,–1dB, 2V Range, 80Msps



Grounded Input Histogram,80Msps

Crosstalk vs Input Frequency


–130

CROS

STAL

K (d

B)

–125

–120

–115

–110

–105

–100

20 40 60 80

2294 G01

100CODE

0

INL

ERRO

R (L

SB)

0.2

0.4

0.6

4096

2294 G02

0

–0.2

–1.01024 2048 3072

–0.6

–0.4

–0.8

1.0

0.8

CODE0

DNL

ERRO

R (L

SB)

0.2

0.4

0.6

4096

2294 G03

0

–0.2

–1.01024 2048 3072

–0.6

–0.4

–0.8

1.0

0.8

FREQUENCY (MHz)0

AMPL

ITUD

E (d

B)

–60

–40

–20

0

35

2294 G04

–80

–100

–70

–50

–30

–10

–90

–110

–1205 15 2510 20 30 40

FREQUENCY (MHz)0

AMPL

ITUD

E (d

B)

–60

–40

–20

0

35

2294 G05

–80

–100

–70

–50

–30

–10

–90

–110

–1205 15 2510 20 30 40

FREQUENCY (MHz)0

AMPL

ITUD

E (d

B)

–60

–40

–20

0

35

2294 G06

–80

–100

–70

–50

–30

–10

–90

–110

–1205 15 2510 20 30 40

FREQUENCY (MHz)0

AMPL

ITUD

E (d

B)

–60

–40

–20

0

35

2294 G07

–80

–100

–70

–50

–30

–10

–90

–110

–1205 15 2510 20 30 40

FREQUENCY (MHz)0

AMPL

ITUD

E (d

B)

–60

–40

–20

0

35

2294 G08

–80

–100

–70

–50

–30

–10

–90

–110

–1205 15 2510 20 30 40

CODE2050

5712

100000

120000

140000

2294 G09

80000

60000

2051

116838

2052

8522

40000

20000

0

COUN

T


LTC2294

72294fa

TYPICAL PERFOR A CE CHARACTERISTICS

UW

SNR and SFDR vs Sample Rate,2V Range, fIN = 5MHz, –1dB

SNR and SFDR vs Clock DutyCycle, 80Msps

SNR vs Input Level, fIN = 70MHz,2V Range, 80Msps

IOVDD vs Sample Rate, 5MHz SineWave Input, –1dB, OVDD = 1.8V

IVDD vs Sample Rate, 5MHz SineWave Input, –1dB

SFDR vs Input Level, fIN = 70MHz,2V Range, 80Msps

SFDR vs Input Frequency, –1dB,2V Range, 80Msps

SAMPLE RATE (Msps)0

95

I VDD

(mA)

105

125

135

145

165

10 50 70

2294 G16

115

155

40 90 10020 30 60 80

2V RANGE

1V RANGE

SAMPLE RATE (Msps)0

0

I OVD

D (m

A)

2

6

8

10

14

10 50 70

2294 G17

4

12

40 90 10020 30 60 80

SNR vs Input Frequency, –1dB,2V Range, 80Msps


65

SNR

(dBF

S)

66

68

69

70

75

72

50 100

2294 G10

67

73

74

71

150 200INPUT FREQUENCY (MHz)

0

85

90

100

150

2294 G11

80

75

50 100 200

70

65

95

SFDR

(dBF

S)

SAMPLE RATE (Msps)0

SNR

AND

SFDR

(dBF

S)

80

90

100

80

2294 G12

70

60

5010 20 30 40 50 60 70 90 100 110

SFDR

SNR

CLOCK DUTY CYCLE (%)30

SNR

AND

SFDR

(dBF

S)

85

90

60

2294 G13

80

75

40 5035 6545 55 7065

70

95

SFDR: DCS ON

SNR: DCS ON

SNR: DCS OFF

SFDR: DCS OFF

INPUT LEVEL (dBFS)–50–60–70

SNR

(dBc

AND

dBF

S)

30

40

50

–20 0

2294 G14

20

10

0–40 –30

dBFS

dBc

–10

60

70

80

INPUT LEVEL (dBFS)–70

SFDR

(dBc

AND

dBF

S)60

dBc

dBFS

90

100

0

2294 G15

50

40

0–60 –50 –40 –30 –20 –10

20

120

110

80

70

30

10

100dBc SFDRREFERENCE LINE


8

LTC2294

2294fa

UUU

PI FU CTIO SAINA

+ (Pin 1): Channel A Positive Differential AnalogInput.

AINA– (Pin 2): Channel A Negative Differential Analog

Input.

REFHA (Pins 3, 4): Channel A High Reference. Shorttogether and bypass to Pins 5, 6 with a 0.1µF ceramic chipcapacitor as close to the pin as possible. Also bypass toPins 5, 6 with an additional 2.2µF ceramic chip capacitorand to ground with a 1µF ceramic chip capacitor.

REFLA (Pins 5, 6): Channel A Low Reference. Shorttogether and bypass to Pins 3, 4 with a 0.1µF ceramic chipcapacitor as close to the pin as possible. Also bypass toPins 3, 4 with an additional 2.2µF ceramic chip capacitorand to ground with a 1µF ceramic chip capacitor.

VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass toGND with 0.1µF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input samplestarts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input samplestarts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Shorttogether and bypass to Pins 13, 14 with a 0.1µF ceramicchip capacitor as close to the pin as possible. Also bypassto Pins 13, 14 with an additional 2.2µF ceramic chip ca-pacitor and to ground with a 1µF ceramic chip capacitor.

REFHB (Pins 13, 14): Channel B High Reference. Shorttogether and bypass to Pins 11, 12 with a 0.1µF ceramicchip capacitor as close to the pin as possible. Also bypassto Pins 11, 12 with an additional 2.2µF ceramic chip ca-pacitor and to ground with a 1µF ceramic chip capacitor.

AINB– (Pin 15): Channel B Negative Differential Analog

Input.

AINB+ (Pin 16): Channel B Positive Differential Analog

Input.

GND (Pins 17, 64): ADC Power Ground.

SENSEB (Pin 19): Channel B Reference Programming Pin.Connecting SENSEB to VCMB selects the internal referenceand a ±0.5V input range. VDD selects the internal reference

and a ±1V input range. An external reference greater than0.5V and less than 1V applied to SENSEB selects an inputrange of ±VSENSEB. ±1V is the largest valid input range.

VCMB (Pin 20): Channel B 1.5V Output and Input CommonMode Bias. Bypass to ground with 2.2µF ceramic chipcapacitor. Do not connect to VCMA.

MUX (Pin 21): Digital Output Multiplexer Control. If MUXis High, Channel A comes out on DA0-DA13, OFA; Channel Bcomes out on DB0-DB13, OFB. If MUX is Low, the outputbusses are swapped and Channel A comes out on DB0-DB13, OFB; Channel B comes out on DA0-DA13, OFA. Tomultiplex both channels onto a single output bus, connectMUX, CLKA and CLKB together.

SHDNB (Pin 22): Channel B Shutdown Mode SelectionPin. Connecting SHDNB to GND and OEB to GND resultsin normal operation with the outputs enabled. ConnectingSHDNB to GND and OEB to VDD results in normal opera-tion with the outputs at high impedance. ConnectingSHDNB to VDD and OEB to GND results in nap mode withthe outputs at high impedance. Connecting SHDNB to VDDand OEB to VDD results in sleep mode with the outputs athigh impedance.

OEB (Pin 23): Channel B Output Enable Pin. Refer toSHDNB pin function.

NC (Pins 24, 25, 41, 42): Do Not Connect These Pins.

DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B DigitalOutputs. DB11 is the MSB.

OGND (Pins 31, 50): Output Driver Ground.

OVDD (Pins 32, 49): Positive Supply for the Output Driv-ers. Bypass to ground with 0.1µF ceramic chip capacitor.

OFB (Pin 40): Channel B Overflow/Underflow Output.High when an overflow or underflow has occurred.

DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A DigitalOutputs. DA11 is the MSB.

OFA (Pin 57): Channel A Overflow/Underflow Output.High when an overflow or underflow has occurred.

OEA (Pin 58): Channel A Output Enable Pin. Refer toSHDNA pin function.


LTC2294

92294fa

SHDNA (Pin 59): Channel A Shutdown Mode SelectionPin. Connecting SHDNA to GND and OEA to GND resultsin normal operation with the outputs enabled. ConnectingSHDNA to GND and OEA to VDD results in normal opera-tion with the outputs at high impedance. ConnectingSHDNA to VDD and OEA to GND results in nap mode withthe outputs at high impedance. Connecting SHDNA to VDDand OEA to VDD results in sleep mode with the outputs athigh impedance.

MODE (Pin 60): Output Format and Clock Duty CycleStabilizer Selection Pin. Note that MODE controls bothchannels. Connecting MODE to GND selects offset binaryoutput format and turns the clock duty cycle stabilizer off.1/3 VDD selects offset binary output format and turns theclock duty cycle stabilizer on. 2/3 VDD selects 2’s comple-ment output format and turns the clock duty cycle stabi-

UUU

PI FU CTIO Slizer on. VDD selects 2’s complement output format andturns the clock duty cycle stabilizer off.

VCMA (Pin 61): Channel A 1.5V Output and Input CommonMode Bias. Bypass to ground with 2.2µF ceramic chipcapacitor. Do not connect to VCMB.

SENSEA (Pin 62): Channel A Reference Programming Pin.Connecting SENSEA to VCMA selects the internal referenceand a ±0.5V input range. VDD selects the internal referenceand a ±1V input range. An external reference greater than0.5V and less than 1V applied to SENSEA selects an inputrange of ±VSENSEA. ±1V is the largest valid input range.

GND (Exposed Pad) (Pin 65): ADC Power Ground. TheExposed Pad on the bottom of the package needs to besoldered to ground.

FUNCTIONAL BLOCK DIAGRA

UU W

Figure 1. Functional Block Diagram (Only One Channel is Shown)

SHIFT REGISTERAND CORRECTION

DIFFREFAMP

REFBUF

2.2µF

1µF 1µF

0.1µF

INTERNAL CLOCK SIGNALSREFH REFL

CLOCK/DUTYCYCLE

CONTROL

RANGESELECT

1.5VREFERENCE

FIRST PIPELINEDADC STAGE

FIFTH PIPELINEDADC STAGE

SIXTH PIPELINEDADC STAGE

FOURTH PIPELINEDADC STAGE

SECOND PIPELINEDADC STAGE

REFH REFL

CLK OEMODEOGND

OVDD

2294 F01

INPUTS/H

SENSE

VCM

AIN–

AIN+

2.2µF

THIRD PIPELINEDADC STAGE

OUTPUTDRIVERS

CONTROLLOGIC

SHDN

OF

D11

D0

•••


10

LTC2294

2294fa

Dual Digital Output Bus Timing(Only One Channel is Shown)

TI I G DIAGRA S

WU W

Multiplexed Digital Output Bus Timing

tAPB

B + 1B + 2 B + 4

B + 3BANALOG

INPUT B

tAPA

A + 1

A – 5

B – 5

B – 5

A – 5

A – 4

B – 4

B – 4

A – 4

A – 3

B – 3

B – 3

A – 3

A – 2

B – 2

B – 2

A – 2

A – 1

B – 1

A + 2 A + 4

A + 3AANALOG

INPUT A

tH

tD tMD

tL

CLKA = CLKB = MUX

D0A-D11A, OFA

2294 TD02

D0B-D11B, OFB

tAP

N + 1N + 2 N + 4

N + 3 N + 5NANALOG

INPUT

tH

tD

tL

N – 4 N – 3 N – 2 N – 1

CLK

D0-D11, OF

2294 TD01

N – 5 N


LTC2294

112294fa

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is theratio between the RMS amplitude of the fundamental inputfrequency and the RMS amplitude of all other frequencycomponents at the ADC output. The output is band limitedto frequencies above DC to below half the samplingfrequency.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between theRMS amplitude of the fundamental input frequency andthe RMS amplitude of all other frequency componentsexcept the first five harmonics and DC.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of allharmonics of the input signal to the fundamental itself. Theout-of-band harmonics alias into the frequency bandbetween DC and half the sampling frequency. THD isexpressed as:

THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)where V1 is the RMS amplitude of the fundamental fre-quency and V2 through Vn are the amplitudes of thesecond through nth harmonics. The THD calculated in thisdata sheet uses all the harmonics up to the fifth.

Intermodulation Distortion

If the ADC input signal consists of more than one spectralcomponent, the ADC transfer function nonlinearity canproduce intermodulation distortion (IMD) in addition toTHD. IMD is the change in one sinusoidal input caused bythe presence of another sinusoidal input at a differentfrequency.

If two pure sine waves of frequencies fa and fb are appliedto the ADC input, nonlinearities in the ADC transfer func-tion can create distortion products at the sum and differ-ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,etc. The 3rd order intermodulation products are 2fa + fb,

APPLICATIO S I FOR ATIO

WU UU

2fb + fa, 2fa – fb and 2fb – fa. The intermodulationdistortion is defined as the ratio of the RMS value of eitherinput tone to the RMS value of the largest 3rd orderintermodulation product.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic orspurious noise that is the largest spectral componentexcluding the input signal and DC. This value is expressedin decibels relative to the RMS value of a full scale inputsignal.

Input Bandwidth

The input bandwidth is that input frequency at which theamplitude of the reconstructed fundamental is reduced by3dB for a full scale input signal.

Aperture Delay Time

The time from when CLK reaches midsupply to the instantthat the input signal is held by the sample and hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion toconversion. This random variation will result in noisewhen sampling an AC input. The signal to noise ratio dueto the jitter alone will be:

SNRJITTER = –20log (2π • fIN • tJITTER)

Crosstalk

Crosstalk is the coupling from one channel (being drivenby a full-scale signal) onto the other channel (being drivenby a –1dBFS signal).

CONVERTER OPERATION

As shown in Figure 1, the LTC2294 is a dual CMOSpipelined multistep converter. The converter has sixpipelined ADC stages; a sampled analog input will result ina digitized value five cycles later (see the Timing Diagramsection). For optimal AC performance the analog inputsshould be driven differentially. For cost sensitive


12

LTC2294

2294fa

applications, the analog inputs can be driven single-endedwith slightly worse harmonic distortion. The CLK input issingle-ended. The LTC2294 has two phases of operation,determined by the state of the CLK input pin.

Each pipelined stage shown in Figure 1 contains an ADC,a reconstruction DAC and an interstage residue amplifier.In operation, the ADC quantizes the input to the stage andthe quantized value is subtracted from the input by theDAC to produce a residue. The residue is amplified andoutput by the residue amplifier. Successive stages operateout of phase so that when the odd stages are outputtingtheir residue, the even stages are acquiring that residueand vice versa.

When CLK is low, the analog input is sampled differentiallydirectly onto the input sample-and-hold capacitors, insidethe “Input S/H” shown in the block diagram. At the instantthat CLK transitions from low to high, the sampled input isheld. While CLK is high, the held input voltage is bufferedby the S/H amplifier which drives the first pipelined ADCstage. The first stage acquires the output of the S/H duringthis high phase of CLK. When CLK goes back low, the firststage produces its residue which is acquired by thesecond stage. At the same time, the input S/H goes backto acquiring the analog input. When CLK goes back high,the second stage produces its residue which is acquiredby the third stage. An identical process is repeated for thethird, fourth and fifth stages, resulting in a fifth stage


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residue that is sent to the sixth stage ADC for finalevaluation.

Each ADC stage following the first has additional range toaccommodate flash and amplifier offset errors. Resultsfrom all of the ADC stages are digitally synchronized suchthat the results can be properly combined in the correctionlogic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2294CMOS differential sample-and-hold. The analog inputs areconnected to the sampling capacitors (CSAMPLE) throughNMOS transistors. The capacitors shown attached to eachinput (CPARASITIC) are the summation of all other capaci-tance associated with each input.

During the sample phase when CLK is low, the transistorsconnect the analog inputs to the sampling capacitors andthey charge to and track the differential input voltage.When CLK transitions from low to high, the sampled inputvoltage is held on the sampling capacitors. During the holdphase when CLK is high, the sampling capacitors aredisconnected from the input and the held voltage is passedto the ADC core for processing. As CLK transitions fromhigh to low, the inputs are reconnected to the sampling

Figure 2. Equivalent Input Circuit

VDD

VDD

VDD

15Ω

15Ω

CPARASITIC1pF

CPARASITIC1pF

CSAMPLE4pF

CSAMPLE4pF

LTC2294

AIN+

AIN–

CLK

2294 F02


LTC2294

132294fa

capacitors to acquire a new sample. Since the samplingcapacitors still hold the previous sample, a charging glitchproportional to the change in voltage between samples willbe seen at this time. If the change between the last sampleand the new sample is small, the charging glitch seen atthe input will be small. If the input change is large, such asthe change seen with input frequencies near Nyquist, thena larger charging glitch will be seen.

Single-Ended Input

For cost sensitive applications, the analog inputs can bedriven single-ended. With a single-ended input the har-monic distortion and INL will degrade, but the SNR andDNL will remain unchanged. For a single-ended input, AIN

+

should be driven with the input signal and AIN– should be

connected to 1.5V or VCM.

Common Mode Bias

For optimal performance the analog inputs should bedriven differentially. Each input should swing ±0.5V forthe 2V range or ±0.25V for the 1V range, around acommon mode voltage of 1.5V. The VCM output pin maybe used to provide the common mode bias level. VCM canbe tied directly to the center tap of a transformer to set theDC input level or as a reference level to an op ampdifferential driver circuit. The VCM pin must be bypassed toground close to the ADC with a 2.2µF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, thedynamic performance of the LTC2294 can be influencedby the input drive circuitry, particularly the second andthird harmonics. Source impedance and reactance caninfluence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 4pF sampling capacitor tothe input pin and start the sampling period. The samplingperiod ends when CLK rises, holding the sampled input onthe sampling capacitor. Ideally the input circuitry shouldbe fast enough to fully charge the sampling capacitorduring the sampling period 1/(2FENCODE); however, this isnot always possible and the incomplete settling maydegrade the SFDR. The sampling glitch has been designed


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to be as linear as possible to minimize the effects ofincomplete settling.

For the best performance, it is recommended to have asource impedance of 100Ω or less for each input. Thesource impedance should be matched for the differentialinputs. Poor matching will result in higher even orderharmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2294 being driven by an RFtransformer with a center tapped secondary. The second-ary center tap is DC biased with VCM, setting the ADC inputsignal at its optimum DC level. Terminating on the trans-former secondary is desirable, as this provides a commonmode path for charging glitches caused by the sample andhold. Figure 3 shows a 1:1 turns ratio transformer. Otherturns ratios can be used if the source impedance seen bythe ADC does not exceed 100Ω for each ADC input. Adisadvantage of using a transformer is the loss of lowfrequency response. Most small RF transformers havepoor performance at frequencies below 1MHz.

Figure 3. Single-Ended to Differential ConversionUsing a Transformer

25Ω

25Ω

25Ω

25Ω

0.1µF

AIN+

AIN–

12pF

2.2µF

VCM

LTC2294ANALOGINPUT

0.1µF T11:1

T1 = MA/COM ETC1-1TRESISTORS, CAPACITORSARE 0402 PACKAGE SIZE

2294 F03

Figure 4 demonstrates the use of a differential amplifier toconvert a single ended input signal into a differential inputsignal. The advantage of this method is that it provides lowfrequency input response; however, the limited gain band-width of most op amps will limit the SFDR at high inputfrequencies.


14

LTC2294

2294fa

Figure 5 shows a single-ended input circuit. The imped-ance seen by the analog inputs should be matched. Thiscircuit is not recommended if low distortion is required.


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Figure 6. Recommended Front End Circuit forInput Frequencies Between 70MHz and 170MHz

Figure 8. Recommended Front End Circuit forInput Frequencies Above 300MHz

Figure 7. Recommended Front End Circuit forInput Frequencies Between 170MHz and 300MHz

25Ω

25Ω12Ω

12Ω

0.1µF

AIN+

AIN–

8pF

2.2µF

VCM

ANALOGINPUT

0.1µF

0.1µF

T1

T1 = MA/COM, ETC 1-1-13RESISTORS, CAPACITORSARE 0402 PACKAGE SIZE

2294 F06

LTC2294

Figure 5. Single-Ended Drive

Figure 4. Differential Drive with an Amplifier

25Ω

25Ω

12pF

2.2µF

VCM

2294 F04

– –

+ +CM

ANALOGINPUT

HIGH SPEEDDIFFERENTIAL

AMPLIFIER AIN+

AIN–

LTC2294

25Ω0.1µF

ANALOGINPUT

VCM

AIN+

AIN–

1k

12pF

2294 F05

2.2µF1k

25Ω

0.1µF

LTC2294

The 25Ω resistors and 12pF capacitor on the analog inputsserve two purposes: isolating the drive circuitry from thesample-and-hold charging glitches and limiting thewideband noise at the converter input.

For input frequencies above 70MHz, the input circuits ofFigure 6, 7 and 8 are recommended. The balun trans-former gives better high frequency response than a fluxcoupled center tapped transformer. The coupling capaci-tors allow the analog inputs to be DC biased at 1.5V. InFigure 8, the series inductors are impedance matchingelements that maximize the ADC bandwidth.

25Ω

25Ω

0.1µF

AIN+

AIN–

2.2µF

VCM

ANALOGINPUT

0.1µF

0.1µF

T1

T1 = MA/COM, ETC 1-1-13RESISTORS, CAPACITORSARE 0402 PACKAGE SIZE

2294 F07

LTC2294

25Ω

25Ω

0.1µF

AIN+

AIN–

2.2µF

VCM

ANALOGINPUT

0.1µF

0.1µF

T1

T1 = MA/COM, ETC 1-1-13RESISTORS, CAPACITORS, INDUCTORSARE 0402 PACKAGE SIZE

2294 F08

6.8nH

6.8nH

LTC2294


LTC2294

152294fa


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Reference Operation

Figure 9 shows the LTC2294 reference circuitry consistingof a 1.5V bandgap reference, a difference amplifier andswitching and control circuit. The internal voltage refer-ence can be configured for two pin selectable input rangesof 2V (±1V differential) or 1V (±0.5V differential). Tying theSENSE pin to VDD selects the 2V range; tying the SENSEpin to VCM selects the 1V range.

The 1.5V bandgap reference serves two functions: itsoutput provides a DC bias point for setting the commonmode voltage of any external input circuitry; additionally,the reference is used with a difference amplifier to gener-ate the differential reference levels needed by the internalADC circuitry. An external bypass capacitor is required forthe 1.5V reference output, VCM. This provides a highfrequency low impedance path to ground for internal andexternal circuitry.

The difference amplifier generates the high and low refer-ence for the ADC. High speed switching circuits areconnected to these outputs and they must be externallybypassed. Each output has two pins. The multiple outputpins are needed to reduce package inductance. Bypasscapacitors must be connected as shown in Figure 9. EachADC channel has an independent reference with its ownbypass capacitors. The two channels can be used with thesame or different input ranges.

Other voltage ranges between the pin selectable rangescan be programmed with two external resistors as shownin Figure 10. An external reference can be used by applyingits output directly or through a resistor divider to SENSE.It is not recommended to drive the SENSE pin with a logicdevice. The SENSE pin should be tied to the appropriatelevel as close to the converter as possible. If the SENSE pinis driven externally, it should be bypassed to ground asclose to the device as possible with a 1µF ceramic capacitor.For the best channel matching, connect an external referenceto SENSEA and SENSEB.

Figure 10. 1.5V Range ADC

Figure 9. Equivalent Reference Circuit

VCM

REFH

SENSETIE TO VDD FOR 2V RANGE;TIE TO VCM FOR 1V RANGE;

RANGE = 2 • VSENSE FOR0.5V < VSENSE < 1V

1.5V

REFL

2.2µF

2.2µF

INTERNAL ADCHIGH REFERENCE

BUFFER

0.1µF

2294 F09

4Ω

DIFF AMP

1µF

1µF

INTERNAL ADCLOW REFERENCE

1.5V BANDGAPREFERENCE

1V 0.5V

RANGEDETECT

ANDCONTROL

LTC2294

VCM

SENSE

1.5V

0.75V

2.2µF12k

1µF12k

2294 F10

LTC2294

Input Range

The input range can be set based on the application. The2V input range will provide the best signal-to-noise perfor-mance while maintaining excellent SFDR. The 1V inputrange will have better SFDR performance, but the SNR willdegrade by 4dB. See the Typical Performance Character-istics section.

Driving the Clock Input

The CLK inputs can be driven directly with a CMOS or TTLlevel signal. A sinusoidal clock can also be used along witha low jitter squaring circuit before the CLK pin (Figure 11).


16

LTC2294

2294fa

CLK

5pF-30pF

ETC1-1T

0.1µF

VCM

FERRITE BEAD

DIFFERENTIALCLOCKINPUT

2294 F13

LTC2294

CLK100Ω

0.1µF

4.7µF

FERRITE BEAD

CLEANSUPPLY

IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR

2294 F12

LTC2294


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The noise performance of the LTC2294 can depend on theclock signal quality as much as on the analog input. Anynoise present on the clock signal will result in additionalaperture jitter that will be RMS summed with the inherentADC aperture jitter.

In applications where jitter is critical, such as when digitiz-ing high input frequencies, use as large an amplitude aspossible. Also, if the ADC is clocked with a sinusoidalsignal, filter the CLK signal to reduce wideband noise anddistortion products generated by the source.

It is recommended that CLKA and CLKB are shortedtogether and driven by the same clock source. If a smalltime delay is desired between when the two channelssample the analog inputs, CLKA and CLKB can be drivenby two different signals. If this delay exceeds 1ns, theperformance of the part may degrade. CLKA and CLKBshould not be driven by asynchronous signals.

Figures 12 and 13 show alternatives for converting adifferential clock to the single-ended CLK input. The use ofa transformer provides no incremental contribution tophase noise. The LVDS or PECL to CMOS translatorsprovide little degradation below 70MHz, but at 140MHzwill degrade the SNR compared to the transformer solu-tion. The nature of the received signals also has a largebearing on how much SNR degradation will be experi-enced. For high crest factor signals such as WCDMA orOFDM, where the nominal power level must be at least 6dBto 8dB below full scale, the use of these translators willhave a lesser impact.

Figure 11. Sinusoidal Single-Ended CLK Drive

CLK

50Ω

0.1µF

0.1µF

4.7µF

1k

1k

FERRITE BEAD

CLEANSUPPLY

SINUSOIDALCLOCKINPUT

2294 F11

NC7SVU04

LTC2294

Figure 13. LVDS or PECL CLK Drive Using a Transformer

Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter

The transformer in the example may be terminated withthe appropriate termination for the signaling in use. Theuse of a transformer with a 1:4 impedance ratio may bedesirable in cases where lower voltage differential signalsare considered. The center tap may be bypassed to groundthrough a capacitor close to the ADC if the differentialsignals originate on a different plane. The use of a capaci-tor at the input may result in peaking, and depending ontransmission line length may require a 10Ω to 20Ω ohmseries resistor to act as both a low pass filter for highfrequency noise that may be induced into the clock line byneighboring digital signals, as well as a damping mecha-nism for reflections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2294 is 80Msps.For the ADC to operate properly, the CLK signal shouldhave a 50% (±5%) duty cycle. Each half cycle must have


LTC2294

172294fa

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single outputbuffer. Each buffer is powered by OVDD and OGND, iso-lated from the ADC power and ground. The additionalN-channel transistor in the output driver allows operationdown to low voltages. The internal resistor in series withthe output makes the output appear as 50Ω to externalcircuitry and may eliminate the need for external dampingresistors.

at least 5.9ns for the ADC internal circuitry to have enoughsettling time for proper operation.

An optional clock duty cycle stabilizer circuit can be usedif the input clock has a non 50% duty cycle. This circuituses the rising edge of the CLK pin to sample the analoginput. The falling edge of CLK is ignored and the internalfalling edge is generated by a phase-locked loop. Theinput clock duty cycle can vary from 40% to 60% and theclock duty cycle stabilizer will maintain a constant 50%internal duty cycle. If the clock is turned off for a longperiod of time, the duty cycle stabilizer circuit will requirea hundred clock cycles for the PLL to lock onto the inputclock. To use the clock duty cycle stabilizer, the MODE pinshould be connected to 1/3VDD or 2/3VDD using externalresistors. The MODE pin controls both Channel A andChannel B—the duty cycle stabilizer is either on or off forboth channels.

The lower limit of the LTC2294 sample rate is determinedby droop of the sample-and-hold circuits. The pipelinedarchitecture of this ADC relies on storing analog signals onsmall valued capacitors. Junction leakage will dischargethe capacitors. The specified minimum operating fre-quency for the LTC2294 is 1Msps.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog inputvoltage, the digital data bits, and the overflow bit.


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2294 F14

OVDD

VDD VDD0.1µF

43Ω TYPICALDATAOUTPUT

OGND

OVDD 0.5V TO 3.6V

PREDRIVERLOGIC

DATAFROM

LATCH

OE

LTC2294

Figure 14. Digital Output Buffer

As with all high speed/high resolution converters, the digi-tal output loading can affect the performance. The digitaloutputs of the LTC2294 should drive a minimal capacitiveload to avoid possible interaction between the digitaloutputs and sensitive input circuitry. The output should bebuffered with a device such as an ALVCH16373 CMOSlatch. For full speed operation the capacitive load shouldbe kept under 10pF.

Lower OVDD voltages will also help reduce interferencefrom the digital outputs.

Data Format

Using the MODE pin, the LTC2294 parallel digital outputcan be selected for offset binary or 2’s complementformat. Note that MODE controls both Channel A andChannel B. Connecting MODE to GND or 1/3VDD selects

Table 1. Output Codes vs Input VoltageAIN

+ – AIN– D11 – D0 D11 – D0

(2V RANGE) OF (OFFSET BINARY) (2’s COMPLEMENT)

>+1.000000V 1 1111 1111 1111 0111 1111 1111+0.999512V 0 1111 1111 1111 0111 1111 1111+0.999024V 0 1111 1111 1110 0111 1111 1110

+0.000488V 0 1000 0000 0001 0000 0000 0001 0.000000V 0 1000 0000 0000 0000 0000 0000–0.000488V 0 0111 1111 1111 1111 1111 1111–0.000976V 0 0111 1111 1110 1111 1111 1110

–0.999512V 0 0000 0000 0001 1000 0000 0001–1.000000V 0 0000 0000 0000 1000 0000 0000

<–1.000000V 1 0000 0000 0000 1000 0000 0000


18

LTC2294

2294fa

offset binary output format. Connecting MODE to2/3VDD or VDD selects 2’s complement output format. Anexternal resistor divider can be used to set the 1/3VDD or2/3VDD logic values. Table 2 shows the logic states for theMODE pin.


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Sleep and Nap Modes

The converter may be placed in shutdown or nap modesto conserve power. Connecting SHDN to GND results innormal operation. Connecting SHDN to VDD and OE to VDDresults in sleep mode, which powers down all circuitryincluding the reference and typically dissipates 1mW. Whenexiting sleep mode it will take milliseconds for the outputdata to become valid because the reference capacitors haveto recharge and stabilize. Connecting SHDN to VDD and OEto GND results in nap mode, which typically dissipates30mW. In nap mode, the on-chip reference circuit is kepton, so that recovery from nap mode is faster than that fromsleep mode, typically taking 100 clock cycles. In both sleepand nap modes, all digital outputs are disabled and enterthe Hi-Z state.

Channels A and B have independent SHDN pins (SHDNA,SHDNB). Channel A is controlled by SHDNA and OEA, andChannel B is controlled by SHDNB and OEB. The nap, sleepand output enable modes of the two channels are completelyindependent, so it is possible to have one channel operat-ing while the other channel is in nap or sleep mode.

Digital Output Multiplexer

The digital outputs of the LTC2294 can be multiplexed ontoa single data bus. The MUX pin is a digital input that swapsthe two data busses. If MUX is High, Channel A comes outon DA0-DA11, OFA; Channel B comes out on DB0-DB11,OFB. If MUX is Low, the output busses are swapped andChannel A comes out on DB0-DB11, OFB; Channel B comesout on DA0-DA11, OFA. To multiplex both channels ontoa single output bus, connect MUX, CLKA and CLKB together(see the Timing Diagram for the multiplexed mode). Themultiplexed data is available on either data bus—the un-used data bus can be disabled with its OE pin.

Grounding and Bypassing

The LTC2294 requires a printed circuit board with a clean,unbroken ground plane. A multilayer board with an inter-nal ground plane is recommended. Layout for the printed

Table 2. MODE Pin FunctionCLOCK DUTY

MODE PIN OUTPUT FORMAN CYCLE STABILIZER

0 Offset Binary Off

1/3VDD Offset Binary On

2/3VDD 2’s Complement On

VDD 2’s Complement Off

Overflow Bit

When OF outputs a logic high the converter is eitheroverranged or underranged.

Output Driver Power

Separate output power and ground pins allow the outputdrivers to be isolated from the analog circuitry. The powersupply for the digital output buffers, OVDD, should be tiedto the same power supply as for the logic being driven. Forexample, if the converter is driving a DSP powered by a 1.8Vsupply, then OVDD should be tied to that same 1.8V supply.

OVDD can be powered with any voltage from 500mV up to3.6V. OGND can be powered with any voltage from GND upto 1V and must be less than OVDD. The logic outputs willswing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin, OE.OE high disables all data outputs including OF. The data ac-cess and bus relinquish times are too slow to allow theoutputs to be enabled and disabled during full speed op-eration. The output Hi-Z state is intended for use during longperiods of inactivity. Channels A and B have independentoutput enable pins (OEA, OEB).


LTC2294

192294fa


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circuit board should ensure that digital and analog signallines are separated as much as possible. In particular, careshould be taken not to run any digital track alongside ananalog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used atthe VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-tors must be located as close to the pins as possible. Ofparticular importance is the 0.1µF capacitor betweenREFH and REFL. This capacitor should be placed as closeto the device as possible (1.5mm or less). A size 0402ceramic capacitor is recommended. The large 2.2µFcapacitor between REFH and REFL can be somewhatfurther away. The traces connecting the pins and bypasscapacitors must be kept short and should be made as wideas possible.

The LTC2294 differential inputs should run paralleland close to each other. The input traces should be asshort as possible to minimize capacitance and to minimizenoise pickup.

Heat Transfer

Most of the heat generated by the LTC2294 is transferredfrom the die through the bottom-side exposed pad andpackage leads onto the printed circuit board. For goodelectrical and thermal performance, the exposed padshould be soldered to a large grounded pad on the PCboard. It is critical that all ground pins are connected to aground plane of sufficient area.

Clock Sources for Undersampling

Undersampling raises the bar on the clock source and thehigher the input frequency, the greater the sensitivity toclock jitter or phase noise. A clock source that degradesSNR of a full-scale signal by 1dB at 70MHz will degradeSNR by 3dB at 140MHz, and 4.5dB at 190MHz.

In cases where absolute clock frequency accuracy isrelatively unimportant and only a single ADC is required,a 3V canned oscillator from vendors such as Saronix orVectron can be placed close to the ADC and simply

connected directly to the ADC. If there is any distance tothe ADC, some source termination to reduce ringing thatmay occur even over a fraction of an inch is advisable. Youmust not allow the clock to overshoot the supplies orperformance will suffer. Do not filter the clock signal witha narrow band filter unless you have a sinusoidal clocksource, as the rise and fall time artifacts present in typicaldigital clock signals will be translated into phase noise.

The lowest phase noise oscillators have single-endedsinusoidal outputs, and for these devices the use of a filterclose to the ADC may be beneficial. This filter should beclose to the ADC to both reduce roundtrip reflection times,as well as reduce the susceptibility of the traces betweenthe filter and the ADC. If you are sensitive to close-in phasenoise, the power supply for oscillators and any buffersmust be very stable, or propagation delay variation withsupply will translate into phase noise. Even though theseclock sources may be regarded as digital devices, do notoperate them on a digital supply. If your clock is also usedto drive digital devices such as an FPGA, you should locatethe oscillator, and any clock fan-out devices close to theADC, and give the routing to the ADC precedence. Theclock signals to the FPGA should have series terminationat the source to prevent high frequency noise from theFPGA disturbing the substrate of the clock fan-out device.If you use an FPGA as a programmable divider, you mustre-time the signal using the original oscillator, and the re-timing flip-flop as well as the oscillator should be close tothe ADC, and powered with a very quiet supply.

For cases where there are multiple ADCs, or where theclock source originates some distance away, differentialclock distribution is advisable. This is advisable both fromthe perspective of EMI, but also to avoid receiving noisefrom digital sources both radiated, as well as propagatedin the waveguides that exist between the layers of multi-layer PCBs. The differential pairs must be close together,and distanced from other signals. The differential pairshould be guarded on both sides with copper distanced atleast 3x the distance between the traces, and groundedwith vias no more than 1/4 inch apart.


20

LTC2294

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C21

0.1µ

F

C27

0.1µ

F

V DD

V DD

V DD

V DD

V DD

V CC

V CM

B

C20

2.2µ

F

C18

1µF

C23

1µF

C34

0.1µ

F

C31

*

C17

0.1µ

F

C14

0.1µ

F

C25

0.1µ

F

C28

2.2µ

F

C35

0.1µ

F

C24

0.1µ

F

C36

4.7µ

F

E3 V DD

3V E5 PWR

GND

V DD

V CC

2294

AI0

1

C1 0.1µ

F

R16

33Ω

R32

OPT

R39

OPT

R1 1k R2 1k R3 1k

R10

1k

R14

49.9

Ω

R20

24.9

Ω

R18 * R24 *

R17

OPT

R22

24.9

Ω

R23

51T2 *C2

90.

1µF

C33

0.1µ

F

J3CL

OCK

INPU

T

U6NC

7SVU

04

U3NC

7SVU

04

24

35

U4NC

7SV8

6P5X

C22

0.1µ

F

C15

0.1µ

F

C12

4.7µ

F6.

3VL1 BEAD

V DD C1

90.

1µF

C11

0.1µ

F

C40.

1µF

C2 2.2µ

F

C10

2.2µ

F

C9 1

µF

C13

1µF

R15

1k

J4AN

ALOG

INPU

T B

V CC

1 2 3

4

••

5

V CM

B

C8 0.1µ

F

C6 *

C44

0.1µ

F

R6 24.9

Ω

R5 * R9 *

R4 OPT

R7 24.9

Ω

R8 51T1 *C3 0.1µ

F

C7 0.1µ

F

J2AN

ALOG

INPU

T A

1 2 3

5

••

4

V CM

A

V CM

A

12

V DD

V DD

34

2/3V

DD

56

1/3V

DD

78

GND

JP1

MOD

E

R34

4.7k

R N1A

33Ω

R N1B

33Ω

R N1C

33Ω

R N1D

33Ω

R N2A

33Ω

R N2B

33Ω

R N2C

33Ω

R N2D

33Ω

R N3A

33Ω

R N3B

33Ω

R N3C

33Ω

R N3D

33Ω

R N4A

33Ω

R N4B

33Ω

R N4C

33Ω

R N5A

33Ω

R N5B

33Ω

R N5C

33Ω

R N5D

33Ω

R N6A

33Ω

R N6B

33Ω

R N6C

33Ω

R N6D

33Ω

C39

1µF

C38

0.01

µFV CC

V DD

BYP

GND

ADJ

OUT

SHDNGN

DIN1 2 3 4

8

U8LT

1763

7 6 5GN

DR2

610

0k

R25

105k

C37

10µF

6.3V

C46

0.1µ

F

E4 GND

C45

100µ

F6.

3VOP

T

C40

0.1µ

FC4

80.

1µF

C47

0.1µ

F1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47

46 45 44

43 42 41 40

39 38 37 36 35 34 33

646362 61 60 59 58 57 56 55 54 53 52 51 50 49

17181920212223242526272829303132

E2 EXT

REF

B

12

V DD

34

V CM

V DD

V CM

B

56

EXT

REF

JP3

SENS

E

E1 EXT

REF

A

12

V DD

34

V CM

V DD

56

EXT

REF

JP2

SENS

EA

C5 0.1µ

FV CC

B4B5 B3 B2 B1 B0 OEB6B7

A4A6A711 12 13 14 15 16 17 18 19

9

20V C

C

74VC

X245

BQX

V CC

8 7 6 5 4 3 2 1 10

A5 A0 T/R

GNDA2A3 A1


A4A6A711 12 13 14 15 16 17 18 19

9

20V C

C

74VC

X245

BQX

V CC

8 7 6 5 4 3 2 1 10

A5 A0 T/R

GNDA2A3 A1

U524

LC02

5

A0 A1 A2 A3

V CC

WP

SCL

SDA

1 2 3 4

8 7 6 5

24

35

U2 U9


A4A6A711 12 13 14 15 16 17 18 19

9

20V C

C

74VC

X245

BQX

V CC

8 7 6 5 4 3 2 1 10

A5 A0 T/R

GNDA2A3 A1


A4A6A711 12 13 14 15 16 17 18 19

9

20V C

C

74VC

X245

BQX

V CC

8 7 6 5 4 3 2 1 10

A5 A0 T/R

GNDA2A3 A1

U10

U11

R N7A

33Ω

R N7B

33Ω

R N7C

33Ω

R N7D

33Ω

R N8A

33Ω

R N8B

33Ω

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 3942 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78

41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 7780 82 84 86 88 90 92 94 96 98 100

79 81 83 85 87 89 91 93 95 97 99

V CC

V SS

SCL

SDA

R33

4.7k

ENAB

LE

V CCI

N

J1ED

GE-C

ON-1

00

R35

100k

14

5 3

2

+C4

10.

1µF

R37

4.99

k

R36

4.99

k

V CCI

N

V SS

SCL

SDA

LTC2

294

A INA

+

A INA

– RE

FHA

REFH

A RE

FLA

REFL

A V D

D CL

KA

CLKB

V D

D RE

FLB

REFL

B RE

FHB

REFH

B A I

NB–

A INB

+

DA5

DA4

DA3

DA2

DA1

DA0

NC NC OFB

DB11

DB10

DB9

DB8

DB7

DB6

DB5

GND VDD

SENSEAVCMAMODE

SHDNAOEAOFA

DA11DA10

DA9DA8DA7DA6

OGNDOVDD

GNDVDD SENSEB VCMB MUX SHDNBOEB NC NC DB0 DB1 DB2DB3DB4OGND OVDD

ASSE

MBL

Y TY

PEDC

851A

-HDC

851A

-M

U1LT

C229

4IUP

LTC2

294I

UP

R5, R

9, R

18, R

2424

.9Ω

12.4

Ω

C6, C

3112

pF8p

F

T1, T

2ET

C1-1

TET

C1-1

-13

INPU

T FR

EQUE

NCY

f IN <

70M

Hzf IN

> 7

0MHz

*VER

SION

TAB

LE

R38


WU UU


LTC2294

212294fa


WU UU

Silkscreen Top

Top Side


22

LTC2294

2294fa


WU UU

Inner Layer 2 GND Inner Layer 3 Power

Bottom Side


LTC2294

232294fa

PACKAGE DESCRIPTIO

U

UP Package64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705)

9 .00 ± 0.10(4 SIDES)

NOTE:1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-52. ALL DIMENSIONS ARE IN MILLIMETERS3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT4. EXPOSED PAD SHALL BE SOLDER PLATED5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE

PIN 1 TOP MARK(SEE NOTE 5)

0.40 ± 0.10

6463

12

BOTTOM VIEW—EXPOSED PAD

7.15 ± 0.10(4-SIDES)

0.75 ± 0.05 R = 0.115TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UP64) QFN 1003

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 ±0.05

7.15 ±0.05(4 SIDES) 8.10 ±0.05 9.50 ±0.05

0.25 ±0.050.50 BSC

PACKAGE OUTLINE

PIN 1CHAMFER

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.www.BDTIC.com/Linear

24

LTC2294

2294fa

RELATED PARTS

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005

RD/LT 0106 REV A • PRINTED IN USA

PART NUMBER DESCRIPTION COMMENTS

LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package



LTC2223 12-Bit, 80Msps ADC 366mW, 68dB SNR, 7mm × 7mm QFN Package














LTC2249 14-Bit, 80Msps ADC 222mW, 73dB SNR, 5mm × 5mm QFN Package

LTC2286 10-Bit, Dual, 25Msps ADC 150mW, 61.8dB SNR, 9mm × 9mm QFN Package



LTC2289 10-Bit, Dual, 80Msps ADC 422mW, 61dB SNR, 9mm × 9mm QFN Package









LTC2299 14-Bit, Dual, 80Msps ADC 444mW, 73dB SNR, 9mm × 9mm QFN Package


ltc2294 - dual 12-bit, 80msps low power 3v adc

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