ltc2216/ltc2215 - 16-bit, 80msps/65msps low noise adc ......ltc2216/ltc2215 1 22165f typical...

LTC2216/LTC2215

122165f

TYPICAL APPLICATION

APPLICATIONS

16-Bit, 80Msps/65Msps Low Noise ADC

The LTC®2216/LTC2215 are 80Msps/65Msps sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400MHz. The input range of the ADC is fi xed at 2.75VP-P.

The LTC2216/LTC2215 are perfect for demanding com-munications applications, with AC performance that includes 81.5dBFS noise fl oor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 85fsRMS allows undersampling of high input frequencies while maintaining excellent noise performance. Maximum DC specs include ±3.5LSB INL, ±1LSB DNL (no missing codes).

The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.

The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer al-lows high performance at full speed with a wide range of clock duty cycles.

n Telecommunicationsn Receiversn Cellular Base Stationsn Spectrum Analysisn Imaging Systemsn ATE

n Sample Rate: 80Msps/65Mspsn 81.5dBFS Noise Floorn 100dB SFDRn SFDR >95dB at 70MHzn 85fsRMS Jittern 2.75VP-P Input Rangen 400MHz Full Power Bandwidth S/Hn Optional Internal Dithern Optional Data Output Randomizern LVDS or CMOS Outputsn Single 3.3V Supplyn Power Dissipation: 970mW/700mWn Clock Duty Cycle Stabilizern Pin-Compatible with LTC2208, LTC2217n 64-Pin (9mm × 9mm) QFN Package

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.All other trademarks are the property of their respective owners.

LTC2216: 64k Point FFT, fIN = 4.9MHz, –1dBFS

–

+S/HAMP

CORRECTIONLOGIC AND

SHIFT REGISTER

OUTPUTDRIVERS

16-BITPIPELINEDADC CORE

INTERNAL ADCREFERENCEGENERATOR

1.575V

COMMON MODE

BIAS VOLTAGE

CLOCK/DUTYCYCLE

CONTROL

D15•••

D0

SHDN DITH MODE LVDS RAND

VCM

ANALOGINPUT

22165 TA01

CMOSORLVDS

0.5V TO 3.6V

3.3V

3.3V

SENSE

OGND

OVDD

2.2μF 1μF

1μF 1μF 1μF

VDD

GND

ADC CONTROL INPUTS

AIN+

ENC +

AIN–

ENC –

OF

CLKOUT

FEATURES DESCRIPTION

22165 TA01b

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0 10 20 30 40

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

LTC2216/LTC2215

222165f

Supply Voltage (VDD) ................................... –0.3V to 4VDigital Output Supply Voltage (OVDD) .......... –0.3V to 4VDigital Output Ground Voltage (OGND) ........ –0.3V to 1VAnalog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V)Digital Output Voltage ................–0.3V to (OVDD + 0.3V)Power Dissipation .............................................2000mWOperating Temperature Range LTC2215C/LTC2216C ............................... 0°C to 70°C LTC2215I/LTC2216I ..............................–40°C to 85°CStorage Temperature Range ..................–65°C to 150°C

OVDD = VDD (Notes 1 and 2)

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

TOP VIEW

65

SENSE 1GND 2VCM 3GND 4VDD 5VDD 6GND 7AIN+ 8AIN– 9

GND 10GND 11

ENC+ 12ENC– 13GND 14VDD 15VDD 16

48 D11+/DA6 47 D11–/DA5 46 D10+/DA4 45 D10–/DA344 D9+/DA2 43 D9–/DA142 D8+/DA041 D8–/CLKOUTA40 CLKOUT+/CLKOUTB 39 CLKOUT–/OFB38 D7+/DB1537 D7–/DB1436 D6+/DB1335 D6–/DB1234 D5+/DB1133 D5–/DB10

64 N

C63

RAN

D62

MOD

E61

LVD

S60

OF+ /O

FA59

OF– /D

A15

58 D

15+ /D

A14

57 D

15/D

A13

56 D

14+ /D

A12

55 D

14–– /D

A11

54 D

13+ /D

A10

53 D

13– –/D

A952

D12

+ /DA8

51 D

12/D

A750

OGN

D49

OV D

D

V DD

17GN

D 18

SHDN

19

DITH

20

D0– /D

B0 2

1DO

+ /DB1

22

D1– /D

B2 2

3D1

+ /DB3

24

D2– /D

B4 2

5D2

+ /DB5

26

D3– /D

B6 2

7D3

+ /DB7

28

D4– /D

B8 2

9 D

4+ /DB9

30

OGN

D 31

OV D

D 32

TJMAX = 150°C, θJA = 20°C/WEXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2215CUP#PBF LTC2215CUP#TRPBF LTC2215UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2215IUP#PBF LTC2215IUP#TRPBF LTC2215UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

LTC2216CUP#PBF LTC2216CUP#TRPBF LTC2216UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2216IUP#PBF LTC2216IUP#TRPBF LTC2216UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2215CUP LTC2215CUP#TR LTC2215UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2215IUP LTC2215IUP#TR LTC2215UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

LTC2216CUP LTC2216CUP#TR LTC2216UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2216IUP LTC2216IUP#TR LTC2216UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

www.linear.com/leadfree/

http://www.linear.com/tapeandreel/

LTC2216/LTC2215

322165f

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)CONVERTER CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

Integral Linearity Error Differential Analog Input (Note 5) l ±1.2 ±3.5 LSB

Differential Linearity Error Differential Analog Input l 0.16/–0.2 ±1 LSB

Offset Error (Note 6) l ±1.5 ±8 mV

Offset Drift ±4 μV/°C

Gain Error External Reference l ±0.3 ±1 %FS

Full-Scale Drift Internal ReferenceExternal Reference

–65±12

ppm/°C

ppm/°C

Transition Noise External Reference 2 LSBRMS

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)ANALOG INPUT

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+ – AIN

–) 3.135V ≤ VDD ≤ 3.465V 2.75 VP-P

VIN, CM Analog Input Common Mode Differential Input (Note 7) l 1.2 1.575 1.8 V

IIN Analog Input Leakage Current 0V ≤ AIN+, AIN

– ≤ VDD l –1 1 μA

ISENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD l –3 3 μA

IMODE MODE Pin Pull-Down Current to GND 10 μA

ILVDS LVDS Pin Pull-Down Current to GND 10 μA

CIN Analog Input Capacitance Sample Mode ENC+ < ENC–

Hold Mode ENC+ > ENC–9.11.8

pFpF

tAP Sample-and-HoldAcquisition Delay Time

0.35 ns

tJITTER Sample-and-HoldAperture Jitter

85 fs RMS

CMRR Analog InputCommon Mode Rejection Ratio

1.2V < (AIN+ = AIN

–) <1.8V 80 dB

BW-3dB Full Power Bandwidth RS < 25Ω 400 MHz

LTC2216/LTC2215

422165f

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS with 2.75V range unless otherwise noted. (Note 4)DYNAMIC ACCURACY

SYMBOL PARAMETER CONDITIONS

LTC2215 LTC2216

UNITSMIN TYP MAX MIN TYP MAX

SNR Signal-to-Noise Ratio 5MHz Input 81.5 81.3 dBFS

15MHz Input, TA = 25°C15MHz Input l

80.880.5

81.481

80.680.2

81.280.8

dBFSdBFS

30MHz Input, TA = 25°C 81.2 81.1 dBFS


8079.7

80.680.2

8079.7

80.580.2

dBFSdBFS

140MHz Input 79 79 dBFS

SFDR Spurious FreeDynamic Range2nd or 3rd Harmonic

5MHz Input 100 100 dBc


8888

10096

8888

10099

dBcdBc



8584

9695

8584

9797

dBcdBc


SFDR Spurious Free Dynamic Range4th Harmonic or Higher


15MHz Input l 95 105 94 105 dBc


70MHz Input l 94 104 93 103 dBc


S/(N+D) Signal-to-NoisePlus Distortion Ratio

5MHz Input 81.5 81.3 dBc


80.380.2

81.280.8

80.280

81.180.7

dBFSdBFS

30MHz Input 80.9 80.8 dBFS


79.379.2

80.380

79.679.4

80.480.1

dBFSdBFS

140MHz Input 78.8 78.8 dBFS

SFDR Spurious Free Dynamic Rangeat –25dBFSDither “OFF”






SFDR Spurious Free Dynamic Rangeat –25dBFSDither “ON”


15MHz Input l 100 115 100 115 dBFS




IMD Intermodulation Distortion fIN1 = 14MHz, fIN2 = 21MHz, –7dBFSfIN1 = 67MHz, fIN2 = 74MHz, –7dBFS

10096

10097

dBcdBc

LTC2216/LTC2215

522165f

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)DIGITAL INPUTS AND DIGITAL OUTPUTS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Encode Inputs (ENC+, ENC–)

VID Differential Input Voltage (Note 7) l 0.2 V

VICM Common Mode Input Voltage Internally SetExternally Set (Note 7) 1.2

1.63

VV

RIN Input Resistance (See Figure 2) 6 kΩCIN Input Capacitance (Note 7) 3 pF

Logic Inputs

VIH High Level Input Voltage VDD = 3.3V l 2 V

VIL Low Level Input Voltage VDD = 3.3V l 0.8 V

IIN Digital Input Current VIN = 0V to VDD l ±10 μA

CIN Digital Input Capacitance (Note 7) 1.5 pF

LOGIC OUTPUTS (CMOS MODE)

OVDD = 3.3V

VOH High Level Output Voltage VDD = 3.3V IO = –10μA

IO = –200μA l 3.1

3.299

3.29

V

V

VOL Low Level Output Voltage VDD = 3.3V IO = 160μA

IO = 1.6mA l

0.01

0.10 0.4

V

V

ISOURCE Output Source Current VOUT = 0V –50 mA

ISINK Output Sink Current VOUT = 3.3V 50 mA

OVDD = 2.5V

VOH High Level Output Voltage VDD = 3.3V IO = –200μA 2.49 V

VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V

OVDD = 1.8V

VOH High Level Output Voltage VDD = 3.3V IO = –200μA 1.79 V

VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V

LOGIC OUTPUTS (LVDS MODE)

STANDARD LVDS

VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV

VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 V

Low Power LVDS

VOD Differential Output Voltage 100Ω Differential Load l 125 175 250 mV

VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 V

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)COMMON MODE BIAS CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 l 1.475 1.575 1.675 V

VCM Output Tempco IOUT = 0 ±60 ppm/°C

VCM Line Regulation 3.135V ≤ VDD ≤ 3.465V 2.4 mV/ V

VCM Output Resistance | IOUT | ≤ 0.8mA 1.1 Ω

LTC2216/LTC2215

622165f

POWER REQUIREMENTS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)TIMING CHARACTERISTICS


LTC2215 LTC2216


VDD Analog Supply Voltage (Note 8) l 3.135 3.3 3.465 3.135 3.3 3.465 V

PSHDN Shutdown Power SHDN = VDD 17 17 mW

Standard LVDS Output Mode

OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 3 3.3 3.6 V

IVDD Analog Supply Current l 217 290 300 370 mA

IOVDD Output Supply Current l 75 90 75 90 mA

PDIS Power Dissipation l 964 1254 1240 1518 mW

Low Power LVDS Output Mode

OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 3 3.3 3.6 V


IOVDD Output Supply Current l 42 50 42 50 mA


CMOS Output Mode

OVDD Output Supply Voltage (Note 8) l 0.5 3.6 0.5 3.6 V




LTC2215 LTC2216


fS Sampling Frequency (Note 8) l 1 65 1 80 MHz

tL ENC Low Time Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

l

l

7.315

7.6927.692

500500

5.944.06

6.256.25

500500

nsns

tH ENC High Time Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

l

l

7.315

7.6927.692

500500

5.944.06

6.256.25

500500

nsns

LVDS Output Mode (Standard and Low Power)

tD ENC to DATA Delay (Note 7) l 1.3 2.5 3.8 1.3 2.5 3.8 ns

tC ENC to CLKOUT Delay (Note 7) l 1.3 2.5 3.8 1.3 2.5 3.8 ns

tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 –0.6 0 0.6 ns

tRISE Output Rise Time 0.5 0.5 ns

tFALL Output Fall Time 0.5 0.5 ns

Data Latency Data Latency 7 7 Cycles

CMOS Output Mode

tD ENC to DATA Delay (Note 7) l 1.3 2.7 4 1.3 2.7 4 ns

tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 1.3 2.7 4 ns

tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 –0.6 0 0.6 ns

Data Latency Data Latency Full Rate CMOSDemuxed

77

77

CyclesCycles

LTC2216/LTC2215

722165f

TIMING DIAGRAM

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND, with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: VDD = 3.3V, fSAMPLE = 65MHz (LTC2215) or 80MHz (LTC2216), LVDS

outputs, differential ENC+/ENC– = 2VP-P sine wave with 1.6V common mode,

input range = 2.75VP-P with differential drive, unless otherwise specifi ed.

Note 5: Integral nonlinearity is defi ned as the deviation of a code from a “best

fi t straight line” to the transfer curve. The deviation is measured from the

center of the quantization band.

Note 6: Offset error is the offset voltage measured from –1/2LSB when the

output code fl ickers between 0000 0000 0000 0000 and 1111 1111 1111

1111 in 2’s complement output mode.

Note 7: Guaranteed by design, not subject to test.

Note 8: Recommended operating conditions.

LVDS Output Mode TimingAll Outputs are Differential and Have LVDS Levels

tH

tD

tC

tL

N – 7 N – 6 N – 5 N – 4 N – 3

ANALOGINPUT

ENC–

ENC+

CLKOUT–

CLKOUT+

D0-D15, OF

22165 TD01

tAPN + 1

N + 2

N + 4

N + 3N

ELECTRICAL CHARACTERISTICS

LTC2216/LTC2215

822165f

tH

tD

tD

tC

tL

N – 8 N – 6 N – 4

N – 7 N – 5 N – 3

ENC–

ENC+

CLKOUTA

CLKOUTB

DA0-DA15, OFA

DB0-DB15, OFB

22165 TD03

tAP

ANALOGINPUT

N + 1

N + 2

N + 4

N + 3N

tAP

ANALOGINPUT

tH

tD

tC

tL

N – 7 N – 6 N – 5 N – 4 N – 3

ENC–

ENC+

CLKOUTA

CLKOUTB

DA0-DA15, OFA

DB0-DB15, OFB22165 TD02

HIGH IMPEDANCE

N + 1

N + 2

N + 4

N + 3N

Demultiplexed CMOS Output Mode TimingAll Outputs are Single-Ended and Have CMOS Levels

Full-Rate CMOS Output Mode TimingAll Outputs are Single-Ended and Have CMOS Levels

TIMING DIAGRAMS

LTC2216/LTC2215

922165f

LTC2216 Integral Nonlinearity (INL) vs Output Code, Dither “Off“

LTC2216 Integral Nonlinearity (INL) vs Output Code, Dither “On“

LTC2216 64k Point FFT, fIN = 15.1MHz, –1dBFS


LTC2216 64k Point FFT, fIN = 15.1MHz, –20dBFS, Dither “Off”

LTC2216 AC Grounded Input Histogram

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2216 64k Point 2-Tone FFT, fIN = 14.25MHz and 21.5MHz, –7dBFS

LTC2216 64k Point FFT, fIN = 15.1MHz, –20dBFS, Dither “On”

LTC2216 Differential Nonlinearity (DNL) vs Output Code

–2.0

–1.5

–1.0

–0.5

0.0

0.5

1.0

1.5

2.0

0 16384 32768 49152 65536

OUTPUT CODE

INL

ER

RO

R (

LS

B)

22165 G01

–2.0

–1.5

–1.0

–0.5

0.0

0.5

1.0

1.5

2.0

0 16384 32768 49152 65536

OUTPUT CODE

INL

ER

RO

R (

LS

B)

22165 G02

–1.0

–0.8

–0.6

–0.4

–0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 16384 32768 49152 65536

OUTPUT CODE

DN

L E

RR

OR

(LS

B)

22165 G03

22165 G04

0

2000

4000

6000

8000

10000

12000

14000

OUTPUT CODE

CO

UN

T

32762 32771 32780

22165 G05

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0 10 20 30 40

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

22165 G06

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0 10 20 30 40

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

22165 G07

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0 10 20 30 40

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

22165 G08

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0 10 20 30 40

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0

0 10 20 30 40

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

22165 G09

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0 10 20 30 40

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

LTC2216/LTC2215

1022165f

LTC2216 SNR vs Input Level,fIN = 15.2MHz




LTC2216 SFDR vs Input Level, fIN = 70.5MHz, Dither “Off”

LTC2216 SFDR vs Input Level, fIN = 15.2MHz, Dither “On”




LTC2216 64k Point 2-Tone FFT,fIN = 14.25MHz and 21.5MHz, –25dBFS, Dither “On”

22165 G10

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0 10 20 30 40

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

0 10 20 30 40

22165 G11 22165 G12

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G13

78

79

80

81

82

INPUT LEVEL (dBFS)

SN

R (

dB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G14

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30 40

22165 G15

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30 40

22165 G16

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30 40

22165 G17

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30 40

22165 G18

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

LTC2216/LTC2215

1122165f

LTC2216 64k Point 2–Tone FFT,fIN = 67.2MHz and 74.4MHz,–25dBFS, Dither “On”




LTC2216 SNR vs Input Level, fIN = 70.5MHz

LTC2216 64k Point 2–Tone FFT, fIN = 67.2MHz and 74.4MHz, –7dBFS





22165 G19

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G20

78

79

80

81

82

INPUT LEVEL (dBFS)

SN

R(d

BFS

)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G21

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30 40

22165 G22

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30 40

22165 G23

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30 40

22165 G24

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30 40

22165 G25

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G26

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G27

78

79

80

81

82

INPUT LEVEL (dBFS)

SN

R (

dB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

LTC2216/LTC2215

1222165f

LTC2216 IVDD vs Sample Rate and Supply Voltage, fIN = 5MHz, –1dBFS

LTC2216 SNR and SFDR vs Clock Duty Cycle, fIN = 5.2MHz

LTC2216 SNR and SFDR vs Sample Rate, fIN = 5.2MHz

LTC2216 SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, –1dBFS


LTC2216 SNR vs Input FrequencyLTC2216 SFDR (HD2 and HD3) vs Input Frequency

LTC2216 SNR and SFDR vs Supply Voltage (VDD), fIN = 5.1MHz

22165 G28

70

75

80

85

90

95

100

105

110

0 50 100 150 200 250

INPUT FREQUENCY (MHz)

SFD

R (

dB

c)

HD2

SFDR

HD3

22165 G29

76

77

78

79

80

81

82

0 50 100 150 200 250


SN

R (

dB

FS)

22165 G30

SAMPLE RATE (Msps)

SN

R (

dB

FS)

AN

D S

FDR

(d

Bc)

SNR

SFDR

LIMIT

70

75

80

85

90

95

100

105

110

0 40 80 120

22165 G31

70

75

80

85

90

95

100

105

110

2.8 3.0 3.2 3.4 3.6

SUPPLY VOLTAGE (V)

SN

R (

dB

FS)

AN

D S

FDR

(d

Bc)

SFDR

SNR

LOWER LIMIT

UPPER LIMIT

22165 G32

SAMPLE RATE (Msps)

I VD

D (

mA

)

VDD = 3.465V

VDD = 3.135V

275

225

325

375

0 40 80 120 160

VDD = 3.3V

22165 G33

60

70

80

90

100

110

30 40 50 60 70

DUTY CYCLE (%)

SN

R(d

BFS)A

ND

SFD

R(d

Bc)

SFDR DCS ON

SFDR DCS OFF

SNR DCS ON

SNR DCS OFF

22165 G34

60

65

70

75

80

85

90

95

100

105

110

0.5 0.75 1 1.25 1.5 1.75 2

ANALOG INPUT COMMON MODE VOLTAGE (V)

SFD

R (

dB

c)

70MHz

5MHz

LTC2216/LTC2215

1322165f





LTC2215 Differential Nonlinearity (DNL) vs Output Code

LTC221564k Point FFT, fIN = 15.1MHz, –20dBFS, Dither “On”


LTC2215 Integral Nonlinearity (INL) vs Output Code, Dither “On”

LTC2215 Integral Nonlinearity (INL) vs Output Code, Dither “Off”

LTC2215 AC Grounded Input Histogram

–2.0

–1.5

–1.0

–0.5

0.0

0.5

1.0

1.5

2.0

0 16384 32768 49152 65536

OUTPUT CODE

INL

ER

RO

R (

LS

B)

22165 G42

–2.0

–1.5

–1.0

–0.5

0.0

0.5

1.0

1.5

2.0

0 16384 32768 49152 65536

OUTPUT CODE

INL

ER

RO

R (

LS

B)

22165 G43

–1.0

–0.8

–0.6

–0.4

–0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 16384 32768 49152 65536

OUTPUT CODE

DN

L E

RR

OR

(LS

B)

22165 G44

22165 G45

0

2000

4000

6000

8000

10000

12000

14000

OUTPUT CODE

CO

UN

T

3275 32768 32777

22165 G50

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G46

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G47

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G48

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G49

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

LTC2216/LTC2215

1422165f


LTC2215 64k Point 2–Tone FFT,fIN = 14.25MHz and 21.5MHz,–25dBFS, Dither “On”









22165 G51

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G52

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G53

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G54

78

79

80

81

82

INPUT LEVEL (dBFS)

SN

R (

dB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G55

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G56

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)A

MP

LIT

UD

E(d

BFS

)

0 10 20 30

22165 G57

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G58

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G59

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

LTC2216/LTC2215

1522165f










LTC2215 64k Point 2–Tone FFT, fIN = 67.2MHz and 74.4MHz, –25dBFS, Dither “On”

22165 G60

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G61

78

79

80

81

82

INPUT LEVEL (dBFS)

SN

R(d

BFS

)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G62

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G63

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G64

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G65

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

AM

PLIT

UD

E(d

BFS

)

0 10 20 30

22165 G66

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G67

30

40

50

60

70

80

90

100

110

120

130

140

INPUT LEVEL (dBFS)

SFD

R(d

Bc

AN

DdB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

22165 G68

78

79

80

81

82

INPUT LEVEL (dBFS)

SN

R (

dB

FS)

–80 –70 –60 –50 –40 –20–30 –10 0

LTC2216/LTC2215

1622165f

LTC2215 IVDD vs Sample Rate and Supply Voltage, fIN = 5MHz, –1dBFS

LTC2215 SFDR (HD2 and HD3) vs Input Frequency LTC2215 SNR vs Input Frequency

LTC2215 SNR and SFDR vs Sample Rate, fIN = 5.2MHz


LTC2215 SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, –1dBFS

LTC2215 SNR and SFDR vs Clock Duty Cycle, fIN = 5.2MHz

LTC2215 SNR and SFDR vs Supply Voltage (VDD), fIN = 5.1MHz

22165 G69

70

75

80

85

90

95

100

105

110


SFD

R (

dB

c)

0 50 100 150 200 250

SFDR

HD2

HD3

22165 G70

76

77

78

79

80

81

82

0 50 100 150 200 250


SN

R (

dB

FS)

22165 G71

SAMPLE RATE (Msps)

SN

R (

dB

FS)

AN

D S

FDR

(d

Bc)

LIMIT

70

75

80

85

90

95

100

105

110

0 40 80 120

SNR

SFDR

22165 G72

70

75

80

85

90

95

100

105

110

2.8 3.0 3.2 3.4 3.6

SUPPLY VOLTAGE (V)

SN

R (

dB

FS)

AN

D S

FDR

(d

Bc)

SFDR

SNR

LOWER LIMIT

UPPER LIMIT

22165 G73

SAMPLE RATE (Msps)

I VD

D (

mA

) VDD = 3.465V

VDD = 3.135V

VDD = 3.3V

125

175

225

275

150

200

250

0 40 80 120 160

22165 G74

60

70

80

90

100

110

DUTY CYCLE (%)

SN

R(d

BFS)A

ND

SFD

R(d

Bc)

30 40 50 60 70

SFDR DCS ON

SFDR DCS OFF

SNR DCS ON

SNR DCS OFF

60

65

70

75

80

85

90

95

100

105

110

0.5 0.75 1 1.25 1.5 1.75 2

ANALOG INPUT COMMON MODE VOLTAGE (V)

SFD

R (

dB

c)

70MHz

5MHz

22165 G75

LTC2216/LTC2215

1722165f

LTC2216/LTC2215 Mid–Scale Settling After Wake-Up from Shutdown or Starting Encode Clock

LTC2216/LTC2215 Full–Scale Settling After Wake-Up from Shutdown or Starting Encode Clock

LTC2216/LTC2215 Normalized Full-Scale vs Temperature, External Reference, 5 Units


LTC2216/LTC2215 Input Offset Voltage vs Temperature,Internal Reference, 5 Units

LTC2216/LTC2215 Normalized Full-Scale vs Temperature, Internal Reference, 5 Units

LTC2216/LTC2215 Input Offset Voltage vs Temperature, External Reference, 5 Units

22165 G76

0.995

0.996

0.997

0.998

0.999

1

1.001

1.002

1.003

1.004

1.005

NO

RM

AL

IZE

D F

UL

L S

CA

LE

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

22165 G77

–5

–4

–3

–2

–1

0

1

2

3

4

5

OFFS

ET V

OLT

AG

E (

mV

)

–40 –20 0 20 40 60 80

TEMPERATURE (°C) 22165 G78

0.995

0.996

0.997

0.998

0.999

1

1.001

1.002

1.003

1.004

1.005

NO

RM

AL

IZE

D F

UL

L S

CA

LE

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

22165 G79

–5

–4

–3

–2

–1

0

1

2

3

4

5

OFFS

ET V

OLT

AG

E (

mV

)

–40 –20 0 20 40 60 80

TEMPERATURE (°C)22165 G80

–0.5

–0.4

–0.3

–0.2

–0.1

0.0

0.1

0.2

0.3

0.4

0.5

FU

LL–

SC

AL

E E

RR

OR

(%

)

0 300 600 900 1200 1500

TIME AFTER WAKE-UP OR CLOCK START (μs)

CLOCK START

WAKE-UP

22165 G81

–0.5

–0.4

–0.3

–0.2

–0.1

0.0

0.1

0.2

0.3

0.4

0.5

FU

LL–

SC

AL

E E

RR

OR

(%

)

CLOCK START

WAKE-UP

TIME AFTER WAKE-UP OR CLOCK START (μs)

0 400 800 1200 1600 2000

LTC2216/LTC2215

1822165f

For CMOS Mode. Full Rate or Demultiplexed

SENSE (Pin 1): Reference Mode Select and External Refer-ence Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full-scale ADC range of 2.75V.

GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.

VCM (Pin 3): 1.575V Output. Optimum voltage for input com-mon mode. Must be bypassed to ground with a minimum of 2.2μF. Ceramic chip capacitors are recommended.

VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1μF ceramic chip capacitors.

AIN+ (Pin 8): Positive Differential Analog Input.

AIN– (Pin 9): Negative Differential Analog Input.

ENC+ (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2kΩ resistor. Output data can be latched on the rising edge of ENC+.

ENC– (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC–. Internally biased to 1.6V through a 6.2kΩ resistor. By-pass to ground with a 0.1μF capacitor for a single-ended Encode signal.

SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state.

DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation.

DB0-DB15 (Pins 21-30 and 33-38): Digital Outputs, B Bus. DB15 is the MSB. Active in demultiplexed mode. The B bus is in high impedance state in full rate CMOS mode.

OGND (Pins 31 and 50): Output Driver Ground.

OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 1μF capacitor.

OFB (Pin 39): Over/Under Flow Digital Output for the B Bus. OFB is high when an over or under fl ow has occurred on the B bus. At high impedance state in full rate CMOS mode.

CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the falling edge of CLKOUTB.

CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA.

DA0-DA15 (Pins 42-48 and 51-59): Digital Outputs, A Bus. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode.

OFA (Pin 60): Over/Under Flow Digital Output for the A Bus. OFA is high when an over or under fl ow has occurred on the A bus.

LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connect-ing LVDS to VDD selects Standard LVDS mode.

MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle sta-bilizer. Connecting MODE to 2/3VDD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer.

RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference.

NC (Pin 64): Not Connected Internally. For pin compatibility with the LTC2208 this pin should be connected to GND or VDD as required. Otherwise no connection.

GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground.

PIN FUNCTIONS

LTC2216/LTC2215

1922165f

For LVDS Mode. STANDARD or LOW POWER

SENSE (Pin 1): Reference Mode Select and External Refer-ence Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full-scale ADC range of 2.75V.

GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.

VCM (Pin 3): 1.575V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2μF. Ceramic chip capacitors are recom-mended.

VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1μF ceramic chip capacitors.

AIN+ (Pin 8): Positive Differential Analog Input.

AIN– (Pin 9): Negative Differential Analog Input.

ENC+ (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2kΩ resistor. Output data can be latched on the rising edge of ENC+.

ENC– (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC–. Internally biased to 1.6V through a 6.2kΩ resistor. By-pass to ground with a 0.1μF capacitor for a single-ended Encode signal.

SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are set in high impedance state.

DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of the data sheet for details on dither operation.

D0–/D0+ to D15–/D15+ (Pins 21-30, 33-38, 41-48 and 51-58): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D15+/D15– is the MSB.

OGND (Pins 31 and 50): Output Driver Ground.

OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF capacitor.

CLKOUT–/CLKOUT+ (Pins 39 and 40): LVDS Data Valid 0utput. Latch data on the rising edge of CLKOUT+, falling edge of CLKOUT–.

OF–/OF+ (Pins 59 and 60): Over/Under Flow Digital Output OF is high when an over or under fl ow has occurred.

LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connect-ing LVDS to VDD selects Standard LVDS mode.

MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle sta-bilizer. Connecting MODE to 2/3VDD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer.

RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. The mode of operation reduces the effects of digital output interference.

NC (Pin 64): Not Connected Internally. For pin compat-ibility with the LTC2208 this pin should be connected to GND or VDD as required. Otherwise no connection.

GND (Exposed Pad Pin 65): ADC Power Ground. The exposed pad on the bottom of the package must be sol-dered to ground.

PIN FUNCTIONS

LTC2216/LTC2215

2022165f

ADC CLOCKS

DIFFERENTIALINPUT

LOW JITTERCLOCKDRIVER

DITHERSIGNAL

GENERATOR

FIRST PIPELINEDADC STAGE

FIFTH PIPELINEDADC STAGE

FOURTH PIPELINEDADC STAGE

SECOND PIPELINEDADC STAGE

ENC+ ENC–

CORRECTION LOGICAND

SHIFT REGISTER

DITHM0DE

OGND

CLKOUT+CLKOUT–OF+

OF–

D15+

D15–

OVDD

D0+

D0–

22165 F01

INPUTS/H

AIN–

AIN+

THIRD PIPELINEDADC STAGE

OUTPUTDRIVERS

CONTROLLOGIC

SHDN RAND LVDS

•••

VDD

GND

PGA

SENSE

VCMBUFFER

ADCREFERENCE

VOLTAGEREFERENCE

RANGESELECT

Figure 1. Functional Block Diagram

BLOCK DIAGRAM

LTC2216/LTC2215

2122165f

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band lim-ited to frequencies above DC to below half the sampling frequency (Nyquist Frequency).

Signal-to-Noise Ratio

The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the fi rst fi ve harmonics.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (Nyquist Frequency). THD is expressed as:

THD Log V V V V VN= − + + +( )( )20 2

23

24

2 21... /

where V1 is the RMS amplitude of the fundamental fre-quency and V2 through VN are the amplitudes of the second through nth harmonics.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.

For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defi ned as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product.

Spurious Free Dynamic Range (SFDR)

The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full-scale and expressed in dBFS.

Full Power Bandwidth

The Full Power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB from a full-scale input signal.

Aperture Delay Time

The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample- and-hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal-to-noise ratio term due to the jitter alone will be:

SNRJITTER = –20log (2π • fIN • tJITTER)

This formula states SNR due to jitter alone at any ampli-tude in terms of dBc.

OPERATION

LTC2216/LTC2215

2222165f

CONVERTER OPERATION

The LTC2216/LTC2215 are CMOS pipelined multistep convert-ers with a low noise front-end. As shown in Figure 1, these converters have fi ve pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. The encode input is also differential for improved common mode noise immunity.

The LTC2216/LTC2215 have two phases of operation, deter-mined by the state of the differential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low.

Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage amplifi er. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplifi ed and output by the residue amplifi er. Successive stages oper-ate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.

When ENC is low, the analog input is sampled differen-tially directly onto the input sample-and-hold capacitors, inside the “input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the voltage on the sample capacitors is held. While ENC is high, the held input voltage is buffered by the S/H amplifi er which drives the fi rst pipelined ADC stage. The fi rst stage acquires the output of the S/H amplifi er during the high phase of ENC. When ENC goes back low, the fi rst stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes high, the second stage produces its residue which is acquired by the third stage. An identi-cal process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fi fth stage for fi nal evaluation.

Each ADC stage following the fi rst has additional range to accommodate fl ash and amplifi er offset errors. Results

from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2216/LTC2215 CMOS differential sample and hold. The differ-ential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.

During the sample phase when ENC is low, the NMOS transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions for high to low, the inputs are reconnected to

Figure 2. Equivalent Input Circuit

VDD

LTC2216/LTC2215

AIN+

22165 F02

VDD

AIN–

ENC–

ENC+

1.6V

6k

VDD

1.6V

6k

RPARASITIC3Ω

CSAMPLE7.3pF

CSAMPLE7.3pF

CPARASITIC1.8pF

CPARASITIC1.8pF

RPARASITIC3Ω

RON20Ω

RON20Ω

APPLICATIONS INFORMATION

LTC2216/LTC2215

2322165f

the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential drive to achieve specifi ed performance. Each input should swing ±0.6875V for the 2.75V range, around a common mode voltage of 1.575V. The VCM output pin (Pin 3) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 2.2μF or greater.

Input Drive Impedance

As with all high performance, high speed ADCs the dynamic performance of the LTC2216/LTC2215 can be infl uenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can infl uence SFDR. At the falling edge of ENC the sample and hold circuit will connect the sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2 • fENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.

For the best performance it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.

INPUT DRIVE CIRCUITS

Input Filtering

A fi rst-order RC low-pass fi lter at the input of the ADC can serve two functions: limit the noise from input cir-cuitry and provide isolation from ADC S/H switching. The LTC2216/LTC2215 have a very broadband S/H circuit, DC to 400MHz. This can be used in a wide range of ap-plications, therefore, it is not possible to provide a single recommended RC fi lter.

Figures 3 and 4 show two examples of input RC fi ltering for two ranges of input frequencies. In general it is desirable to make the capacitors as large as can be tolerated–this will help suppress random noise as well as noise coupled from the digital circuitry. The LTC2216/LTC2215 do not require any input fi lter to achieve data sheet specifi ca-tions; however, no fi ltering will put more stringent noise requirements on the input drive circuitry.

Transformer Coupled Circuits

Figure 3 shows the LTC2216/LTC2215 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50Ω can reduce the input bandwidth and increase

Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 5MHz to 100MHz

35Ω

5Ω

35Ω

10Ω

10Ω

5Ω

5Ω

0.1μF

AIN+

AIN–

8.2pF

2.2μF

8.2pF

8.2pF

VCM

T1

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

22165 F03

LTC2216/

LTC2215


LTC2216/LTC2215

2422165f

high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequen-cies below 1MHz.

Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics.

Figure 4 shows transformer coupling using a transmis-sion line balun transformer. This type of transformer has much better high-frequency response and balance than fl ux coupled center-tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.575V.

Figure 5. DC Coupled Input with Differential Amplifi er

0.1μF

AIN+

AIN–

4.7pF

2.2μF

4.7pF

4.7pF

VCM

ANALOGINPUT

0.1μF

0.1μF5Ω

25Ω

5Ω

25Ω5Ω

10Ω

10Ω

T11:1

T1 = MA/COM ETC1-1-13RESISTORS, CAPACITORSARE 0402 PACKAGE SIZEEXCEPT 2.2μF

22165 F04

LTC2216/

LTC2215

Figure 4. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 100MHz to 250MHz

– –

++

AIN+

AIN–

2.2μF

12pF

12pF

VCM

ANALOGINPUT

22165 F05

CM

AMPLIFIER = LTC6600-20,LTC1993, ETC.

HIGH SPEEDDIFFERENTIAL

AMPLIFIER 25Ω

25Ω

LTC2216/

LTC2215

PGA

1.575V

SENSE

VCMBUFFER

INTERNALADC

REFERENCE

RANGESELECT

AND GAINCONTROL

2.5VBANDGAP

REFERENCE

2.2μF

TIE TO VDD TO USE INTERNAL 2.5V

REFERENCEOR INPUT AN

EXTERNAL 2.5V REFERENCE

OR INPUT ANEXTERNAL 1.25V

REFERENCE

22165 F06

Figure 6. Reference Circuit

Reference Operation

Figure 6 shows the LTC2216/LTC2215 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifi er and control circuit. The LTC2216/LTC2215 has three modes of reference operation: Internal Refer-ence, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full-scale range of 2.75VP-P. A 1.575V output, VCM, is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference; which will not be stable without this capacitor. The minimum value required for stability is 2.2μF.

Direct Coupled Circuits

Figure 5 demonstrates the use of a differential amplifi er to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop amplifi er will de-grade the ADC SFDR at high input frequencies. Additionally, wideband op amps or differential amplifi ers tend to have high noise. As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input.


LTC2216/LTC2215

2522165f

The internal programmable gain amplifi er provides the internal reference voltage for the ADC. This amplifi er has very stringent settling requirements and therefore is not accessible for external use.

The SENSE pin can be driven ±5% around the nominal 2.5V or 1.25V external reference inputs. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1μF ceramic capacitor.

Figure 7. A 2.75V Range ADC with an External 2.5V Reference

VCM

SENSE

1.575V

3.3V

2.2μF

2.2μF1μF

22165 F07

LTC1461-2.52 6

4

LTC2216/

LTC2215

3. If the ADC is clocked with a fi xed-frequency sinusoidal signal, fi lter the encode signal to reduce wideband noise.

4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise.

The encode inputs have a common mode range of 1.2V to VDD. Each input may be driven from ground to VDD for single-ended drive.

Driving the Encode Inputs

The noise performance of the LTC2216/LTC2215 can depend on the encode signal quality as much as on the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC oper-ating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits.

Any noise present on the encode signal will result in ad-ditional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.

In applications where jitter is critical (high input frequen-cies), take the following into consideration:

1. Differential drive should be used.

2. Use as large an amplitude possible. If using trans-former coupling, use a higher turns ratio to increase the amplitude.

Figure 8. Equivalent Encode Input Circuit

LTC2216/LTC2215

22165 F08

ENC–

ENC+

1.6V

1.6V

6k

6k

TO INTERNALADC CLOCK

DRIVERS

VDD

VDD

VDD

Figure 9. Balun-Driven Encode

50Ω100Ω

8.2pF

0.1μF

0.1μF

0.1μF

T1

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

50Ω

22165 F09

ENC–

ENC+

LTC2216/

LTC2215


LTC2216/LTC2215

2622165f

use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2216/LTC2215 sample rate is determined by droop affecting the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junc-tion leakage will discharge the capacitors. The specifi ed minimum operating frequency for both the LTC2215 and LTC2216 is 1Msps.

DIGITAL OUTPUTS

Digital Output Modes

The LTC2216/LTC2215 can operate in four digital output modes: standard LVDS, low power LVDS, full rate CMOS, and demultiplexed CMOS. The LVDS pin selects the mode of operation. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the LVDS pin.

Table 1. LVDS Pin Function

LVDS DIGITAL OUTPUT MODE

0V(GND) Full-Rate CMOS

1/3VDD Demultiplexed CMOS

2/3VDD Low Power LVDS

VDD LVDS

Digital Output Buffers (CMOS Modes)

Figure 11 shows an equivalent circuit for a single output buffer in CMOS Mode, Full-Rate or Demultiplexed. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and eliminates the need for external damping resistors.

As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2216/LTC2215 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as the

22165 F11

ENC–

ENC+

3.3V

3.3V

D0

Q0

Q0

MC100LVELT22 130Ω 130Ω

83Ω 83Ω

LTC2216/

LTC2215

Figure 11. ENC Drive Using a CMOS to PECL Translator

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC2216 is 80Msps, while the maximum encode rate for the LTC2215 is 65Msps. For the ADCs to operate properly the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 5.94ns for the LTC2216 internal circuitry to have enough settling time for proper operation. For the LTC2215, each half cycle must be at least 7.31ns. Achieving a pre-cise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended ENCODE signal asymmetric rise and fall times can result in duty cycles that are far from 50%.

An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC pin to sample the analog input. The falling edge of ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To

Figure 10. Single-Ended ENC Drive,Not Recommended for Low Jitter

22165 F10

ENC–1.6V

VTHRESHOLD = 1.6VENC+

0.1μF

LTC2216/

LTC2215


LTC2216/LTC2215

2722165f

resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length.

In Low Power LVDS Mode 1.75mA is steered between the differential outputs, resulting in ±175mV at the LVDS receiver’s 100Ω termination resistor. The output com-mon mode voltage is 1.20V, the same as standard LVDS Mode.

Data Format

The LTC2216/LTC2215 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 2 shows the logic states for the MODE pin.

Table 2. MODE Pin Function

MODE OUTPUT FORMATCLOCK DUTY

CYCLE STABILIZER

0V(GND) Offset Binary Off

1/3VDD Offset Binary On

2/3VDD 2’s Complement On

VDD 2’s Complement Off

22165 F12

OVDD

VDD VDD

0.1μF

TYPICALDATAOUTPUT

OGND

OVDD 0.5VTO 3.6V

PREDRIVERLOGIC

DATAFROM

LATCH

43Ω

LTC2216/LTC2215

Figure 12. Equivalent Circuit for a Digital Output Buffer

ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used, but is not required since the ADC has a series resistor of 43Ω on-chip.

Lower OVDD voltages will also help reduce interference from the digital outputs.

Digital Output Buffers (LVDS Modes)

Figure 13 shows an equivalent circuit for an LVDS output pair. A 3.5mA current is steered from OUT+ to OUT– or vice versa, which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output volt-age to 1.20V. For proper operation each LVDS output pair must be terminated with an external 100Ω termination

22165 F13

3.5mA

1.20V

LVDSRECEIVER

OGND

10k 10k

VDD

VDD

0.1μF

OVDD3.3V

PREDRIVERLOGIC

DATAFROM

LATCH

+

–

OVDD

OVDD

43Ω

43Ω

100Ω

LTC2216/LTC2215

Figure 13. Equivalent Output Buffer in LVDS Mode


LTC2216/LTC2215

2822165f

Overfl ow Bit

An overfl ow output bit (OF) indicates when the converter is over-ranged or under-ranged. In CMOS mode, a logic high on the OFA pin indicates an overfl ow or underfl ow on the A data bus, while a logic high on the OFB pin indicates an overfl ow on the B data bus. In LVDS mode, a differen-tial logic high on OF+/OF– pins indicates an overfl ow or underfl ow.

Output Clock

The ADC has a delayed version of the encode input avail-able as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal en-code. In both CMOS modes, A bus data will be updated as CLKOUTA falls and CLKOUTB rises. In demultiplexed CMOS mode the B bus data will be updated as CLKOUTA falls and CLKOUTB rises.

In Full Rate CMOS Mode, only the A data bus is active; data may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB.

In demultiplexed CMOS mode CLKOUTA and CLKOUTB will toggle at 1/2 the frequency of the encode signal. Both the A bus and the B bus may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB.

Digital Output Randomizer

Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling, or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise fl oor for a large reduction in unwanted tone amplitude.

The digital output is “Randomized” by applying an exclu-sive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output

are not affected. The output Randomizer function is active when the RAND pin is high.

Output Driver Power

Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. In CMOS mode OVDD can be powered with any logic voltage up to the 3.6V. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. In LVDS Mode, OVDD should be connected to a 3.3V supply and OGND should be connected to GND.

Figure 14. Functional Equivalent of Digital Output Randomizer

•••

CLKOUT

OF

D15 D0

D14 D0

D2 D0

D1 D0

D0D0

D1

RAND = HIGH,SCRAMBLE

ENABLED

D2

D14

D15

OF

CLKOUT

RAND

22165 F14

LTC2216/LTC2215


LTC2216/LTC2215

2922165f

Figure 15. Descrambling a Scrambled Digital Output

•••

D1

D0

D2

D14

D15

PC BOARD

FPGA

CLKOUT

OF

D15 D0

D14 D0

D2 D0

D1 D0

D0

22165 F15

LTC2216/

LTC2215

Internal Dither

The LTC2216/LTC2215 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels.

As shown in Figure 16, the output of the sample-and-hold amplifi er is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in typically less than 0.5dB elevation in the noise fl oor of the ADC, as compared to the noise fl oor with dither off when a suitable input termination is provided (see Demo Board schematic DC996B).

Figure 16. Functional Equivalent Block Diagram of Internal Dither Circuit

+ –

AIN–

AIN+

S/HAMP

DIGITALSUMMATION

OUTPUTDRIVERS

MULTIBIT DEEPPSEUDO-RANDOM

NUMBERGENERATOR

16-BITPIPELINEDADC CORE

PRECISIONDAC

CLOCK/DUTYCYCLE

CONTROL

CLKOUTOF

D15•••

D0

ENC

DITHER ENABLEHIGH = DITHER ONLOW = DITHER OFF

DITHENC

ANALOGINPUT

22165 F16

LTC2216/LTC2215


LTC2216/LTC2215

3022165f

Grounding and Bypassing

The LTC2216/LTC2215 requires a printed circuit board with aclean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2216/LTC2215 has been optimized for a fl owthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.

The LTC2216/LTC2215 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.

Heat Transfer

Most of the heat generated by the LTC2216/LTC2215 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of suffi cient area with as many vias as possible.


LTC2216/LTC2215

3122165f

Layer 1 Component Side Layer 2 GND Plane


LTC2216/LTC2215

3222165f


Layer 3 GND Layer 4 GND

LTC2216/LTC2215

3322165f

Layer 5 GND Layer 6 Bottom Side


LTC2216/LTC2215

3422165f

12

25

26

47

48

1

2

23

36

37

VC1

VC2

VC3

VC4

VC5

VE1

VE2

VE3

VE4

VE5

U3

FIN

11

08

3.3

V

EN

12

EN

34

EN

58

EN

78

EN

I1N

I1P

I2N

I2P

I3N

I3P

I4N

I4P

I5N

I5P

I6N

I6P

I7N

I7P

I8N

I8P

O1

NO

1P

O2

NO

2P

O3

NO

3P

O4

NO

4P

O5

NO

5P

O6

NO

6P

O7

NO

7P

O8

NO

8P

3

22

27

46

13 4 5 6 7 8 9

10

11

14

15

16

17

18

19

20

21

2 4 6 81

01

21

41

61

82

02

22

42

62

83

03

23

43

63

84

04

24

44

64

85

05

25

4

1 3 5 7 9 11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

10

0

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

3

22

27

46

13 4 5 6 7 8 9

10

11

14

15

16

17

18

19

20

21

U2

LTC

22

16

IUP

/LT

C2

21

5IU

P

SE

NS

E

GN

D2

VC

M

GN

D

VD

D5

VD

D6

GN

D7

AIN

P

AIN

N

GN

D1

0

GN

D1

1

EN

CP

EN

CN

GN

D1

4

VD

D1

5

VD

D1

6

D1

1+

D1

1–

D1

0+

D1

0–

D9

+

D9

–

D8

+

D8

–

CL

KC

OU

T+

CL

KO

UT

–

D7

+

D7

–

D8

+

D8

–

D5

+

D5

–

1 2 3 4 5 6 7 8 9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

NC

RAND

MODE

LVDS

OF+

OF–

D15+

D15–

D14+

D14–

D13+

D13–

D12+

D12–

OGND50

OVDD49

17

18

19

20

21

22

23

24

25

26

27

27

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

VDD17

GND18

SHDN

DITH

D0–

D0+

D1–

D1+

D2–

D2+

D3–

D3+

D4–

D4+

OGND31

OVDD32

1 2 3 4

8 7 6 5

U5

FIN

11

01

K8

X

C1

50

.1μ

F

R4

11

00

Ω

RIN

–

GN

D

EN

GN

D

RIN

+

VC

C

DO

UT

+

DO

UT

–

22165 F

17

C5

0.0

1μF

C7

0.0

1μF

C1

20

.1μ

F

C6

0.0

1μF

C4

8.2

pF

C3

0.0

1μF

C1

32

.2μ

F

R1

41

00

0Ω

R1

55

Ω

C2

60

.1μ

F

C2

50

.1μ

F

C1

60

.1μ

F

C1

8O

PT

C1

9O

PT

R4

48

6.6

Ω

R1

13

3.2

Ω

R1

23

3.2

Ω

R1

31

00

Ω

R2

81

0Ω

R1

61

00

Ω

R1

71

00

ΩR

91

0Ω

R1

01

0Ω

R2

71

0Ω

C1

72

.2μ

F

VC

C

R3

71

00

Ω

C8

4.7

pF

R5

5.1

Ω

R4

5.1

Ω

R4

2FE

RR

ITE

BE

AD

R4

3FE

RR

ITE

BE

AD

L1

56

nH

••

• •

••

C1

08

.2p

F

R3

68

6.6

Ω

R2

49

.9Ω

R1

49

.9Ω

C8

8.2

pF C

20

.01μ

F

C1

0.0

1μF

T1

MA

BA

-00

71

59

-0

00

00

0

TP

1E

XT

RE

F

T2

T3

ET

C1

-1-1

3

J5 AIN

R8

10

00

Ω

R6

10

00

Ω

J3

R7

10

00

Ω

3.3

V

J7E

NC

OD

EC

LO

CK

2 4 6

1 3 5

DIT

HE

R

ON

OFF

VC

C

VC

C

VC

C

SH

DN

RU

N

2 4 6

1 3 5

VD

D

GN

D

2 4 6

1 3 5

R2

41

00

k

R2

64

99

0Ω

TP

53

.3V

TP

2P

WR

GN

D

C3

50

.1μ

F

C3

60

.1μ

F

C2

80

.1μ

F

C2

90

.1μ

F

C3

00

.1μ

F

C2

00

.1μ

F

C2

20

.1μ

F

C3

40

.1μ

F

C3

10

.1μ

F

C3

20

.1μ

F

C3

84

.7μ

FC

24

4.7

μF

C1

44

.7μ

F

12

25

26

47

48

1

2

23

36

37

VC1

VC2

VC3

VC4

VC5

VE1

VE2

VE3

VE4

VE5

U4

FIN

11

08

3.3

V

EN

12

EN

34

EN

58

EN

78

EN

I1N

I1P

I2N

I2P

I3N

I3P

I4N

I4P

I5N

I5P

I6N

I6P

I7N

I7P

I8N

I8P

O1

NO

1P

O2

NO

2P

O3

NO

3P

O4

NO

4P

O5

NO

5P

O6

NO

6P

O7

NO

7P

O8

NO

8P

5 44

43

42

41

40

39

38

35

34

33

32

31

30

29

28

45

44

43

42

41

40

39

38

35

34

33

32

31

30

29

28

R3

01

00

Ω

R2

31

00

Ω

R2

21

00

Ω

R2

11

00

Ω

R2

01

00

Ω

R1

91

00

Ω

R1

81

00

Ω

R3

11

00

Ω

R4

01

00

Ω

R3

91

00

Ω

R3

81

00

Ω

R3

51

00

Ω

R3

41

00

Ω

R3

31

00

Ω

R3

21

00

ΩR

29

49

90

Ω

R2

54

99

0Ω

U1

24

LC

02

ST

VC

C

GN

D

6C

L

6D

A

WP

A2

A1

A0

6 5 7 3 2 1

48

3.3

V

C2

70

.1μ

F

AR

RA

YE

EP

RO

M

R3

DN

P

2 4 6

1 3 5V

DD

GN

D

ON

OFF

J4

65

J1E

J1O

ME

C8

-15

0-0

2-L

-D-E

DG

E_

CO

NN

RE

-DIM

J2 M

OD

EJ9

AU

X P

WR

CO

NN

EC

TO

R

R4

58

6.6

Ω

AS

SE

MB

LY

* V

ER

SIO

N T

AB

LE

U2

BIT

SC

8R

45

DC

99

6B

-ELT

C2

21

7IU

P1

64

.7p

F8

6.6

DC

99

6B

-FLT

C2

21

7IU

P1

61

.8p

F1

82

DC

99

6B

-GLT

C2

21

6IU

P1

64

.7p

F8

6.6

DC

99

6B

-HLT

C2

21

6IU

P1

61

.8p

F

C9

-10

8.2

pF

3.9

pF

8.2

pF

3.9

pF

L1

56

nH

18

nH

56

nH

18

nH

18

2

R3

6,

44

86

.6

43

.2

86

.6

43

.2

T2

MA

BA

ES

00

60

WB

C1

-1L

B

MA

BA

ES

00

60

WB

C1

-1L

B

DC

99

6B

-ILT

C2

21

5IU

P1

64

.7p

F8

6.6

DC

99

6B

-JLT

C2

21

5IU

P1

64

.7p

F

8.2

pF

7.9

pF

56

nH

18

nH

18

2

86

.6

43

.2

MA

BA

ES

00

60

WB

C1

-1L

B

1M

Hz

TO

70

MH

z

1M

Hz

TO

70

MH

z

INP

UT

FR

EQ

UE

NC

Y

70M

Hz

TO

140M

Hz

70M

Hz

TO

140M

Hz

1M

Hz

TO

70

MH

z

70M

Hz

TO

140M

Hz


LTC2216/LTC2215

3522165f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTIONUP Package

64-Lead Plastic QFN (9mm × 9mm)(Reference LTC DWG # 05-08-1705)

9 .00 ± 0.10(4 SIDES)

NOTE:1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-52. ALL DIMENSIONS ARE IN MILLIMETERS3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT4. EXPOSED PAD SHALL BE SOLDER PLATED5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE

PIN 1 TOP MARK(SEE NOTE 5)

0.40 ± 0.10

6463

12

BOTTOM VIEW—EXPOSED PAD

7.15 ± 0.10

7.15 ± 0.10

7.50 REF(4-SIDES)

0.75 ± 0.05R = 0.10

TYP

R = 0.115TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UP64) QFN 0406 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

7.50 REF(4 SIDES)

7.15 ±0.05

7.15 ±0.05

8.10 ±0.05 9.50 ±0.05

0.25 ±0.050.50 BSC

PACKAGE OUTLINE

PIN 1CHAMFER

C = 0.35

LTC2216/LTC2215

3622165f

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008

LT 0208 • PRINTED IN USA

RELATED PARTSPART NUMBER DESCRIPTION COMMENTS

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LTC2217 16-Bit, 105Msps ADC Low Noise 1190mW, 81.2dB SNR, 100dB SFDR

LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package

LTC2220-1 12-Bit, 185Msps ADC 910mW, 67.5dB SNR, 9mm × 9mm QFN Package

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LTC2299 Dual 14-Bit, 80Msps ADC 445mW, 73dB SNR, 9mm × 9mm QFN Package

LT5522 400MHz to 2.7GHz High Linearity Downconverting Mixer

4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports

LT5527 400MHz to 3.7GHz High Linearity Downconverting Mixer

High IIP3: 23.5dBm at 1.9GHz, Conversion Gain: 2.3dB at 1.9GHz, NF = 12.5dB

LT5557 400MHz to 3.7GHz High Signal Level Downconverting Mixer

High IIP3: 23.5dBm at 3.5GHz, Conversion Gain: 1.7dB at 3.5GHz

ltc2216/ltc2215 - 16-bit, 80msps/65msps low noise adc ......ltc2216/ltc2215 1 22165f typical...

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