ece243 2013-final-solutionsexams.skule.ca/exams/ece243h1_20131_631429809824ece243... · 2018. 2....

Student # (use if pages get separated) ____________________________

ECE243 Computer Organization Pg 1 of 13 Spring 2013

UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING

FINAL EXAMINATION, APRIL 2013

Second Year

ECE243H1 S – COMPUTER ORGANIZATION Exam Type: D

Examiner – P. Anderson, N. Enright Jerger, and A. Moshovos

Instructions

This is a type D exam. You are allowed to use any printed/hand-written material including your course notes. You may use a University approved calculator.

Last Name (Print Clearly): _ ______________________________

First Name: _____________________________________________ Student Number: ___________________ ___________________________________________________________________________________________________

Question 1 20

Question 2 10

Question 3 20

Question 4 25

Question 5 10

Question 6 20

Question 7 25

Total 130

General Instructions: State your assumptions. Show your work. Comment your code. Solutions that are judged significantly inefficient will lose some marks. The exam is printed on two sides of the page. The last pages and the back of this one are blank and can be used for answers or calculations. Make your answers clear.

There are 7 questions and a total of 130 marks. There are 8 pieces of paper in the exam, this one included, printed both sides. The page numbering is 1-16.

SOLUTIONS



Question 1 – Basic Assembly [20 Marks] Assuming that initially all registers contain zero, show using eight hexadecimal digits the final value for each register after executing all the instructions of the following program. Do so for little-endian. The final value for r16 is given. “foo” is a function that abides by the NIOS II calling conventions and is properly behaved. The code is placed starting from address 0x00001000, that is main = 0x00001000. If you cannot determine the value of a register write UNKNOWN and explain why. .data xyz: .word bobos, 0x2, 0x3, 0x4 bobos: .byte 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70

.text

.global main main:

movia r16, xyz ldw r17, 0(r16) ldw r18, 0(r17)

addi r19, r0, 0x123F addi r20, r0, -2 and r21, r20, r19 or r22, r20, r19 addi r10, r0, 10 call foo movia r8, bobos beq r8, r17, dodo

koko: srli r9, r16, 8 br done dodo: slli r9, r16, 4 done: r16 = 0x0fab 1000

r21 = 0x0000 123e

r17 = 0x0fab 1010

r22 = 0xffff ffff

r18 = 0x4030 2010

r8 = 0x0fab 1010

r19 = 0x0000 123f

r9 = 0xfab1 0000

r20 = 0xffff fffe

R31 = 0x0000 1028

r10 = 0x0000 0000a



Question 2. [10 Marks] Instruction Encoding Consider the following hypothetical instruction encodings for an 8-bit CPU design. (Note these are not the same encoding as given in the lectures.)

a) What problems arise from this encoding?

Correctness: Certain values of R1, R2 or Imm4 will mimic op codes of other instructions. If someone does not state this but mentiones performance as an issue - decoding is more challenging since instruction word layout is not fixed.

b) Which encodings would you change? Justify your answer.

Swap bits[7-4] with bits[3-0] for add and sub (or for load, store, and bz) so all op-codes are in bits[3-0] (or in bits[7-4]).

Instruction Encoding – Bits 7-0

Instruction 7 6 5 4 3 2 1 0

Load R1 (R2) R1 R2 0 0 0 0

Store R1 (R2) R2 R1 0 0 1 0

Add R1 R2 1 0 0 0 R1 R2

Sub R1 R2 0 1 1 0 R1 R2

BZ Imm4 Imm4 0 1 0 1



Question 3 -- Caches [20 Marks] a) [6 Marks] A 16MByte, write-through, 16-way set-associative cache has 256-byte blocks. Show how this cache will be indexed assuming a 4GB byte-addressable address space (same as in NIOS II). How many bits will be used for offset, set, and tag given a 32-bit address: TAG SET OFF bits = 12 12 8 b) [4 Marks] In a 64KByte, 2-way set-associative cache with 64-byte blocks, set 0x123 contains tag 0x13456. Which memory block is currently cached there? Provide the range of addresses for this block. You may want to write the set and tag values in binary before you calculate the block addresses. Block starts at address = 0x9a2b48c0 (in hexadecimal please) Block ends at address = 0x9a2b48ff (in hexadecimal please) c) [4 Marks] In a 4Kbyte direct-mapped cache with 16byte blocks which set number counting from 0 will address 0xfabece12 be cached in? Set = 1110 0001 (in binary please) What will be its tag? Tag = 1111 1010 1011 1110 1100 (in binary please) d) [6 Marks] A 128KB write-back cache is 4-way set-associative with 128Bytes per block, uses LRU replacement. Calculate how many bits are needed for the various parts of the whole cache: DATA bits = 220 TAG bits = 17 * 210 Valid bits = 210 Replacement Bits = 28*ceil[lg(4!)] = 1280, or 28*4*ceil[lg(4)] = 2048 Dirty Bits = 210 Other bits = 0 (or blank)



Question 4. [25 Marks] Processor Implementation You are the CEO and CTO of PETOOMBA, an automatic pet grooming device manufacturer. The brains of your flagship grooming device uses the 8-bit processor we described in lectures. The datapath is given on the next page. The application developers have offered to get you a case of your favorite gummy bears if you implement an additional instruction that performs a multiply accumulate. Without it, the developers cannot produce the smooth motion that is worthy of PETOOMBA’s reputation.

The new instruction takes the format of:

MAC R1 Imm2

Which implements K1 = K1 + R1 * 2Imm2 where Imm2 is an unsigned value. The functionality is as follows:

1. K1 = K1 + (R1



b) [5 Marks] Modify datapath to implement the new instruction

- add a Zero extended Imm2 input to the ALU2 mux SolutionA: - add an input to the ALU2 mux connected to the output of the ALUout register SolutionB: - add an R2Sel mux to do the same thing as the R1Sel mux - add an input to the ALU1 mux connected to the output of the ALUout register



An extra copy of the datapath is provided for your convenience. Put an “X” through the datapath you do not wish to have marked



Question 5. [10 Marks] What actions take place in the datapath given on the previous page (same as the one in the lectures) when the control signals take the following values?

Note: ALUop for Add is 000 and for Shift is 100

PCWrite

AddrSel

Mem

Read

Mem

Write

IRload

MDR

load

R1Sel

RFWrite

R1R2

load

RegIn

ALU1

ALUop

FlagWrite

ALU2

AluO

utLoad

1

0 1 0 0

1 1

1 0 1 0 000 1 000 1

PC = PC + R2 RF[1] = ALUout MDR = MEM[R2] ALUout = PC + R2, and set N and Z flags



Question 6. [20 Marks] Building Memories

A) [6 Marks] How many 512 x 4-bit memory chips would be needed to build:

i) A 2KByte memory? 8

ii) A 32KByte memory? 128

iii) A 4K x 12 bit memory? 24

B) [14 Marks] Draw the design for a 2K x 8 bit memory built using 512 x 4 bit memory chips.

8 chips

2x4 or 4x2 organization

Connections (512 x 4 bit memory chip port names prefixed with „i“):

- iA8-iA0 = A8-A0 - iR/!iW = R/!W - one row: iD3-iD0=D3-D0,

the other row: iD3-iD0=D7-D4 - one column: !iCS = !CS or !A10 or !A9,

other column: !iCS = !CS or !A10 or A9, other column: !iCS = !CS or A10 or !A9, other column: !iCS = !CS or A10 or A9,

A10-A0

D7-D0

!CS

R/!W

D3-D0 R/!W

!CS

A8-A0

D3-D0 R/!W

!CS

A8-A0

D3-D0 R/!W

!CS

A8-A0

D3-D0 R/!W

!CS

A8-A0

D3-D0 R/!W

!CS

A8-A0

D3-D0 R/!W

!CS

A8-A0

D3-D0 R/!W

!CS

A8-A0

D3-D0 R/!W

!CS

A8-A0



Question 7. [30 Marks] I/O Devices Joe De Ziner decides to build a plant health sensing device. The ground-stick-like device contains several sensors including one for ground humidity, acidity, and temperature among others. The brains of the device is a NIOS II computer. Joe decides to use the ADC123 chip to convert incoming analog levels to digital. The chip has multiple analog inputs (called channels) and converts the values to a 12-bit digital number. Only one channel can be converted at a time. The device has the following two registers, selectable using the RS input on the chip. RS0=0 Control and Status (CSR) Register (read/write capable)

unused (may read as zero or one) IE Done Go Channel Select (0-‐7) b15-‐b6 b5 b4 b3 b2 b1 b0

RS1=1 Data Register (read only)

reserved, contain arbitrary value

Converted data

b15-‐b12 b11-‐b0 To use the device, the channel is selected and the “Go” bit is set to a 1. This can be done at the same time. This will cause the “Done” bit to go to zero. When the conversion is finished (it takes time to convert the input analog signal to digital) the “Done” bit will be set to 1. When this happens, the finished converted value will be in the Data register. Reading this will set the “Done” bit to zero. The interrupt for the device is enabled by setting the IE bit to 1. When IE is 1 the IRQ output of the chip will be high when Done is 1, low when Done is 0. The chip is to be attached to the NIOSII using interrupt IRQ12 and mapped at base memory address 0x0A000000 a) Circuits [15 Marks]

i. On the next page, help Joe by drawing the circuitry to attach the device, shown on top, to the NIOS II bus below. Connect all the pins at the bottom of the chip. CE is chip enable – the data lines are at high impedance when CE is 0, otherwise they depend on RS and R/!W. ANIN0-ANIN7 are the analog inputs and don’t need to be connected. Indicate which IRQ line of the NIOSII bus you are using.

ii. With your circuit, what part of the NIOSII address range is used by the

device? Answer: 0x0A000000 to 0x0A000007 (multiple options, see below)



Connections (device port names prefixed with „d“):

- dIRQ = IRQ12

- dR/!dW = R/W!

There are many ways how to map this chip. Below is one possible solution which maps CSR to word at 0x0A000000 (leaving 2 MSB unused) and DATA register to word at 0x0A000004 (again leaving 2 MSB unused).

- dRS = A2

(status register=0x0A000000-0x0A000003, data register =0x0A000004-0x0A000007)

- dD0-dD15 connected to Din0-Din15

- dD0-dD15 also drives a tri state buffer enabled by R/!W on to Dout0-Dout15

- CE = ME & BE0 & BE1 & (A31-A3 == 0x01400000) (support only halfword and word accesses)

D0-D15 CE RS R/!W

AnIN0 … AnIN7 ß analog sensors connect here

IRQ __

IRQ



b) Software [10 marks] Joe also needs help with the software:

i. [10 Marks] Write the interrupt handler for this device in NIOS II assembly language that reads data for a single channel and initiates conversion for the next channel, as shown in the pseudo-code below. unsigned short ADCv[6]; unsigned int ADCch;

interrupt handler: ADCv[ADCch] = bits 11-0 of ADC123’s Data Register; ADCch += 1; if (ADCch > 5) ADCch = 0; initiate conversion for channel “ADCch”;

As shown above, the data for each channel (0-5) should be saved in an array of words ADCv. Channels 6 and 7 are not used. The interrupt handler should save the data for the current channel (determined by ADCch) into the corresponding entry of the array (ADCv[ADCch]), and initiate conversion for the next channel (ADCch+1).

On the next page implement a complete interrupt handler in NIOS II assembly. The pseudo-code is repeated there as well. Make sure to write all sections including the “.data” and the one for interrupts.



.data ADCv: .skip 12 ADCch:.word 0

.section .exceptions “ax” ISR: # check done bit of the CSR movia et, 0x0A000000 ldwio et, 0(et) andi et, et, 0x10 beq et, et, exitISR

# save regs addi sp, sp, -8 stw r2, 0(sp) stw r3, 4(sp)

# get converted data in et movia et, 0x0A000004 ldwio et, 0(et) andi et, et, 0xfff

# ADCv[ADCch] = converted data movia r2, ADCv # (&ADCch= &ADCv[0] + 12) ldw r3, 12(r2) # r3 = ADCch add r2, r2, r3 add r2, r2, r3 # r2 = &ADCv[ADCch] stw et, 0(r2) # ADCv[ADCch] = converted data

#increment or reset ADCch addi r3, r3, 1 # ADCch++ movi et, 5 ble r3, et,storeADCch # if (ADCch

ece243 2013-final-solutionsexams.skule.ca/exams/ece243h1_20131_631429809824ece243... · 2018. 2....

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