editorial advanced vlsi architecture design for emerging...

EditorialAdvanced VLSI Architecture Design for EmergingDigital Systems

Yu-Cheng Fan,1 Qiaoyan Yu,2 Thomas Schumann,3 Ying-Ren Chien,4 and Chih-Cheng Lu5

1Department of Electronic Engineering, National Taipei University of Technology, Taipei 10608, Taiwan2Department of Electrical and Computer Engineering, University of New Hampshire, Durham, NH 03824, USA3Department of Electrical Engineering and Information Technology, Hochschule Darmstadt-University of Applied Sciences,Birkenweg 8, 64295 Darmstadt, Germany4Department of Electrical Engineering, National Ilan University, Yilan 260, Taiwan5Division for Biomedical & Industrial IC Technology, Industrial Technology Research Institute, Hsinchu 310, Taiwan

Correspondence should be addressed to Yu-Cheng Fan; [email protected]

Received 29 September 2014; Accepted 29 September 2014; Published 22 December 2014

Copyright © 2014 Yu-Cheng Fan et al. This is an open access article distributed under the Creative Commons Attribution License,which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

With physical feature sizes in VLSI designs decreasing rap-idly, existing efficient architecture designs need be reex-amined. Advanced VLSI architecture designs are requiredto further reduce power consumption, compress chip area,and speed up operating frequency for high performanceintegrated circuits. With time-to-market pressure and ris-ing mask costs in the semiconductor industry, engineeringchange order (ECO) design methodology plays a main rolein advanced chip design. Digital systems such as commu-nication and multimedia applications demand for advancedVLSI architecture design methodologies so that low powerconsumption, small area overhead, high speed, and low costcan be achieved.

This special issue is dedicated to aspects of VLSI archi-tecture design and their applications. Special interest focuseson emerging digital systems. This special issue contains eightpapers that focus on the power minimization design, effi-cient hardware Trojan detection, low-areaWallace multiplier,gate-level circuit reliability analysis, low power and highspeed arithmetic circuits, power effective fractional-N-PLLfrequency synthesizer, power-saving architecture for networkon chip, and ECO design.

In the paper entitled “On-chip power minimization usingserialization-widening with frequent value encoding,” theauthors address the problem of the high-power consumptionof the on-chip data buses by exploring a new framework for

memory data bus. In particular, serialization-widening (SW)of data buswith frequent value encoding (FVE) is proposed tominimize the power consumption of the on-chip cache databus.

In the paper entitled “Efficient hardware trojan detectionwith differential cascade voltage switch logic,” the authorspresent to exploit the inherent feature of differential cascadevoltage switch logic (DCVSL) to detect hardware trojans(HTs) at runtime. By examining special power characteristicsof DCVSL systems uponHT insertion, the authors can detectHTs, even if the HT size is small. Simulation results show thatthe method achieves up to 100% HT detection rate. The eval-uation on ISCAS benchmark circuits shows that the schemeobtains a HT detection rate in the range of 66% to 98%.

In the paper entitled “Low-Area Wallace multiplier,” theauthors propose a reduced-area Wallace multiplier withoutcompromising on the speed of the originalWallacemultiplier.The proposed designs are synthesized using Synopsys DesignCompiler in 90 nmprocess technology and achieve the lowestarea cost as compared to other tree-based multipliers. Thespeed of the proposed and reference multipliers is almost thesame.

In the paper entitled “Gate-level circuit reliability analysis:a survey,” the authors provide an overview of some typicalmethods for reliability analysis with special focus on gate-level circuits that are either large or small, with or without

Hindawi Publishing CorporationVLSI DesignVolume 2014, Article ID 746132, 2 pageshttp://dx.doi.org/10.1155/2014/746132

2 VLSI Design

reconvergent fan-outs. It is intended to help the readers gainan insight into the reliability issues and their complexityas well as optional solutions. Understanding the reliabilityanalysis is also a first step towards advanced circuit designsfor improved reliability in the future research.

In the paper entitled “Performance analysis of modifieddrain gating techniques for low power and high speed arithmeticcircuits,” the authors present several high performance andlow power techniques for CMOS circuits. In these designmethodologies, drain gating technique and its variations aremodified by adding an additional NMOS sleep transistor atthe output node. This method helps to achieve faster dis-charge and thereby provides higher speed. Intensive simu-lations are performed using Cadence Virtuoso in a 45 nmstandardCMOS technology at room temperature with supplyvoltage of 1.2 V. Comparative analysis of the present circuitswith standard CMOS circuits shows smaller propagationdelay and lesser power consumption.

In the paper entitled “Optimization of fractional-N-PLLfrequency synthesizer for power effective design,” the authorsdesign a low power fractional-N phase-locked loop (FNPLL)frequency synthesizer for industrial application, which isbased on VLSI. The design of FNPLL has been optimizedusing different VLSI techniques to acquire significant perfor-mance in terms of speed with relatively less power consump-tion.

In the paper entitled “Design of smart power-saving archi-tecture for network on chip,” the authors present a novel archi-tecture, namely, smart power-saving (SPS), for low powerconsumption and low area in virtual channels of NoC. Com-paring with related works, the new proposedmethod reduceswith 37.31%, 45.79%, and 19.26% on power consumption andreduces with 49.4%, 25.5%, and 14.4% on area, respectively.

Finally, in the paper entitled “Engineering change ordersdesign using multiple variables linear programming for VLSIdesign,” the authors present an engineering change orders(ECO) design usingmultiple variable linear programming forVLSI design. The authors adopt linear programming tech-nique to plan and balance the spare cells and target cells tomeet the new specification according to logic transformation.The proposed method solves the related problem of resourcefor ECOproblems and provides a hardware-efficient solution.

Acknowledgments

Finally, the Guest Editors would like to thank all the authorswho sent their valuable contributions and all the reviewers fortheir valuable comments.

Yu-Cheng FanQiaoyan Yu

Thomas SchumannYing-Ren ChienChih-Cheng Lu

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