ee 247b/me 218: introduction to mems design ctn 4/22/21

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EE 247B/ME 218: Introduction to MEMS DesignLecture 25m2: Sensing Circuit Non-Idealities & Integration

CTN 4/22/21

Copyright © 2021 Regents of the University of California

EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 8

Non-Ideal Operational Amplifiers


Integrator-Based Diff. Position Sensing

+VP

-VP

io

Cp 0v-

+

CF

R2

(for biasing)2

2

1

sCR


Actual Op Amps Are Not Ideal

• Actual op amps, of course, are not ideal; rather, they …Generate noiseHave finite gain, Ao

Have finite bandwidth, wbHave finite input resistance, Ri

Have finite input capacitance, Ci

Have finite output resistance, Ro

Have an offset voltage VOS between their (+) and (-) terminals

Have input bias currentsHave an offset IOS between the bias currents into the

(+) and (-) terminalsHave finite slew rateHave finite output swing (governed by the supply voltage

used, -L to +L)

• And what’s worse: All of the above can be temperature (or otherwise environmentally) dependent!


Finite Op Amp Gain and Bandwidth

A

b

s

AsA

1

0

jA 0log 20 A

b T

This pole actually designed in for some op amps.

Open-loop response of the amplifier.

• For an ideal op amp:

• In reality, the gain is given by:

• For w>>wb:

Unity gain frequency:

3 dB frequency

ss

A

s

AsA Tb

b

00)(

Integrator w/ time const. 1/wT

bT A 0

20dB/dec

Finite Gain

Finite Bandwidth

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Op Amp Non-Idealities

Input resistance Ri and Output Resistance R0:

With finite Ri and R0, and finite gain and BW, the op amp equivalent circuit becomes:

Op Amp Non-Idealities Ri & R0

0v

v-

(+)v

iR0R

vvAv

0C+-

⇒ Basically reduces down to a voltage-amplifier model

⇒ Add an output C0 to model a single pole response, where

00

1

CRwb


Input Offset Voltage V0S

Input Offset Voltage, V0S:

vvAv0

+

-

)out! railsit :or (usually, 0 00 LLvv

00 vIdeal case:

Reality:

Why? Internal mismatches within the op amp cause a dc offset.Model this with an equivalent input offset voltage V0S.

0v+

-

+-

SV0

Typically, V0S = 1mV – 5mV


Effect of V0S on Op Amp Circuits

Example: Non-Inverting Amplifier

mVVmVVR

RS 505 ,9 e.g., 00

1

2

1

200 1

R

RVV S

2R

1R

+

-

+-SV0

(not so bad …)


Effect of V0S on Op Amp Circuits (cont.)

fRTo fix this, place a resistor in shunt with the C then:

R

RVv

f

S 100

Example: Integrator

0v

t

Will continue to increase until op amp saturates

dtiC

Vvt

S 0 100

1

00

0

00

1

1

tCS

tS

S

vRC

tV

dtR

V

CV

R

+

-

+-

SV0

SV0

- +Cv

C

1i

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Integrator-Based Diff. Position Sensing

+VP

-VP

io

Cp 0v-

+

CF

R2

(for biasing)2

2

1

sCR


Buffer-Bootstrapped Position Sensing

• Bootstrap the ground lines around the interconnect and bond padsNo voltage across Cp

It’s effectively not there!

+VP

-VP

+

-0v

Unity Gain Buffer

Cp

Includes capacitance from interconnects, bond pads, and Cgs of the op amp

Cgd

0v

0v

Cgd = gate-to-drain capacitance of the input MOS transistor

1×

InterconnectGround Plane


Effect of Finite Op Amp Gain

+VP

-VP

+

-0v

Unity Gain Buffer

CpCgd

Total ADXL-50 Sense C ~ 100fF


Integration of MEMS and Transistors

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Integrate or Not?

• Benefits:Lower parasitic capacitance and resistance improved

sensitivity and resolution, higher operation frequencyBetter reliabilityReduced size lower cost? Reduced packaging complexity integration is a form of

packaging lower cost?Higher integration density supports greater functionality

• Challenges:Temperature ceilings imposed by the transistors or MEMSProtecting one process from the otherSurface topography of MEMSMaterial incompatibilitiesMultiplication of yield losses (versus non-integrated)Acceptance by transistor foundries


250 nm CMOS Cross-Section

P

P Well - NMOS SubstrateN Well - PMOS Substrate

PNP+ P+ N+ N+

S G D S G D

G

D

S S

D

GSub Sub

Silicon Substrate

2nd Level Metal Interconnect (e.g., Cu)

1st Level Metal Interconnect (e.g., Al)

CVD Tungsten

TiN Local Interconnect

LPCVD SiO2

Lightly Doped Drain (LDD)

LOCOS Oxidation

TiSi2 Contact Barrier

Polysilicon Gate

28 masks and a lot more 28 masks and a lot more complicated than MEMS!


•Mixed:

problem: multiple passivation/protection steps large number of masks required

problem: custom process for each product

•MEMS-first or MEMS-last:

adv.: modularity flexibility less development time

adv.: low pass./protection complexity fewer masks

Merged MEMS/Transistor Technologies (Process Philosophy)

MEMS-Last:

MEMS-First:


Analog Devices BiMEMS Process

• Interleaved MEMS and 4 mm BiMOS processes (28 masks)

• Diffused n+ runners used to interconnect MEMS & CMOS

• Relatively deep junctions allow for MEMS poly stress anneal

• Used to manufacture the ADXL-50 accelerometer and Analog Devices family of accelerometers

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Analog Devices BiMEMS Process (cont)

• Examples:

Analog Devices ADXL 78

• Can you list the advances in the process from old to new?

Old New

Analog Devices ADXL-202 Multi-Axis Accelerometer


•Mixed:








•Modular technology minimizes product updating effortModule 1: micromachining process (planar technology)Module 2: transistor process (planar IC technology)

• Adv.: (ideally) no changes needed to the transistor process

• Adv.: high temperature ceiling for some MEMS materials

• Challenges:Reducing topography after MEMS processing so

transistors can be processedMaximizing the set of permissible MEMS materials; the

materials must be able to withstand transistor processing temperatures

Getting transistor foundries to accept pre-processed wafers

MEMS-First Integration


• Problem: mstructural topography interferes with lithographydifficult to apply photoresist for submicron circuits

• Soln.: build mmechanics in a trench, then planarize before circuit processing [Smith et al, IEDM’95]

MEMS-First Integration

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• Used to demonstrate functional fully integrated oscillators

• Issues: lithography and etching may be difficult in trench may

limit dimensions (not good for RF MEMS)mmechanical material must stand up to IC temperatures

(>1000oC) problem for some metal materialsmight be contamination issues for foundry IC’s

[Smith et al, IEDM’95]

MEMS-First Ex: Sandia’s iMEMS


Bosch/Stanford MEMS-First Process

• Single-crystal silicon microstructures sealed under epi-poly encapsulation covers

•Many masking steps needed, but very stable structures

Resonator Epi-Poly Cap

Substrate

ContactEpi-Poly Seal

mMechanical Device

Transistor Circuits

Vacuum Chamber

[Kim, Kenny Trans’05]

Epi-silicon for CMOS


Problems With MEMS-First

•Many masking steps needed, plus CMP required cost can grow if you’re not careful

• Processes using trenches sacrifice lithographic resolution in microstructures

•MEMS must withstand transistor processing temperaturesPrecludes the use of structural materials with low

temperature req’mts: metals, polymers, etc.

• Exotic MEMS (e.g., ZnO) that can contaminate transistors during their processing are not permissible thus, not truly modular

• Foundry acceptance not guaranteed and might be rare


Foundry Acceptance of MEMS-First?

• Is a CMP’ed silicon surface sufficiently pure for fabrication of aggressively scaled transistors? How about if an oxide is grown over the CMP’ed surface and removed via a wet etch to yield a “pristine” surface?

• Is epi silicon grown as part of a sealing process sufficiently pure for fabrication of aggressively scaled transistors?

• CMOS is many times more difficult to run than MEMSFeature sizes on the nm scale for billions of devicesContamination a big issue: many foundries may not accept

pre-processed wafers for contamination reasonsMany foundries will not accept any pre-processed wafers,

MEMS or not just can’t guarantee working transistor circuits with unknowns in starting silicon

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•Mixed:








•Modular technology minimizes product updating effortModule 1: transistor process (planar IC technology)Module 2: micromachining process (planar technology)

• Adv.: foundry friendlyVirtually any foundry can be used can use the

lowest cost transistor circuits (big advantage)

• Adv.: topography after circuit fabrication is quite small, especially given the use of CMP to planarize the metallization layers

• Issue: limited thermal budget limits the set of usable structural materialsMetallization goes bad if temperature gets too highAluminum grows hillocks and spikes junctions if T>500oCCopper diffusion can be an issue at high temperatureLow-k dielectrics used around metals may soon lower

the temperature ceiling to only 320oC

MEMS-Last Integration


Berkeley Polysilicon MICS Process

• Uses surface-micromachined polysilicon microstructures with silicon nitride layer between transistors & MEMSPolysilicon dep. T~600oC; nitride dep. T~835oC1100oC RTA stress anneal for 1 min.metal and junctions must withstand temperatures ~835oC tungsten metallization used with TiSi2 contact barriers in situ doped structural polySi; rapid thermal annealing

EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 35• Fabrication steps compatible with planar IC processing

Surface Micromachining

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• Completely monolithic, low phase noise, high-Q oscillator (effectively, an integrated crystal oscillator)

• To allow the use of >600oC processing temperatures, tungsten (instead of aluminum) is used for metallization

OscilloscopeOutput

Waveform

Single-Chip Ckt/MEMS Integration

[Nguyen, Howe 1993][Nguyen, Howe 1993]


• Problem: tungsten is not an accepted primary interconnect metal

• Challenge: retain conventional metallizationminimize post-CMOS processing temperaturesexplore alternative structural materials (e.g., plated

nickel, SiGe [Franke, Howe et al, MEMS’99])Limited set of usable structural materials not the

best situation, but workable

Usable MEMS-Last Integration


Poly-SiGe MICS Process

•MICS = “Modular Integration of Circuits and Structures”

•MEMS-last process, where SiGe micromechanics are planar processed directly above conventional foundry circuitsenabled by lower deposition temperature of SiGe ~450oCAdv.: alleviates contamination issues of pre-circuit

processes, allowing a wider choice of IC technologies

[Franke, Howe 2001]

Shielded vertical signal path to gate of input transistor5-Level Metal

Foundry CMOS

Poly-SiGe MEMS

Shielded Interconnect to drive electrode


Polysilicon Germanium

• DepositionLPCVD thermal decomposition

of GeH4 and SiH4 or Si2H6

Rate >50 Å/min, T < 475°C, P = 300-600 mT

At higher [Ge]: rate ↑, T ↓In-situ doping, ion

implantation

• Dry EtchingSimilar to poly-Si, use F, Cl,

and Br- containing plasmasRate ~0.4 mm/min

•Wet EtchingH2O2 @ 90oC: can get 4

orders of magnitude selectivity between >80% and <60% Ge content

Good release etchant

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Poly-SiGe Mechanical Properties

• Conformal deposition

• Low as-deposited stress (when its done right)

• Young’s modulus ~ 146 GPa (for poly-Si0.35Ge0.65)

• Density ~4280 kg/m3

• Acoustic velocity ~5840 m/s (25% lower than polysilicon)Harder to achieve high

frequency devices

• Fracture strain 1.7% (compared to 1.5% for MUMPS polySi)

•Q=30,000 for n-type poly-Ge in vacuum


UCB Poly-SiGe MICS Process

• 2 mm standard CMOS process w/ Al metallization

• P-type poly-Si0.35Ge0.65 structural material; poly-Ge sacrificial material

• Process:Passivate CMOS w/ LTO @ 400oCOpen vias to interconnect runnersDeposit & pattern ground planeRTA anneal to lower resistivity (550oC, 30s)

Transistor Circuits


ASIMPS Ckt/MEMS Integration Process

•MEMS constructed from metal/insulator laminates of foundry CMOS

• Top metal layer used as etch mask for CHF3/O2

oxide etch

• Structures released via a final SF6 isotropic dry etch

• Independent electrostatic actuation possible due to multiple insulated metal layers

• Stress issues can be trickyMust design defensively

against warping

[G. Fedder, CMU]

Metal/insulator stack


ASIMPS Ckt/MEMS Integration Process

• Direct integration of Al/oxide MEMS structure with silicon CMOS or SiGe BiCMOS circuits

•Multiple electrodes within structures

• Derivatives for bulk silicon structures

Etched Pit

CompositeBeam

StatorElectrodes

CMOSTransistor

Silicon Substrate

[G. Fedder, CMU]

GyroResonator

Uncooled IR Detector Element

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Effect of Finite Op Amp Gain

+VP

-VP

+

-0v

Unity Gain Buffer

CpCgd

Total ADXL-50 Sense C ~ 100fF

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ee 247b/me 218: introduction to mems design ctn 4/22/21

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