eecs 141 – s02 advanced logic...
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Digital Integrated Circuits © J. Rabaey 2000Logic
EECS 141 – S02Advanced Logic Styles
Digital Integrated Circuits © J. Rabaey 2000Logic
Previous Lecture
l Optimization of CMOS Logic Gatesl 5 Design Techniques
» Transistor sizing» Transistor ordering» Logic transformations» Buffer insertion» Swing reduction
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Today’s Lecture
l Transistor sizing in complex logic gatesl Alternative static logic families
Digital Integrated Circuits © J. Rabaey 2000Logic
Midterm 1
l Total: 30l Mean: 18.9l Median: 19.5l Stdev: 5.8l Max: 28.5
Good job!
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Sizing Logic Paths for Speed
l Frequently, input capacitance of a logic path is constrained
l Logic has to drive some capacitancel Example: ALU load in Intel’s microprocessors
is 0.5pFl How do we size the ALU datapath to achieve
maximum speed?l We have already solved this for the inverter
chain – can we generalize it for any type of logic?
Digital Integrated Circuits © J. Rabaey 2000Logic
Buffer Example
∑=
+=
N
i
ip
ftDelay
10 1
γ
Minimum delay is when fi ’s are equal(each stage bears the same effort)
CL
In Out
1 2 N
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Digital Integrated Circuits © J. Rabaey 2000Logic
Optimum Effort per Stage
Ff N =ˆWhen each stage bears the same effort:
N Ff =ˆ
NNFftpD N
+=
+= ∑ γγ
/1
10
ˆMinimum path delay
Digital Integrated Circuits © J. Rabaey 2000Logic
Delay in a Logic Gate
)(0 γgf
ptDelay p +=
p = Electrical effort: ratio of intrinsic delay of complex gateand inverter (function of gate topology and layout)
g = Logical effort: How much worse is a complex gate atproducing output current (compared to an inverter)
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Electrical Effort
Estimates of intrinsic delay factors of various logic types assuming simple layout styles, and a fixed PMOS/NMOS ratio.
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Logical EffortLogical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current
g = 1 g = 4/3 g = 5/3
B
A
A BF
VDDVDD
A B
A
B
F
VDD
A
A
F
1
2 2 2
2
21 1
4
4
Inverter 2-input NAND 2-input NOR
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Logical Effort of Gates
Logic efforts of common logic gates, assuming a PMOS/NMOS ratio of 2.
Digital Integrated Circuits © J. Rabaey 2000Logic
Logical Effort of Gates
1 2 3 4 5Fanout f
1
2
3
4
5
IntrinsicDelay
EffortDelayInv
erte r: g
=1; p =1
2-inp
u t NAN
D: g=4
/3; p=
2
Nor
mal
ized
Dela
y
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Delay Through Combinational Block
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Example: Optimize Path
H = 40/9G = 20/9F = 2f =x =y =
From David Harris
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Alternative Logic Styles
l Static CMOS is robust and reliablel But
» Large (2N transistors)» Slow (large capacitance)
l Hence … A quest for alternative logic styles that are smaller, faster, or lower-power.
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Ratioed Logic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
FVSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
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Digital Integrated Circuits © J. Rabaey 2000Logic
Ratioed Logic
VD D
VSS
PDN
In1
In2
In3
F
RLLoadResistive
N transistors + Load
• VOH = VDD
• VOL = RPN
RPN + RL
• Assymetrical response
• Static power consumption
•
• tpL= 0.69 RLCL
Digital Integrated Circuits © J. Rabaey 2000Logic
Active Loads
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
DepletionLoad
PMOSLoad
depletion load NMOS pseudo-NMOS
VT < 0
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Load Lines of Ratioed Gates
0.0 1.0 2.0 3.0 4.0 5.0Vout (V)
0
0.25
0.5
0.75
1
I L(N
orm
aliz
ed)
Resistive load
Pseudo-NMOS
Depletion load
Current source
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Pseudo-NMOS
VD D
A B C D
FCL
VOH = VDD (similar to complementary CMOS)
kn VDD VTn–( )VOLVOL
2
2-------------–
kp
2------ VDD VTp–( )
2=
VOL VDD VT–( ) 1 1kpkn------–– (assumingthatVT VTn VTp )= = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
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Digital Integrated Circuits © J. Rabaey 2000Logic
Pseudo-NMOS NAND Gate
VDD
GND
Digital Integrated Circuits © J. Rabaey 2000Logic
Improved Loads
A B C D
F
CL
M1M2 M1 >> M2Enable
VDD
Adaptive Load
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Improved Loads (2)
VDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
AABB
M1 M2
Dual Cascode Voltage Switch Logic (DCVSL)
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Example
B
A A
B B B
Out
Out
XOR-NXOR gate
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Pass-Transistor Logic
Inpu
ts Switch
Network
OutOut
A
B
B
B
• N transistors• No static consumption
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NMOS-only switch
A = 2.5 V
B
C = 2.5V
CL
A = 2.5 V
C = 2.5 V
BM2
M1
Mn
Threshold voltage loss causesstatic power consumption
VB does not pull up to 2.5V, but 2.5V -VTN
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(1) NMOS Only Logic: Level Restoring Transistor
M2
M1
Mn
Mr
OutA
B
VDDVDDLevel Restorer
X
• Advantage: Full Swing
• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
Digital Integrated Circuits © J. Rabaey 2000Logic
Level Restoring Transistor
(a) Output node (b) Intermediate node X
0 2 4 6t (nsec)
-1.0
1.0
3.0
5.0
Vou
t (V
)
0 2 4t (nsec)
-1.0
1.0
3.0
5.0
VX
with
without
VB
with
without
6
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Digital Integrated Circuits © J. Rabaey 2000Logic
Solution 2: Single Transistor Pass Gate with VT=0
Out
VDD
VDD
2.5V
VDD
0V 2.5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
Digital Integrated Circuits © J. Rabaey 2000Logic
Complimentary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=A⊕Β Ý
F=A⊕ ΒÝ
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-TransistorNetwork
Pass-TransistorNetwork
AABB
AABB
Inverse
(a)
(b)
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4 Input NAND in CPL
Digital Integrated Circuits © J. Rabaey 2000Logic
Solution 3: Transmission Gate
A B
C
C
A B
C
C
B
CL
C = 0 V
A = 2.5 V
C = 2.5 V
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Digital Integrated Circuits © J. Rabaey 2000Logic
Resistance of Transmission Gate
Vout
0 V
2.5 V
2.5 VRn
Rp
0.0 1.0 2.00
10
20
30
Vout, V
Res
ista
nce,
ohm
s
Rn
Rp
Rn || Rp
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Pass-Transistor Based Multiplexer
AM2
M1
B
S
S
S F
VDD
GND
VDD
In1 In2S S
S S
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Transmission Gate XOR
A
B
F
B
A
B
BM1
M2
M3/M4
Digital Integrated Circuits © J. Rabaey 2000Logic
Delay in Transmission Gate Networks
V1 Vi-1
C
2.5 2.5
0 0
Vi V i+1
CC
2.5
0
V n-1 V n
CC
2.5
0
In
V1 Vi V i+1
C
V n-1 V n
CC
In
ReqR eq Req Req
CC
(a)
(b)
C
R eq R eq
C C
R eq
C C
Req Req
C C
Req
C
In
m
(c)
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Digital Integrated Circuits © J. Rabaey 2000Logic
Delay Optimization
Digital Integrated Circuits © J. Rabaey 2000Logic
Transmission Gate Full Adder
A
B
P
Ci
VDD A
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup