electronic devices in mtl annual report 2009

8/2/2019 Electronic Devices in MTL Annual Report 2009

1/38

E e De e

Si Current-limiters based on Si Pillar Ungated FET or Field-emission Applications ...........................................................................DE.1Semiconductor and Insulator Engineering or the Improvement o Organic Thin-Film Transistors ..............................................DE.2High-per ormance Cold Cathodes or Sub-mm-wave Compact Sources ...............................................................................................DE.3Reproducible Lithographically Patterned Metal-oxide Transistors or Large-area Electronics ........................................................DE.4High-electron-mobility Germanium MOSFETs: The E ect o n-type Channel Implants and Ozone Sur ace Passivation ........DE.5Si/SiGe Tunneling Transistors ................................................................................................................................................................................DE.6Impact o Uniaxial Strain and Channel Orientation on Band-to-band Tunneling in Si/SiGe Heterostructures ..........................DE.7Nonvolatile Memory Devices with Nanoparticle/High-k Dielectric Tunnel-barrier Engineering ....................................................DE.8Exciplex Transistors ...................................................................................................................................................................................................DE.9Modeling o Deep-reactive Ion-etch Variation ................................................................................................................................................DE.10Modeling o Electrochemical-mechanical Polishing (ECMP) ......................................................................................................................DE.11Stability o Metal Oxide-based Field-e ect Transistors .................................................................................................................................DE.12

Electrical Reliability o GaN HEMTs on Si Substrates .....................................................................................................................................DE.13RF Power CMOS or Millimeter-wave Applications .........................................................................................................................................DE.14Quantum Capacitance in Scaled-Down III-V HEMTs ......................................................................................................................................DE.15RF Reliability o GaN High-electron-mobility Transistor ...............................................................................................................................DE.16Inverted-type InGaAs HEMTs or Logic Applications .....................................................................................................................................DE.17Impact o Strain on the Characteristics o InGaAs HEMTs ............................................................................................................................DE.18Advanced Substrate Engineering: Integration o InP Lattice Constant on Si ........................................................................................DE.19Characteristics o Selectively Grown Ge-on-Si Photodiodes.......................................................................................................................DE.20Scaled SiGe-channel p-MOSFETs on Insulator .................................................................................................................................................DE.21Uniaxial Strained-Si Gate-all-around Nanowire FETs .....................................................................................................................................DE.22A Superconductivity Switch Constructed in an EuS/Al/EuS Sandwich Structure .................................................................................DE.23Charge Transport Studies in Single-crystal Organic Field-e ect Transistors .........................................................................................DE.24

Silicon and Silicon-ermanium Magnetic-tunneling-emitter Bipolar Transistors...................................................................................DE.25AlGaN/GaN Nanowire HEMTs ................................................................................................................................................................................DE.26Seamless On-wa er Integration o GaN HEMTs and Si(100) MOSFETs ......................................................................................................DE.27AlGaN/GaN Vertical Power Transistors................................................................................................................................................................DE.28GaN Power Transistors Grown on Si Substrate.................................................................................................................................................DE.29Sel -aligned AlGaN/GaN HEMTs ............................................................................................................................................................................DE.30New Technologies or High- requency GaN Transistors ...............................................................................................................................DE.31Generalized Dri t-di usion or Thermoelectrics ..............................................................................................................................................DE.32Magnetic and Magnetoelectronic Memory and Logic ..................................................................................................................................DE.33Dual-threshold-voltage Organic Thin- lm Transistors or Mixed-signal Integrated Circuits ............................................................DE.34E ects o Bias Stress in Organic Thin- lm Transistors ....................................................................................................................................DE.35Materials Reliability in GaN-based Devices .......................................................................................................................................................DE.36E ects o Active Atomic Sinks and Reservoirs on the Reliability o Cu/low-k Interconnects ...........................................................DE.37


2/38DE.1 MICROSYSTEMS TECHNOLOGY LABORATORIES ANNUAL RESEARCH REPORT 2009 ElEctronic DEvicEs

ElEctronic DEvicEs

s cu e - m e ba ed s P a U ga ed FEt F e d-emApp aY. Niu, L. F. Velasquez-Garcia, A. I. AkinwandeSponsorship: DARPA

We used vertical silicon ungated eld-effect transistors(FETs) as current limiters to individually ballast eld-emitter arrays of density. The device structure, shown inFigure 1, consists of silicon or carbon nano ber (CNF)emission tips that are individually connected in series withhigh-aspect-ratio silicon pillars (1m x 1m x 100m).The device structure provides a simple solution tothree problems that have plagued eld emission arrays:emission current uniformity, emission current stability,and reliability.The ungated FETs are designed as high-aspect-ratiosilicon pillars to achieve velocity saturation of carriers

and obtain current source-like characteristics. The Sipillar ungated FETs are connected in series with eldemitter tips to limit current in each eld emitter in spiteof tip radii variation/distribution. To provide rigorouscharacterization of the ungated FET behavior, we made atest structure that exposed selected numbers of columns. Also to achieve optimal dynamic output resistanceof a current limiter, silicon pillar ungated FETs werefabricated on n-type substrates with 150-200 -cm, 20-40-cm and 4-6 -cm resistivity. Figure 2 is an example of current-voltage characteristics obtained on silicon pillarungated FETs fabricated on a 20-40 cm resistivity. Processand device simulations were also conducted to solidify ourexperimental results.

FIGURE 1: Device structure FEAsare ormed on top o Si columns(FETs). Each column holds oneemitter. The drain o the FET isconnected to the emitter o theFE, i.e., node oating. Voltage isdistributed between FEA and FET.

Normalized I-V: Medium Condu ctivity, Dice 6 (2,2) Size 1

0.0E+00

1.0E-07

2.0E-07

3.0E-07

4.0E-07

5.0E-07

6.0E-07

0 10 20 30 40 50 60 70 80 90 100

Voltage (V)

FIGURE 2: The FET characterization data showcurrent saturation is achieved. The columns have dopant

concentrations o 1x1015 cm-3,2x1014 cm-3, and 2x1013 cm-3.

REFERENCES

[1] L. F. Velasquez-Garc ia, B. Adeoti,Y. Niu, and A.I. Akinwande,Uni orm High Current FieldEmission o Electrons romSi and CNF FEAs Individuallycontrolled by Si Pillar UngatedFETs,IEEE IEDM,2007, pp.599-602.

[2] C. Canali, G. Majni, R. Minder,and G. Ottaviani, Electronand Hole Dri t VelocityMeasurements in Silicon andTheir Empirical Relation toElectric Field and Temperature,IEEE Trans.Electron Devices, vol. ED-22, pp. 1045-1047, 1975.

[3] B. T. Murphy, Uni ed Field-E ect Transistor TheoryIncluding Velocity Saturation,IEEE Journal of Solid-StateCircuits, Jun. 1980, pp. 325-327.

[4] J. Baek, M.S. Shur, K. W. Lee,and T. Vu, Current-VoltageCharacteristics o UngatedGaAs FETs,IEEE Transactions onElectron Devices, Nov. 1985, pp.2426-2430.

[5] H. J. Boll, J. E. Iwersen, and E.W. Perry, High-speed currentlimiter,IEEE Trans. ElectronDevices, vol. ED-13, pp. 904-907,Dec. 1966.

[6] H. Takemura, Y. Tomihari,N. Furutake, F. Matsuno, M.Yoshiki, N. Takada, A. Okamotoand Soichiro Miyano A NovelVertical Current LimiterFabricated with a Deep TrenchForming Technology or HighlyReliable Field Emitter Arrays,NEC Corporation.



ElEctronic DEvicEs

sem du a d i u a E g ee g he imp eme o ga th -F m t aM. A. Smith, A. I. AkinwandeSponsorship: GEM Ph.D. Engineering Fellowship, O ce o the Dean or Graduate Students

The potential uses for electronic solid state devicesare endless. As organic semiconductor-based devicescan easily be scaled to large areas and fabricated onmechanically compliant and non-planar surfaces atlow temperatures, they can lead to a more profoundrealization of the possibilities that solid state technologiesoffer [1].To realize organic semiconductor-based devices as apervasive complement to Si CMOS devices, the electricalperformance of organic semiconductor devices must be improved. In particular, the operating voltagemust reduce while the current and the on-current to

off-current ratio increase. The device of interest is apentacene-based organic thin- lm transistor (OTFT).Delocalized -bonded electrons enable semiconducting behavior in pentacene [1]. To make useful circuits, keydevice parameters such as threshold voltage, subthresholdslope, and on-current to off-current ratio have to bereproducible. Ultimately, these device parameters arerelated to pentacene thin- lm quality (grain size, growthmodes, and material phases), which affects carriermobility.

Conventional methods of device fabrication have beused to address performance issues with limited sucThis work will address these issues through insulatoand semiconductor engineering. Initial efforts willconcentrate on engineering the gate insulator by usia high dielectric constant material. Speci cally, BZN(Bi1.5Zn0.8+xNb1.3-xO7) is a paraelectric pyrochlore systethat boasts a high dielectric constant, low dielectricloss, and low co- ring temperature, making it a viabinsulator for improving OTFT performance andenabling advanced circuit design [2]. Later phases othis work will focus on engineering the semiconducdeposition. Enhancements to standard evaporativedeposition techniques will be explored by in situ coof new forms of energy to control pentacene thin- lmorphology and defects.

FIGURE 1: Pentacene OTFT topview micrograph

REFERENCES:

[1] M. Kitamura and Y. Arakawa,Pentacene-based organic

eld-e ect transistors, Journal of Physics-Condensed Matter, vol. 20, May 2008.

[2] Y. Choi, I. D. Kim, H. L. Tuller,and A. I. Akinwande, Low-voltage organic transistorsand depletion-load inverterswith high-K pyrochlore BZNgate dielectric on polymersubstrate, IEEE Transactionson Electron Devices, vol. 52, pp.2819-2824, Dec 2005.



ElEctronic DEvicEs

MAtEriAls

H gh-pe ma e c d ca h de sub-mm-wa e c mpa s u eL. F. Velsquez-Garca, Y. Niu, S. Guerrera, A. I. AkinwandeSponsorship: DARPA

The continued demand for very widebandcommunications and increased need for wireless channelcapacity have led to the exploration of new regions of operation that will exploit the upper millimeter-wavespectral range. The broad minimum that occurs inatmospheric absorption between 200GHz and 300 GHz islargely under-utilized because of a lack of high-bandwidthand high-power ampli ers in this frequency range thatare compact and ef cient. The core of proposed vacuumampli er technology is a eld-emitter-array (FEA)cathode. Due to the exponential dependence of theemitted current on the emitter tip radius [1], emissioncurrents are extremely sensitive to tip radii variation.In addition, research has shown that nm-sized emittertips have a distribution with long tails [2]. Therefore,spatial variation of tip radius results in the spatialvariation of the emission currents and hence the currentdensity. The variation also results in non-uniform turn-on voltages even when the tips are located next to eachother. Moreover, at a given voltage only a small fractionof the tips in an FEA emit because the sharper tips burnout early, before the duller tips emit, resulting in under-utilization of the FEA (Figure 1). Attempts to increase theemission current by increasing the voltage often result in burnout and shifting of the operating voltage to highervoltages. Spatial non-uniformity can be substantiallyreduced if arrays of emitters are ballasted [3]. UngatedFETs are ideal to individually ballast each emitter becausethey behave like current sources and can be fabricatedwith high emitter density FEAs [4]. Limiting the currentfrom each emitter makes it possible to prevent destructiveemission from the sharper tips while allowing higheroverall current emission because of the emission of theduller tips. Using the ungated FET individual ballastingtechnology, we have demonstrated more than 600 mA of emission with no damage to the cathode (Figure 2).

FIGURE 1: Emission current IE versus gate voltage V G or varyingtip radii r. The tip radius has adistribution with variation andmean ro. The emitter current

alls within the turn-on limit(controlled by the noise oor) andthe burn-out limit (due to ohmicheating). For a constant gate bias,only a small percentage o the tipscontributes to the total emissioncurrent.

FIGURE 2: The DC (low-current)and pulsed (high current) IV characteristics o a 1-million eldemitter array. More than 600 mAo current were measured with nodamage to the cathode.

REFERENCES

[1] R. Gomer,Field Emission and Field Ionization , AmericanInstitute o Physics, New York,1961.

[2] M. Ding, G. Sha, and A. I.Akinwande, Silicon FieldEmission Arrays WithAtomically Sharp Tips: Turn-On Voltage and the E ect o Tip Radius Distribution,IEEE Transactions on Electron Devices ,Vol 49, No. 12, Dec. 2002, pp.2333 2342.

[3] H. Takemura, Y. Tomihari,N. Furutake, F. Matsuno, M.Yoshiki, N. Takada, A. Okamoto,and S. Miyano, A novel verticalcurrent limiter abricatedwith a Deep-trench- ormingtechnology or highly reliable

eld emitter arrays,Technical Digest of the IEEE International Electron Device Meeting , Dec.1997, pp. 709-712.

[4] L. F. Velsquez-Garc a, B. Adeoti,Y. Niu and A. I. Akinwande,Uni orm High Current FieldEmission o Electrons romSi and CNF FEAs IndividuallyControlled by Si Pillar UngatedFETs,Technical Digest IEEE International Electron DeviceMeeting , Washington DC, USA,Dec. 2007, pp. 599 602.



ElEctronic DEvicEs

rep du b e l h g aph a y Pa e ed Me a - x de t ala ge-a ea E eA. Wang, B. Yaglioglu, C. G. Sodini, V. Bulovi, A. I. AkinwandeSponsorship: SRC/FCRP C2S2

Metal-oxide-based eld-effect transistors (FETs) have been demonstrated with higher charge-carrier mobilities,higher current densities, and faster response performancethan amorphous silicon FETs, which are the dominanttechnology used in display backplanes [1], [2]. Becausethe optically transparent semiconducting oxide lms can be deposited at near-room temperatures, these materialsare compatible with future generations of large-areaelectronics technologies that require exible substrates[3]. Our project aims to develop a low-temperature,scalable lithographic process for metal oxide-based FETsthat can be integrated into large-area electronic circuits.

While any single demonstrated transistor may haveexcellent characteristics, circuit design using these FETsis impossible without the capability to reproduciblyfabricate FETs with uniform characteristics. Previously, wedemonstrated top-gate, fully lithographic FETs of varyingchannel lengths on 100-mm glass wafers with a sputteredZnO:In2O3 channel layer, using an organic polymer,parylene, as the gate dielectric and indium-tin-oxide(ITO) for source/drain contacts. Because of process non-uniformities, however, FET turn-off voltages (VOFF) acrossa wafer and between wafer lots varied by as much as10V. By modifying the process to deposit semiconductorand protective dielectric together without breakingvacuum, the FET uniformity across wafers was improved;the standard deviation of VOFFdecreased to



ElEctronic DEvicEs

MAtEriAls

H gh-e e -m b y Ge ma um MosFEt :the E e - ype cha e imp aa d oz e su a e Pa aJ. Hennessy, D. A. AntoniadisSponsorship: SRC/FCRP MSD

Germanium n-channel devices have historically shownpoor performance due to an asymmetric distributionof interface states that degrade electrostatic behaviorand carrier mobility. In this work, we demonstratetwo methods for improving the performance of Gen-MOSFETs: ozone surface passivation and n-typeion-implantation. Figure 1 shows the interface statedensity (D it) extracted near the middle of the bandgap by the conductance method for germanium samplesreceiving in-situ exposure to a high concentration of ozone immediately prior to Al2O3 gate deposition. Bothn-type and p-type samples that received ozone treatmentshow a signi cant reduction in Dit compared to samplesthat received a standard wet clean only. This techniquehas also been shown to result in Dit reduction near both band edges and enhanced electron and hole mobility[1]. Previous work has demonstrated enhanced electronmobility for phosphorus-implanted Ge n-MOSFETs[2]. Figure 2 shows the effective electron mobility of Gen-MOSFETs that received channel implants of arsenicor antimony in addition to ozone surface passivationprior to gate deposition. Devices receiving a 41012 cm-2 dose show a signi cant increase in electron mobility,particularly at low inversion densities, but also adegraded subthreshold slope and increased off-statecurrent, indicating some buried-channel-like behavior.Devices receiving a 11012 cm-2 implant dose showlittle degradation in subthreshold slope but maintain asigni cant enhancement in mobility compared to un-implanted devices [1].

FIGURE 1: The Dit near the middleo the bandgap or ALD Al2O3 onO3-treated germanium substrates

FIGURE 2: E ective electronmobility (split-CV) or As and Sbimplanted germanium n-MOSFETs.

REFERENCES

[1] J. Hennessy and D. A.Antoniadis, High ElectronMobility GermaniumMOSFETs: E ect o n-typeChannel Implants and OzonePassivation, inProc. 67 th Annual Device Research Conference ,2009, to be published.

[2] A. Ritenour, J. Hennessy, and D.A. Antoniadis, Investigation o carrier transport in germaniumMOSFETs with WN/Al2O3 /AlNgate stack,IEEE Electron DeviceLetters, vol. 28, no. 8, pp. 746-749, Aug. 2007.



ElEctronic DEvicEs

s /s Ge tu e g t aH. Lee, O. Nay eh, L. Gomez, J. L. Hoyt, D. A. AntoniadisSponsorship: DARPA

The tunneling eld-effect transistor (TFET) is interestingas a promising candidate for futurecomplementarymetal-oxide-semiconductor (CMOS) technology due toits potential for low-voltage operation. To successfullycompete with conventional MOSFETs,it is importantto decrease the sub-threshold swing (SS) and improvethe drive currentto reduce the power requirements.Theoretically the sub-threshold swing of TFETscould bescaled down to below 60 mV/dec at room temperaturedue to the band-to-band tunneling (BTBT) mechanism of operation. Optimization of tunneling current is complexsince it depends on several parameters such as dopingconcentration and pro le abruptness of the source, gateoxide thickness, and low band-gap material [1]. In thiswork, planar-heterojunction TFETs with Si/strainedSiGe have been fabricated with two differentnominalGe concentrations (40 % and 70 %) and with gate oxidethicknesses of 2.5 and 3.5nm. Biasing conditions have been utilized in order to observe the different tunnelinginjection mechanism such as N-channel TFET (NTFET)and P-channel TFET (PTFET). The measurement has been done in NTFET mode by using an N+ bias (VN+ >

0) condition and a negative gate bias (see inset of F1). The comparison of NTFET I-V characteristics b70 % Ge and 40 % Ge content structures is shown inFigure 1. A device with 70 % Ge contentdisplays animproved drive current and SS compared to a 40% GeNTFET due to the reduction in tunneling barrier wiand high mobility. Work is in progress with laser spiannealing (LSA) in order toimprove performance byreducing Ge out-diffusion during implant activationFigure 2 shows the comparison of NTFETs withvaryingoxide thickness. The device with the thinner gate oxhas improved drive current. Thistrait is due to theimproved coupling of the gate potential to the chann[2].

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.01E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

VN+>0+ -

+ -VG

N-type substrate

N+ Poly

N+ P+

SiO2

Floating

Si1-XGe X

BBT

VN+>0+ -

+ -VG

N-type substrate

N+ Poly

N+ P+

SiO2

Floating

Si1-XGe X

BBTBBT

I P +

( A / u m

)

VG (v)

EOT=3.5nmW=50 um, Lg=50um3 keV, BF2

70 % SiGe

40 % SiGe

NTFET

VN+=3.05 V

VN+=1.55 V

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.01E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

VN+>0+ -

+ -VG

N-type substrate

N+ Poly

N+ P+

SiO2

Floating

Si1-XGe X

BBT

VN+>0+ -

+ -VG

N-type substrate

N+ Poly

N+ P+

SiO2

Floating

Si1-XGe X

BBTBBT

I P +

( A / u m

)

VG (v)

EOT=3.5nmW=50 um, Lg=50um3 keV, BF2

70 % SiGe

40 % SiGe

NTFET

VN+=3.05 V

VN+=1.55 V

70 % SiGe

40 % SiGe

NTFETNTFET

VN+=3.05 V

VN+=1.55 V

NTFET

VN+=3.05 V

VN+=1.55 V

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.01E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

I p + ( A / u m

)

VG (v)

70 % SiGeW=50 um, Lg=50um3 keV, BF2

3.5 nm SiO2

2.5 nm SiO2

NTFETNTFET

VN+=3.05 V

VN+=1.55 V

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.01E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

I p + ( A / u m

)

VG (v)

70 % SiGeW=50 um, Lg=50um3 keV, BF2

3.5 nm SiO2

2.5 nm SiO2

FIGURE 1: Measured trans ercharacteristics (drain current, IP+versus V G) or NTFETs with 40 %SiGe and 70 % SiGe. IncreasingGe content improves the drivecurrent and sub-threshold swing. The inset shows a cross-sectionalview o the abricated TFET and anexperimental bias setup condition

or creating the NTFET operationmode.

FIGURE 2: Measured trans ercharacteristics (drain current, IP+versus V G) or NTFETs with 2.5- and3.5-nm-thick gate oxides.

REFERENCES

[1] O.M. Nay eh, C. N. Chleirigh,J. Hennessy, L. Gomez, J. L.Hoyt, and D.A. Antoniadis,Design o Tunneling Field-E ect Transistors usingStrained-Silicon/Strained-Germanium Type-II StaggeredHeterojunction, IEEE ElectronDevice Letters, vol. 29, no. 9,pp. 1074-1077, Sep. 2008

[2] W. Y. Choi, J. Y. Song, J. D.Lee, Y. J. Park, and B.-G.Park, Tunneling eld-e ecttransistors (TFETs) withsubthreshold swing (SS) lessthan 60 mV/dec, IEEE ElectronDevice Letters, vol. 28, no. 8, pp.743-745, Aug. 2007.



ElEctronic DEvicEs

MAtEriAls

impa U ax a s a a d cha e o e a Ba d- -ba d tu e g s /s Ge He e u u e

O. M. Nay eh, L. Xie, J. A. del Alamo, J. L. Hoyt, D. A. AntoniadisSponsorship: SRC/FCRP MSD, DARPA

Heterostructure tunneling eld effect transistors(HTFETs) have potential for extremely low voltageoperation (



ElEctronic DEvicEs

nAnotEcHnoloGY

n a e Mem y De e w h na pa e/H gh-k D e etu e -ba e E g ee gO. M. Nay eh, J. Hennessy, D. A. Antoniadis, K. Mantey, M. H. Nay ehSponsorship: SRC/FCRP MSD

Silicon-nanoparticle-based nonvolatile memory devicesusing uniformly delivered colloidal nanoparticles [1]are candidate replacement candidates for traditionalpolysilicon ash memory [2], [3]. Future devices areenvisioned to require the use of high-k dielectrics forachieving suitable nonvolatile memory characteristics [2].In this work we make use of novel heterojunctions formed between silicon nanoparticles and high-k dielectrics todesign and construct more optimal nonvolatile memorydevices using tunnel barrier engineering. Figure 1shows a cross-sectional TEM of silicon nanoparticlesembedded in an atomic-layer-deposited high-k dielectric(Al2O3). Figure 2 shows a select capacitance-voltage (C-V)hysteresis measurement of the device.

REFERENCES

[1] O.M. Nay eh, D.A. Antoniadis,K. Mantey, and M.H. Nay ehUni orm Delivery o SiliconNanoparticles on DeviceQuality Substrates usingSpin-Coating rom IsopropylAlcohol Colloids, Accepted orPublication in Applied PhysicsLetters(2009)

[2] O.M. Nay eh, D.A. Antoniadis,K. Mantey, and M.H. Nay eh,Memory e ects in metal-oxidesemiconductor capacitorsincorporating dispensedhighly monodisperse 1 nm Sinanoparticles, Applied PhysicsLetters , Volume 90, 153015,(2007)

[3] O.M. Nay eh, NonvolatileMemory Devices with Colloidal1.0 nm Silicon Nanoparticles:Principles o Operation,Fabrication, Measurements,and Analysis , PhD dissertation,MIT, Cambridge, MA, 2008

Al2O 3 Al2O 3

FIGURE 1: Example XTEM, aconstructed device showingsilicon nanoparticles (2.9 nm,circled) embedded in ALD-

deposited Al2O3.

.00E+00

.00E-11

.00E-10

.50E-10

.00E-10

.50E-10

-8 -4 0 4 8-8 -4 0 4 80

50

100

150

200

250

V

.00E+00

.00E-11

.00E-10

.50E-10

.00E-10

.50E-10

-8 -4 0 4 8-8 -4 0 4 80

50

100

150

200

250

V

FIGURE 2: Capacitance-voltage(C-V) hysteresis characteristics o the device.



ElEctronic DEvicEs

PHotonics

Ex p ex t aJ. Lee, C. L. Mulder, M. A. BaldoSponsorship: NRI/INDEX

Excitons, bound pairs of electrons and holes, mediatethe interconversion of charges and photons and thus can be used for an ef cient interconnect between electroniccircuits and optical communication. The ability to guideexcitons in space can lead to an excitonic switch thatdirectly routes an optical signal. Recently, High et al.demonstrated an excitonic transistor using indirectexcitons formed in AlGaAs/GaAs coupled quantumwells ata temperature of 1.4K [1]. The much larger binding energy of excitons in organic semiconductorscould enable excitonic transistors at room temperature.Furthermore, by exploiting spin-disallowed transitionsin organic materials, room temperature excitons can lastup to milliseconds, more than suf cient to enable excitonpropagation over large distances and the operation of sample circuits.In this work we aim to demonstrate an exciton transistor based on organic semiconductors that can operate atroom temperature. Exciplexes, indirect electron-holepairs situated on adjacent molecules, are interesting because they are spatially oriented witha de nedelectron-hole spacing. The exciplex energy can becontrolled by applying electric elds. Wepropose toguide exciplexes using the energy gradientdetermined by external electric elds (See Figure 1). In Figure2, we show that by changing the voltage bias over a4,4,4-tris-(3-methylphenylphenylamino)triphenylamine(m-MTDATA)/bathocuproine (BCP) heterojunction, theenergy of the exciplexes can be changed over 40meV,well above thermal energy at room temperature. We alsoobserve that long-lived exciplexes can be created witha lifetime of several microseconds at room temperaturein the phosphorescent system of N,N-diphenyl-N,N- bis(3-methyl-phenyl)-l,lbiphenyl-4,4diamine (TPD)/iridium(III) bis(4,6-di uorophenylpyridinato-N,C2)-picolinate (Firpic). These results open apromising routetoward the spatial manipulation of exciplexes in organicsemiconductors.

REFERENCES

[1] A. A. High, E. E. Novitskaya, L.V. Butov, M. Hanson, and A. C.Gossard, Control o excitonfuxes in an excitonic integratedcircuit,Science, vol. 321, pp.229-231, July 2008.

FIGURE 1: The device structureo the organic exciplex transistorand its energy pro le under theoperating condition. We controlexciplex uxes by modulating thegate bias and, thus, the potentialbarrier. The source createsexciplexes by injecting electronsand holes. The drain detects theexciplex uxes by separating andextracting them with high reversebiases.

FIGURE 2: The control o theexciplex energy by an externalelectric eld. The exciplexenergy is changed over 40meV in an organic heterojunction o m-MTDATA and BCP. Inset (A): theorganic heterojunction diodethat exhibits exciplex emission.Inset (B): the electroluminescencespectra with low and high electric

elds.



ElEctronic DEvicEs

MAtEriAls

M de g Deep- ea e i -e h va aJ. O. Diaz, H. K. Taylor, D. S. BoningSponsorship: Sandia National Laboratories

Our modeling work with deep-reactive ion-etching(DRIE) has provided effective models to account forwafer-, die-, and feature-level non-uniformities [1]-[3].The variation observed has been explained by spatial andtemporal differences in the amount of F radical species atthe wafer surface and their limited ux into features [4].Despite our previous success integrating wafer- and die-level models, fundamental incompatibilities between theseand most feature-level models had prevented us fromintegrating them together. We have revised our modelingmethods to eliminate model compatibility issues. On thewafer- and die-levels, our new approach uses a simpleelectrical network analogue (Figure 1) to predict the time-evolving concentration of the etchant species available tothe features. This prediction is used to provide estimatesof the average etch rate in different regions within thewafer. The direct compatibility with the existing feature-level semi-physical models provides the exibility to easilyincorporate future effect-modeling enhancements suchas sidewall etching and tapering. The model can also betuned to speci c tool-dependent etching characteristicsand etch recipes by the tting of parameters extractedfrom etch-depth measurements of wafers with pre-determined patterns. We are currently interested inunifying this model into a CAD tool capable of optimizingMEMS fabrication by accurately depicting the tradeoff between etching speed and uniformity in DRIE, whichrequires selecting and using the best feature-level modelavailable. Additionally, we would like to expand currentfeature-level models to correctly account for the mainsidewall effects relevant to the reliability of MEMS devices.

To Vacuum PumpTo Vacuum Pump Wafer

Gas Source

FIGURE 1: The electricalequivalent network used or DRIEwa er- and die-level modeling. Init, voltage corresponds to F radicalconcentration while currentcorresponds to radical ux in agiven direction.

REFERENCES

[1] H. K. Taylor, H. Sun, T. F. Hill, A.Farahanchi and D. S. Boning,Characterizing and predictingspatial nonuni ormity in thedeep reactive ion etching o silicon, J. Electrochem. Soc.153,C57585 (2006).

[2] T. Hill, H. Sun, H. K. Taylor, M.A. Schmidt, and D. Boning,Pattern Density BasedPrediction or Deep ReactiveIon Etch (DRIE),Tech. Digest of 2004: Hilton Head Solid-State Sensors and ActuatorsWorkshop, Hilton Head Island, SC, 2004.

[3] A. Farahanchi, Characterizationand Modeling o PatternDependencies and TimeEvolution in Plasma Etching.Masters Thesis, MassachusettsInstitute o Technology,Cambridge, 2008.

[4] R.A. Gottscho, C.W. Jurgensen,and D.J. Vitkavage, Microscopicuni ormity in plasma etching, J. Vac. Sci. Technol.B, vol. 10, pp.21332147, 1992.



ElEctronic DEvicEs

MAtEriAls

M de g E e hem a -me ha a P h g (EcMP)W. Fan, J. Johnson, D. S. BoningSponsorship: SRC/SEMATECH Engineering Research Center or Environmentally Benign Semiconductor Manu acturing

Electrochemical mechanical polishing (ECMP) is anemerging technology in semiconductor processes, usedfor Cu interconnecting layer planarization. In previouswork, our group proposed a non-ohmic ECMP modelto understand the exponential dependence of currenton overpotential at the electrode/electrolyte interfaceand to calculate the Cu removal rate [1]. Based onelectrochemical theory and process physics, the modelhas been well improved and extended to 3D accountingfor lateral voltage/current distribution and Cu-layerresistance change during the process. The calculation issimpli ed by using equivalent circuit elements to simulatethe electrochemical reaction. As Figure 1(a) shows, the model captures theelectrochemical reactions occurring at surfaces of boththe wafer and the polishing pad using equivalent diodeelements, and the lateral coupling distribution in theelectrolyte is modeled using resistive elements.. Assumingthat single-wafer rotation time is much shorter than totalpolishing time, radial time-averaged current densitydistributions on the wafer surface are calculated due tomultiple voltage zones (Figure 1(b)). From the simulationresult, we conclude that the model computes the currentdensity of the chemical reaction in the water surfaceeffectively (Figure 2(a)). Figure 2(b) shows the radialaveraged current density, which is proportional to theinstantaneous removal rate. Current work is seeking tocalculate the Cu thickness evolution during the processand extract model parameters to t experiment data.

FIGURE 1: (a) Framework o the3D ECMP model. The top voltagesource level is a pad and thebottom variable resistors levelis a Cu wa er. The electrolyte inthe middle is simulated by pureresistors. The overpotential atelectrolyte and wa er/pad sur aceis characterized by diodes. (b) Topview o pad showing multiplevoltage zones and Cu wa erposition. The wa er is connected tothe ground via the contact point inthe pads center. From the wa erscenter to its edge, the radial averagecurrent density is calculated alongthe red dashed circles.

FIGURE 2: (a) The distributiono the current density o thechemical reaction on the wa ersur ace (A/cm2) in the beginningo the process. The pad voltagzone settings are V 1=2V, V 2=1V,and V 3=3V. The blank area in thwa er image is the part underthe contact point where nochemical reaction occurs. (b) Tinstantaneous current densityalong the wa er radius at thebeginning o process. The remrate and removal amount in eactime step can be calculated witthe current density.

REFERENCES

[1] Z. Li, D. Truque, D. Boning,R. Caramto, and C. Borst,Modeling wa er leveluni ormity in electrochemical-mechanical polishing (ECMP), Advanced MetallizationConference , Albany, NY, Oct.2007.



ElEctronic DEvicEs

MAtEriAls

s ab y Me a ox de-ba ed F e d-e e t aB. Yaglioglu, A. Wang, K. Ryu, C. Sodini, A. I. Akinwande, V. BuloviSponsorship: Hewlett-Packard, DARPA

The main goal of this research is to combine a low-temperature budget fabrication method with scalableprocesses such as sputter deposition to realize oxidechannel eld-effect transistors (FETs) on glass or exibleplastic substrates. Oxide-based transistors offer anattractive alternative to commercially used amorphous Sitransistors due to their high mobility values (~10-20cm2 /Vs vs ~1cm2 /Vs) [1-3]. Field-effect mobility, sub-thresholdslope, and threshold voltage of FETs are the mainparameters that are characterized for circuits. However,reliability of properties needs to be also addressed beforethese devices take their place in large-area electronicapplications.In this study we test the stability of FETs that have apolymer dielectric, parylene, and an amorphous oxidesemiconductor, zinc indium oxide. The devices areprocessed lithographically at low temperatures (T 100 C). Figure 1 shows a typical transfer characteristicscurve representing device performance. The inset givesthe distribution of the threshold voltage across a 4-inchwafer. In Figure 2, the change in I-V characteristics isshown under a prolonged gate bias stress. The gate bias is interrupted at xed times to record the transfercharacteristics of the transistor at a drain bias of VD=1V.Preliminary results of I-V tests show a positive shift inthe threshold voltage. Two possible mechanisms thatare originally proposed for similar shifts in amorphousSi FETs are metastable state generation in thesemiconductor and charge trapping in the dielectric [4].Stability experiments at different temperatures and biasgate voltages are conducted to understand the instabilitymechanisms in these hybrid (inorganic/organic) devices.

FIGURE 1: Trans er characteristicso a W/L=100/100 transistor.Data are taken rom -5V to 5V with 0.1V steps while V D= 1V. Thedistribution o threshold voltagecollected rom 17 devices ondi erent dies across the wa er isgiven in the inset.

FIGURE 2: The V G-ID curve o atransistor as a unction o stresstime. The stress measurement isinterrupted every 180s to measurethe trans er characteristics.Measurements a ter 3min, 15min,30min, and 1h are included to showthe shi t in the characteristics.

REFERENCES

[1] P.F. Carcia, R.S McLean,M.H. Reilly, and G. Nunes,Transparent ZnO thin lmtransistors abricated by r magnetron sputtering, Applied Physics Letters, vol. 82, no. 7, pp.1117-1119, Feb. 2003

[2] N.L. Dehu , E.S. Kettenring, D.Hong, H.Q. Chiang, J.F. Wager,R.L. Ho man, C.H. Park, andD.A. Keszler, Transparentthin lm transistors with zincindium oxide channel layer, Journal of Applied Physics, vol.97, no. 6, pp. 064505:1-5, Mar.2005.

[3] H. Kumomi, K. Nomura, T.Kamiya, and H. Hosono,Amorphous oxide channelTFTs,Thin Solid Films, vol. 516,no. 7, pp.1516-1522, Feb. 2008.

[4] M.J. Powell, C. van Berkel,and J R. Hughes, Time andtemperature dependenceo instability mechanisms inamorphous silicon thin- lmtransistors, Applied PhysicsLetters, vol. 54, no.14, pp. 1323-1325, Jan. 1989.



ElEctronic DEvicEs

E e a re ab y Gan HEMt s sub a eS. Demirtas, J. A. del AlamoSponsorship: ARL MURI

GaN High Electron Mobility Transistors (HEMT) arevery promising devices for high power, high frequencyapplications due to the unique properties of the GaNsystem. However, their reliability is limited even whengrown on traditional substrates such as SiC, which hasa relatively good match with the GaN lattice. Recently,Si has emerged as a very attractive alternative to SiCsubstrates due to its low cost, availability and well-knowncharacteristics. The disadvantage of using a Si substrateis the increased lattice and thermal mismatch with GaN.This brings new reliability concerns. In our work, we havecarried out systematic reliability experiments on industrialdevices from our collaborators Nitronex Corporation andTriquint Semiconductor to understand the mechanisms of electrical degradation of GaN HEMTs on Si.One of the consequences of growing GaN-on-Si is anincreased number of traps and other electrical defects.This is observable in fresh HEMTs. Figure 1 comparescurrent transients observed in virgin GaN-on-Si and GaN-on-SiC devices after a 1 second pulse of -10V at the gate.The purpose of such a short pulse is to pump electronsinto the traps which get negatively charged and hencesuppress the 2DEG in the channel, causing a suddendecrease in drain current. As time goes on, these electronswill be detrapped from these states allowing the currentto recover to its original value before the pulse. As thenumber of traps increase, more electrons will be trappedin these states and the initial current collapse is larger.In our experiments we monitor IDlin, which is the drain

current at VDS=0.5 V and VGS=1 V. Our experimentsshow a higher current collapse and a slower recoverdevices on a Si substrate when compared to devices

SiC substrate. Clearly this shows that the higher mis between the GaN heterostructure and the Si substratcauses more traps than on a SiC substrate.Our approach to the reliability testing of GaN-on-SiHEMTs is similar to that followed in [1] and [2]. Weperform electrical stress experiments under a varietyconditions. An automated benign characterization sumonitors important gures of merit (FOM) of the desuch as maximum drain current (IDMAX), gate leakagecurrent (IGOFF), drain and source resistances (RD, RS)throughout the experiment. Measurements of FOM place at prede ned intervals and the stress is interruduring these measurements. Figure 2 shows the outpof the characterization suite for IDMAX, IGOFF, RD and R S fora GaN-on-Si HEMT. In this test, VDS=0 V and constantwhereas VGSis stepped from -5 V to -60 V by 1 V steevery 10 seconds. This is a typical case where RD andRS increase and IDMAXdecreases with increased stress.IGOFF rst decreases due to increased trapping with suntil it experiences an almost three orders of magniincrease around a stress voltage of 45 V. This increapermanent and the voltage that this occurs is referreto the critical voltage for IGOFFdegradation, VCRIT. Thisis the key signature of degradation due to the inverspiezoelectric effect.

REFERENCES

[1] J. Joh, DegradationMechanisms o GaN HighElectron Mobility Transistors,SM thesis, MIT, 2007.

[2] A. A. Villanueva, Electricalreliability o RF power GaAsPHEMTs, SM thesis, MIT, 2003.

FIGURE 1: Comparison o currenttransients in resh GaN-on-Siand GaN-on-SiC HEMTs a ter theapplication o 1 second pulse o value -10V at the gate. The currenttransient curves are normalizedto the uncollapsed values o IDlin.Note the larger current collapse inGaN-on-Si HEMT due to increasednumber o traps caused by thelarger substrate mismatch.

FIGURE 2: Output o thecharacterization suite utilized inour research or a typical electricalstress experiment. In this stresstest, V DS=0V and constant whereasV GSis stepped rom -5V to -60V by 1V every 10 seconds. RD and RS increase whereas IDMAXdecreaseswith increased stress. IGOFFexhibitsa decrease rst until the criticalvoltage or degradation is reachedwhere it increases by almost threeorders o magnitude.



ElEctronic DEvicEs

circUits & sYstEMs

rF P we cMos M me e -wa e App aU. Gogineni, J. A. del AlamoSponsorship: SRC, Intel PhD Fellowship, IBM

Radio frequency (RF) power ampli ers are corecomponents of almost all wireless systems. TraditionallyIII-V, SiC, or SiGe devices have been used in powerampli ers because of their ability to deliver highpower and operate at high frequencies. Recently therehas been an increased interest in using Si CMOS fordesigning single-chip integrated systems for operationin the millimeter-wave regime. Speci c applicationsin this regime include wireless LAN and collision-avoidance radar. A key concern in using CMOS forthese applications is the inability of CMOS to yieldhigh-ef ciency power ampli ers with power levels over10 mW in the 60-80 GHz regime. In our work, weare investigating the fundamental limitations of usingSi CMOS in power ampli ers and exploring optionsfor device optimization with the goal of enhancing themillimeter-wave power-handling ability of Si CMOS.Previous research in our group at MIT into the RF powerperformance of 65-nm and 90-nm Si CMOS devices[1], [2] has shown that the optimum device width thatdelivers the maximum power at any frequency (shown asopen diamonds in Figure 1) scales down with increasingfrequency. The effective cut-off frequency for power(frequency at which the output power drops below 10mW) can be extrapolated to be around 20 GHz for 65-nm CMOS. Peak PAE and output power are stronglycorrelated to the maximum oscillation frequency (f max) [1]and hence the decrease in output power for wide devicescan be attributed mainly to a decrease in f max.To explain the f max degradation in wide devices, small-signal equivalent circuits were extracted from thes-parameters measured on devices with different widths.The results show that the intrinsic parameters such as thetransconductance (g m) and intrinsic capacitances (Cgs andCgd) are constant across width, but the extrinsic parasiticresistances (R D and R G) increase with increasing width.In this work, device width is increased by wiring multipleunit cells (each containing 24 ngers of 2 mm width) inparallel. The additional wiring between the cells results inhigher parasitic resistances for the wider devices. Hence,the key to enabling CMOS for millimeter-wave powerapplications is a parasitic-aware approach to designing

wide devices.

Several test structures with optimized parasitics hav been designed and implemented on IBMs 65-nm an45-nm CMOS technologies. Some of the design ide being explored include (a) alternate ways of connecelemental devices in parallel, and (b) use of multipllevels and thicker levels of metal to reduce interconresistance.

FIGURE 1: Maximum power (atpeak PAE) vs. MOSFET width atdi erent requencies or 65-nmdevices (V dd =1 V) [1].

FIGURE 2: Normalizedtransconductance and parasitic

resistances vs. device width or65-nm devices (V dd=1V, ID=100mA/ mm).

REFERENCES

[1] J. Scholvin, D.R. Greenberg, andJ.A. del Alamo, Fundamentalpower and requency limitso deeply-scaled CMOS orRF power applications, inProceedings of International Electron Device Meeting 2006 ,pp. 217-220.

[2] J. Scholvin, D.R. Greenberg, andJ.A. del Alamo, Per ormanceand limitations o 65-nmCMOS or integrated RF powerapplications, inProceedings of International Electron DeviceMeeting 2005 , pp. 369-372.



ElEctronic DEvicEs

Qua um capa a e s a ed-D w iii-v HEMtD. Jin, J. A. del AlamoSponsorship: SRC/FCRP MSD, Intel Corporation

As Si CMOS fast approaches the end of the roadmap,nding a new transistor technology that would allow the

extension of Moores law has become a technical problemof great signi cance. Among the various candidatesthat are being contemplated, III-V-based Field-EffectTransistors represent a very promising technology dueto the outstanding electron-transport properties of III-Vcompound semiconductors. In particular, InGaAs-basedHigh-Electron-Mobility Transistors (HEMTs) fabricatedat MIT exhibit great logic performance and constitutean excellent test bed to explore a future III-V CMOStechnology [1].

In order to improve the logic performance of HEMTs,the barrier thickness needs to continue to scale down soas to maintain electrostatic integrity and enhance gatecapacitance. However, as the barrier thickness approachesa few nanometers in thickness, the gate capacitance doesnot increase as much as expected as a result of the niteinversion-layer capacitance. This limit comes from twomain contributions: nite quantum capacitance [2] andthe centroid capacitance. The rst one originates inthe extra energy required to create a two-dimensionalelectron gas (2DEG) in a quantum well due to the nitedensity of states. The second one is related to the shapeof the charge distribution in the inversion layer [3]. Inscaled-down III-V HEMTs, due to the small effective massof electrons in the channel, these two effects conspireto seriously limit the overall gate capacitance of thedevice and limit its current driving capability. Correct

understanding of these effects and accurate modelinare essential to predicting the logic performancecharacteristics of future scaled III-V FETs.In this research, we model the gate capacitance of HEMTs (Figure 1) and compare it with experimentameasurements on devices fabricated at MIT (Figure2). Using a one-dimensional Poisson-Schrodingersolver (Nextnano), we show that the overall gatecapacitance of HEMTs can be modeled precisely as series combination of an insulator capacitance and tinversion-layer capacitance. This one consists of a pcombination of the contributions of each occupied

electron subband. For each sub-band, the inversion-layer capacitance consists of the quantum capacitan(CQ_i) and the centroid capacitance (Ccent_i), which areconnected in series (Figure 1). We have performedS-parameter measurements and extracted the gate-capacitance characteristics of InGaAs HEMT structwith 4-nm barrier thickness in the linear regime [4]The measurements agree very well with the modelecapacitance (Figure 2).Our model suggests that in the operational range of these devices, the quantum capacitance signi cantlylowers the overall gate capacitance of the device. Thresearch suggests that it is important to explore newways to increase the quantum capacitance in order tdevelop scaled down III-V FETs with superior logic

characteristics.

REFERENCES

[1] D-H. Kim and J.A. del Alamo,Scaling behavior o In0.7Ga0.3AsHEMTs or LogicInternational Electron Devices MeetingTechnical Digest , pp. 837-840,Dec 2006

[2] S. Luryi, Quantum capacitancedevices Applied Physics Letter,vol. 52, pp. 501-503, Feb 1988.

[3] H. S. Pal, J. D. Cantley, S. S.Ahmed, and M. S. Lundstrom,Infuence o Bandstructureand Channel Structure on theInversion Layer Capacitance o Silicon and GaAs MOSFETsIEEE Transactions on Electron Devices ,vol. 55, pp. 904-908, Mar 2008

[4] D-H. Kim, to be published

FIGURE 1: The gate-capacitancemodel used in this work. For eachsubband, the inversion-layercapacitance is the series o thequantum capacitance and thecentroid capacitance.

FIGURE 2: Experimental andmodeled gate capacitance o 4-nm barrier thickness InGaAsHEMTs in the linear regimeas a unction o applied gatevoltage. The 1st electron subbanddominates in the HEMTsoperational range. The quantumcapacitance severely brings downthe overall gate capacitance.



ElEctronic DEvicEs

rF re ab y Gan H gh-e e -m b y t aJ. Joh, J. A. del Alamo in collaboration with TriQuint SemiconductorSponsorship: Army Research Laboratory (contract # W911QX-05-C-0087)

Thermally accelerated RF life tests (RFLT) are widelyaccepted as the most reliable ways to evaluate thelifetime of RF ampli ers in the eld. However, RF lifetests require arelatively complicated setup and anaccurately determined and controlled device channeltemperature, which is sometimes very dif cult to achieve.The situation is particularly complex for high-powerdensity technologies such as GaN high-electron-mobilitytransistors (HEMTs) or high-voltage GaAs-baseddevices. Also, in terms of understanding the physics of degradation, RFLT is somewhat cumbersome because achange in RF output power can result from a variety of different causes.In order to overcome these complexities, DC life tests(DCLT) are often preferred due to their simplicity.In addition, during DCLT, better insight into failuremechanisms can be obtained by monitoring changesin various DC parameters such as the maximum draincurrent, IDmax, and the threshold voltage,VT [1]. Thoughsimple to implement, DC life tests have several limitations.First, the choice of stress bias conditions is not obvious.Second, DC life tests can at most only hope to emulatethe DC conditions of the RF ampli er and not the impactof the RF waveform. Thus, they can be immune to sometypes of degradation (e.g., RF breakdown degradation)that could be presentonly under RF conditions. Third,DC life tests may not predict the lifetime under RFconditions if degradation of a wrong DC parameter thatis irrelevant to RF power degradation is chosen as afailure criteria. It is then of great importance to establisha correlation between the degradation that is producedduring DCLT and RFLT [2].

In this work, using TriQuints X-Band GaN HEMTtechnology, we study how DC and RF gures of medegrade during DC and RF stresses. Unlike conventRF life tests in which only RF output power, Pout,and quiescent DC current, IDQ, are monitored, weincorporated a characterization suite that extracts seDC parameters such as IDSS(drain current at VGS=0)and VT in the RFLT. UnderRF stress , it was found thatIDSSis a better indicator of Pout degradation than IDQ (Figures 1 and 2). Similarly, during DCLT in which wregularly measure RF performance gures of merit,DSS degradation was found to correlate well witha drop inPout. Other DC gures of merit such as IDQ or VT did notshow a clear correlation with Pout. Also, we found thatdue to the larger voltage swing beyond the DC bias which prevails under large RF power input, RF stresdegrade GaN HEMTs much more than DC stress doeven at the same VDSand device channel temperature.particular, the gate current can seriously degrade unRF stress, with a serious impact on Pout.With this understanding of the correlation between Dand RF degradation, we can focus on DC gures ofin DCLT that are more relevant to real RF output podegradation. This focus will help us understand phydegradation mechanisms of GaN HEMTs. Also, we better design DC stress experiments that can accurapredict RF reliability.

REFERENCES

[1] J. Joh and J. A. del Alamo,Mechanisms or electricaldegradation o GaN high-electron mobility transistors,IEEE IEDM Tech. Digest , pp.415-418, 2006.

[2] J. Joh, J. A. del Alamo, U.Chowdhury, and J. L. Jimenez,Correlation between RF andDC reliability in GaN highelectron mobility transistors,ROCS Workshop Proceedings, pp.185-188, 2008.

FIGURE 1: Correlation betweendegradation in Pout and IDSS or 10di erent devices rom a singlewa er.

FIGURE 2: Correlation betweendegradation in Pout and IDQ_DC orthe same experiment in Figure 1.



ElEctronic DEvicEs

i e ed- ype i GaA HEMt l g App aT.-W. Kim, D. H. Kim, J. A. del AlamoSponsorship: SRC/FCRP MSD, Intel Corporation

As conventional CMOS scaling approaches the endof the roadmap, III-V-based FETs are seriously beingconsidered as an alternative logic technology [1]. For anynew device technology to take over the CMOS roadmap,electrical characteristics superior to those of Si CMOS arerequired in terms of performance (ON current and OFFcurrent) and short-channel effects (evaluated throughsubthreshold swing and DIBL, among other gures of merit) at the required device dimensions [2]. The III-Vhigh-electron-mobility transistor (HEMT) represents anexcellent model system to study issues of relevance infuture III-V MOSFETs. In order to gracefully scale intothe deep sub-100-nm range, the barrier thickness (a wide bandgap semiconductor in the case of a HEMT) needsto be scaled down into the few-nm range. At MIT we areinvestigating InAlAs/InGaAs HEMTs with reduced InAlAs barrier thickness by three-step gate-recess process [3] andPt-sinking-gate technology [4]. A drawback of a reduced barrier thickness is a large gate leakage current. In orderto counteract this, we are currently investigating inverted-type InAlAs/InGaAs HEMTs where there are no dopantsin the InAlAs barrier above the channel. The expectedtrapezoidal-shaped barrier should signi cantly reduce thegate leakage current level.We have fabricated 30-nm gate-length inverted-type InAlAs/InGaAs HEMTs on InP substrate. Theheterostructure was designed to have Si delta-doping

layers both above and below the channel. In the intrregion of the device, the dopants are removed from top barrier through a three-step gate recess process.In this way, a barrier thickness of 5 nm was achieveFigure 1 shows the subthreshold characteristics of representative 30-nm inverted-type InGaAs HEMTswith typical conventional InGaAs. The inverted HEexhibit a reduction in gate leakage current of aroundorder of magnitude when compared with conventiondevices of similar dimensions. In addition, they shoexcellent short-channel effect characteristics with SmV/dec and DIBL = 80 mV/V. Figure 2 shows ION /IOFF ratio as a function of gate length. The ION /IOFFratio of the inverted HEMTs is nearly 105 at VDD = 0.5 V and itis fairly constant as the device scales down in size. Tresults reveal the bene ts of the trapezoidal-shapedenergy barrier under the gate. Unfortunately, there adrawbacks to this device design. These devices showa larger source resistance than conventional devices because of the high tunneling resistance associated the higher energy barrier of the cap/barrier/channelregion. The transconductance of 30-nm devices is 1S/mm at VDS=0.5 V and the source resistance is 0.39mm, as extracted by the gate current injection meFor a process optimization, we hope to improve theperformance of 30-nm inverted-type InAlAs/InGaAHEMTs by reducing the parasitic resistances througnew ohmic contact scheme.

REFERENCES

[1] J. del Alamo and D.-H. Kim,Beyond CMOS: LogicSuitability o InGaAs HEMTs,in Indium Phosphide & Related Materials(IPRM)Proceeding, pp.14-18, May 2006.

[2] J. del Alamo and D.-H. Kim,InGaAs CMOS: a Beyond-the-Roadmap Logic Technology?in Device Research Conference(DRC) Proceeding., pp. 201-202,June 2007.

[3] D.-H. Kim and J. del Alamo,30-nm Pseudomorphic HEMTson an InP Substrate With aCurrent-Gain Cuto Frequencyo 628 GHz,IEEE Electron DeviceLetters, Vol. 29, No. 8, Aug. 2008.

[4] D.-H. Kim and J. del Alamo,30 nm E-mode InAs PHEMTs

or THz and Future LogicApplications, inInt. ElectronDevices Meeting (IEDM) Tech.Dig., pp. 719-722, Dec. 2008.

20 40 60 80 100 120 14010 3

10 4

10 5

10 6

In0.7Ga 0.3As HEMT

Lg [nm]

VDS=0.5V

Inverted In 0.7Ga 0.3As HEMT

FIGURE 1: Subthresholdcharacteristics o inverted-typeInGaAs HEMTs with conventionaltype InGaAs and channel normalHEMTs.

FIGURE 2: The ION /IOFFratio o inverted-type InGaAs HEMT andconventional InGaAs HEMTs as a

unction o gate length.



ElEctronic DEvicEs

MAtEriAls

impa s a he cha a e i GaA HEMtL. Xia, J. A. del AlamoSponsorship: SRC/FCRP MSD

With the incorporation of mechanical strain into thechannel of Si MOSFETs, electron and hole mobilities have been improved by 2x and 3x, respectively, as comparedwith their unstrained counterparts [1], [2]. Just as withSi, it is of interest to study the impact of strain on thetransport characteristics of InGaAs, a material that iscurrently receiving a great deal of attention as a post-SiCMOS logic technology. Our work studies the impact of strain on the electrostatics and transport properties of InGaAs High Electron Mobility Transistors (HEMTs).We have fabricated a chip-bending apparatus thatallows us to apply either tensile or compressive uniaxial

strain to a small chip while conducting electricalmeasurements. Chips with size down to 2 mm x 4 mmcan be accommodated. The strain level can be as high as+/-0.4%.By applying unaxial strain to an n-channel InGaAsHEMT, we found that the threshold voltage shiftslinearly with the applied strain, up to about 30 mV, asshown in Figure 1. This shift is due to the introduction

of piezoelectric charge into the device due to in-planstrain and a change of the Schottky barrier height duto the hydrostatic pressure component. The linearregime transconductance also changes with strain. Tunderlying mechanism for this change is likely to bcombination of change in the electrostatic characterof the InGaAs quantum well and the mobility of 2DIn parallel, we are fabricating our own p-channel IIIFETs in an effort to study the impact of mechanical on hole transport. We have developed a fabricationprocess for strain-free p-type Al0.42Ga0.58 As/GaAs HEMTThe saturation current and maximum transconducta

of a 2-m-long HEMT are 22 mA/mm and 16 mS/m(at VDS=-2 V), respectively. Figure 2 shows the outpucharacteristics. However, the devices suffer from exgate leakage current that prevents them from beingcompletely turned off. After solving this problem, wwill be able to experimentally study the strain impap-channel III-V-based device performance.

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.00

5

10

15

20

VGS

: 0.6V~-0.8V VGS :-0.2V

VDS (V)

FIGURE 1: Threshold voltage(V T ) shi t o n-type Al0.23Ga0.77As / In0.15Ga0.85As HEMT under strain. The V T is de ned as V GSwhen IDS=1 mA/mm. Strain is applied parallelto the channel direction [-110].

FIGURE 2: Output characteristicso p-type Al0.42Ga0.58As/GaAs HEMT. The gate length is 2 m.

REFERENCES

[1] J. R. Hwang, J. H. Ho, S. M.Ting, T. P. Chen, Y. S. Hsieh, C. C.Huang, Y. Y. Chiang, H. K. Lee, L.Ariel, T. M. Shen, G. Braithwaite,M. Currie, N. Gerrish, R.Hammond, A. Lochte eld, F.Singaporewala, M. Bulsara, Q.Xiang, M. R. Lin, W. T. Shiau, Y.T. Loh, J. K. Chen, S. C. Chien, F.Wen, Per ormance o 70 nmstrained-silicon CMOS devices,Digest o Technical Papers.2003 Symposium on, 2003, pp.103-104.

[2] L. Washington, F. Nouri, S.Thirupapuliyur, G. Eneman, P.Verheyen, V. Moroz, L. Smith,X. Xiaopeng, M. Kawaguchi, T.Huang, K. Ahmed, M. Balseanu,X. Li-Qun, S. Meihua, K. Yihwan,R. Rooyackers, M. Kristin De, R.Schreutelkamp, pMOSFET with200% mobility enhancementinduced by multiple stressors,Electron Device Letters, IEEE 27(2006) 511-513.



ElEctronic DEvicEs

MAtEriAls

Ad a ed sub a e E g ee g:i eg a i P la e c a sL. Yang, E. A. FitzgeraldSponsorship: SRC/FCRP MSD

Integration of the InP lattice constant with Si CMOSplatforms is motivated by the monolithic interconnectionof III/V optoelectronic and electronic devices with thehighly integrated Si logic. However, integration of InPon Si requires a comprehensive solution that addresseslattice mismatch, thermal expansion mismatch, IV/III-Vintegration, and alloy engineering challenges. We investigated III/V graded () buffer on 6 offcutGaAs substrate in combination with 6 offcut Ge onInsulator (GOI) substrate to integrate InP on Si. First,we chose 6 offcut GOI as the substrate toaccommodatethe antiphase disorder in the IV/III-V integration [1]and

established excellent GaAs epitaxy on the substrate withproper surface preparation. Then we investigated twopaths to integrate InP on 6 offcut GaAs: GaAs/InxGa1-x As/InyGa1-yP/InP as shown in Figure 1 and GaAs/GaAs1-xSbx /InP as shown in Figure 2. For the GaAs/

InxGa1-x As/InyGa1-yP/InP path, we demonstrated the integration of InP on 6 offcut GaAs with a threadindislocation density (TDD) of 7.9x106 /cm2. The totalInxGa1-x As/InyGa1-yP buffer thickness is 4.0 um, whshould be thin enough toavoid the cracking problemthat can be caused by the thermal expansion misma between InP and Si. However, it was demonstrated GaAs1-xSbx can be grown with compositions in the ranof solid immiscibility [2].We investigated GaAs/GaA1-xSbx /InP path to get InP lattice constant on 6 offcutGaAs. GaAs1-xSbx was gradually graded from GaAs tGaAs0.51Sb0.49,which is lattice-matched to InP, and InPdeposited on top. The interface of GaAs0.51Sb0.49 /InP stillneeds to be optimized to get good quality InP layer.Forthe next step, we will further optimize the GaAs/G1-xSbx /InP path and combine InP on GaAs together witGaAs on GOI to realize the integration of InP on Si

REFERENCES

[1] S. M. Ting and E. A. Fitzgerald,Metal-organic chemical vapordeposition o single domainGaAs on Ge/GexSi1-x /Si and Gesubstrates, Journal of Applied Physics, vol 87, pp.2618-2628,March 2000.

[2] M. J. Cherng, G. G.String ellow, and R. M. Cohen,Organometallic vapor phaseepitaxial growth o GaAs0.5Sb0.5, Applied Physics letters, vol 44,pp.677-679, Jan. 1984.

575C GaAsSb

500C InP

FIGURE 1: An XTEM o 6 o cutGaAs/InxGa1-xAs/InyGa1-yP/InP.

FIGURE 2: An XTEM o 6 o cutGaAs/GaAs1-xSbx /InP.



ElEctronic DEvicEs

PHotonics

cha a e se e e y G w Ge- -s Ph d deN. DiLello, J. Yoon, M. Kim, J. Orcutt, J. L. HoytSponsorship: SRC student ellowship, DARPA

Germanium is a promising candidate for use in CMOS-compatible photodiodes. Its strong absorption in the1.55-m range and relative ease of integration on siliconsubstrates make it suitable for telecommunications systemsand other high-speed electronic photonic integratedcircuits. Important gures of merit for these photodiodesare the reverse leakage current and the responsivity. Toreduce power consumption and improve the signal-to-noise ratio, the diodes must have a low leakage currentin reverse bias and a high responsivity. This studyhas investigated the leakage current and responsivityof germanium photodiodes selectively grown by low-pressure chemical vapor deposition (LPCVD) using an Applied Materials epitaxial reactor.To fabricate these diodes, germanium was grownselectively in oxide windows on a p+ Si substrate. Thewafers then received an in-situ cyclic anneal to reducethe threading dislocation density. The wafers weresubsequently implanted with phosphorus to create avertical pin junction and contacted with metal. In thisstudy, the Ge thickness was either 1 m or 2 m. Thecurrent vs. voltage characteristics for 100-m squaredevices show that the dark current is ~250 nA at -1 Vfor both of these samples, as indicated in Figure 1. Ithas previously been noted that the threading dislocationdensity of Ge-on-Si lms decreases with increasingthickness, indicating that lm quality is better for thicker

samples [1]. This suggests that Ge lm quality is not thelimiting factor in this case and more study is needed tofurther characterize the dark current. Figure 2 shows theresponsivity vs. wavelength plot for both 1-m- and 2-m-thick samples. At -1 V and 1550 nm, the 1-m sampleand 2-m sample have responsivities of 0.23 A/W and0.46 A/W respectively. This 2x increase in responsivity isconsistent with the increase in Ge thickness.

FIGURE 1: Current vs. voltageor a 1-m-thick (green) sample

and a 2-m-thick (red) Ge sample. The dark current in reversebias is virtually the same orboth samples, suggesting thatsomething other than materialquality is limiting the leakage.Both devices are 100 m square.Inset: Cross-sectional schematicdiagram o a Ge-on-Si photodiode.

FIGURE 2: Responsivity as aunction o wavelength or a

1-m-thick (green) sample anda 2-m-thick (red) Ge samplemeasured at a bias o -1 V. At 1550nm, the responsivity o the thinsample is hal o the responsivityo the thick sample. Both devicesare 100 m square.

REFERENCES

[1] M. Kim, O. Olubuyide, J.Yoon, and J.L. Hoyt, SelectiveEpitaxial Growth o Ge-on-Si orPhotodiode Applications,ECSTransactions , vol. 16, issue 10,pp. 837 847, 2008.



ElEctronic DEvicEs

s a ed s Ge- ha e p-MosFEt i u aL. Gomez, P. Hashemi, J. L. HoytSponsorship: SRC/FCRP MSD, MIT Lemelson Presidential Fellowship

Scaling of CMOS-device dimensions alone can no longerprovide the necessary current drive enhancementsrequired to continue historic performance gains.Strained-Si, SiGe, and Ge are under investigation as Sireplacement technologies due to their enhanced carrier-transport properties [1]-[3]. Biaxial compressive strained-Si0.45Ge0.55p-MOSFETs with gate lengths down to 65 nmhave been fabricated to explore the merits of a strained-Si0.45Ge0.55channel. Care was taken to avoid process stepsthat might alter or eliminate the strain in the channel.Hole mobility and velocity have been extracted and are benchmarked against a comparable Si control device.The dR/dL mobility extraction method was employedto determine the mobility of scaled p-MOSFETs withgate lengths in the range of 65-150nm [4]. Devices inthis gate length range are observed to exhibit a 2.4xhole effective mobility enhancement over the Si holeuniversal mobility. Three velocity extraction methodswere employed and the velocity characteristics of scaledstrained-Si0.45Ge0.55p-MOSFETs have been documented[5], [6]. A velocity enhancement is observed in stained-Si0.45Ge0.55p-MOSFETs over control devices with a similargate length and DIBL. The velocity enhancement is inthe range of 1.1-1.3x. This enhancement is observed toincrease with increasing proximity to the source injectionpoint. Band structure and ballistic velocity calculationssuggest that a substantial enhancement in velocity can beexpected with the incorporation of Ge into the channeland the addition of uniaxial stress [7], [8]. Simulationspredict that a moderate amount of Ge (e.g., Si0.45Ge0.55)coupled with -5 GPa of uniaxial stress can provide avelocity enhancement of 4.3x. This velocity is nearly two-fold larger than what Si is expected to provide with anequivalent amount of uniaxial stress.

FIGURE 1: The enhancementrelative to the Si control or theaverage id, gmi, and xo extractedhole velocities. The strained-Si0.45Ge0.55p-MOSFETs exhibit anenhancement over Si controldevices ranging rom 1.13-127x.All devices have an average LGate =150 nm and DIBL = 140 mV/V.

FIGURE 2: The simulatedballistic velocity enhancementrelative to relaxed Si with appliedcompressive uniaxial stress orSi, biaxial compressive strained-Si0.45Ge0.55pseudomorphic torelaxed-Si (Si0.45Ge0.55 /Si), Ge, andbiaxial compressive strained-Gepseudomorphic to relaxed-Si0.6Ge0.4(Ge/Si0.6Ge0.4). Simulationswere per ormed using nextnano3 and FETtoy [7], [8].

REFERENCES

[1] S.W. Bedell, A. Majumdar,J.A. Ott, J. Arnold, K. Fogel,S.J. Koester, and D.K. Sadana,Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs,IEEE Electron Device Letters, vol. 29,no. 7, pp. 811-813, July 2008.

[2] S. Thompson, N. Anand, M.Armstrong, C. Auth, B. Arcot, M.Alavi, P. Bai, J. Biele eld, R.Bigwood, J. Brandenburg, M.Buehler, S. Cea, V. Chikarmane,C. Choi, R. Frankovic, T. Ghani,G. Glass, W. Han, T. Ho mann,M. Hussein, P. Jacob, A. Jain,C. Jan, S. Joshi, C. Kenyon, J.Klaus, S. Klopcic, J. Luce, Z.Ma, B. Mcintyre, K. Mistry, A.Murthy, P. Nguyen, H. Pearson,T. Sand ord, R. Schwein urth,R. Shaheed, S. Sivakumar, M.Taylor, B. Tu ts, C. Wallace, P.Wang, C. Weber, and M. Bohr,

A 90 nm logic technologyeaturing 50 nm strained siliconchannel transistors, 7 layer Cuinterconnects, low k ILD, and 1m2 SRAM Cel l, inIEDM Tech.Dig.,2002, pp. 61-64.

[3] M.L. Lee and E.A. Fitzgerald,Optimized strained Si/strained Ge dual-channelheterostructures or highmobility P- and N-MOSFETs,in IEDM Tech. Dig., 2003, pp.18.1.1- 18.1.

[4] K. Rim, S. Narasimha, M.Longstreet, A. Mocuta, andJ. Cai, Low eld mobilitycharacteristics o sub-100 nmunstrained and strained SiMOSFETs, inIEDM Tech. Dig.,2002, pp. 43.

[5] A. Lochte eld and D.A.Antoniadis, On ExperimentalDetermination o CarrierVelocity in Deeply ScaledNMOS: How Close to theThermal Limit?,IEEE ElectronDevice Letters, vol. 22, no. 2,Feb. 2001.

[6] A. Khaki rooz and D.A.Antoniadis, TransistorPer ormance Scaling: The Roleo Virtual Source Velocity andIts Mobility Dependence, inIEDM Tech. Dig., 2006, pp. 1-4.

[7] nextnano3, NEXTNANO,Munich, Germany, 2007.Available: http://www.nextnano.de/

[8] FETtoy 2.0, nanoHUB, PurdueUniversity, West La ayette,IN, 2008. Available: https://nanohub.org/tools/ ettoy/wiki



ElEctronic DEvicEs

MAtEriAls

U ax a s a ed-s Ga e-a -a u d na w e FEtP. Hashemi, L. Gomez, J. L. HoytSponsorship: SRC/FCRP MSD, IBM Fellowship

Multi-gate device architectures such as tri-gate or Gate-all-around (GAA) nanowire (NW) MOSFETs are promisingcandidates for aggressively scaled Si-based CMOS dueto their excellent electrostatics, low power consumption,and immunity to short channel effects [1], [2]. However,several effects such as quantum mechanical con nementeffects and the non-ideality of the NW sidewalls play asigni cant role in degrading the performance of thesedevices. As a result, strain engineering of the Si NWchannel is critical to improve device performance.In this work, GAA strained-Si NW n-MOSFETs werefabricated using a top-down approach and their intrinsic

and extrinsic performance was measured. Figure 1 showsa sample cross-section transmission electron microscopyimage of a GAA strained-Si n-MOSFET, looking downthe axis of the nanowires in the device channel, showingparallel nanowires with diameter ~ 8 nm, and LTO gatedielectric. Mobility of the GAA nanowires was extracted by measuring the intrinsic gate-channel capacitanceusing the split-CV method, after subtracting the parasiticcapacitance measured on neighboring structures withoutNWs. The channel intrinsic conductance was correctedfor series resistance. Figure 2 shows the electron effectivemobility vs. average inversion charge density for ~49 nm-wide strained-Si GAA NWs, measured by both the 2-FETmethod and split CV, demonstrating excellent agreement between the two mobility extraction techniques. Universal(100) mobility and the mobility of planar SOI and SSDOI(t=8.7nm, close to the average thickness of strained-Si NW) and unstrained-Si NWs (WNW=44nm) are alsoshown for comparison. The strained-Si nanowire showsmobility enhancement over universal, thin-body planarSOI and SOI NW devices (with the slightly smaller widthof ~44nm).

FIGURE 1: Cross-sectiontransmission electron microscopyimage o a GAA strained-Sin-MOSFET, looking down theaxis o the nanowires in thedevice channel, showing parallelnanowires with diameter ~ 8 nm,and LTO gate dielectric [3].

FIGURE 2: Low- eld electronmobility (e ) vs. average chargedensity (Ninv) o GAA strained-Si nanowire (WNW= 49nm)measured by the split-CV and2-FET methods. The e or thewidest unstrained-Si nanowire(W=44nm), planar SOI, SSDOI(t=8.7nm), and universal areshown or comparison [4].

REFERENCES

[1] B. Doyleet al. Tri-Gate Fully-Depleted CMOS Transistors:Fabrication, Design and Layout,in VLSI Symp. Tech. Dig., 2003,pp. 133-134.

[2] S.-D. Suk et al. HighPer ormance 5nm radius TwinSilicon Nanowire MOSFET(TSNWFET): Fabrication on Bulk Si Wa er, Characteristics, andReliability, inIEDM Tech. Dig.,2005, pp. 735-738.

[3] P. Hashemi, L. Gomez, andJ.L. Hoyt, Gate-All-AroundN-MOSFETs with UniaxialTensile Strain-InducedPer ormance EnhancementScalable to Sub-10-nmNanowire Diameter,IEEE Electron Device Lett., vol. 30, no.4, pp. 401-403, April 2009.

[4] P. Hashemi, L. Gomez, M.Canonico, and J.L. HoytElectron Transport inGate-All-Around UniaxialTensile Strained-Si Nanowiren-MOSFETs, inIEDM Tech. Dig.,2008, pp. 865-868.



ElEctronic DEvicEs

MAtEriAls

A supe du y sw h c u ed a Eus/A /Eussa dw h s u u eG. X. Miao, C. H. Nam, C. A. Ross, J. S. MooderaSponsorship: NSF, ONR

Superconductivity is known to be tunable with spin-polarized carriers as the excess spins suppress the spinsinglet state of Cooper pairing [1]. In this work weattempt to use a magnetic insulator to generate netspin accumulations in a thin superconducting Al layer.It was shown that the exchange interaction betweenthe conduction electrons and the rst ferromagneticlayer can lead to large spin-dependent variation in thesuperconducting transition temperatures [2]. We takeadvantage of such properties and show that large Zeemansplitting is indeed generated inside the thin Al layer, andthat the Al lm can be driven back and forth between itsnormal state and superconducting state with an external

eld, leading to virtually in nite magnetoresistance(Figure 1). When the lateral dimension of the structureis reduced (for example, see structures in Figure 2), westart to see very complicated magnetic responses, as aresult of the domain wall formation and propagation. Ourcurrent study focuses mainly on the effect of domain wallson superconductivity and the use of nanoconstrictions intuning the resulted magnetoresistance.

FIGURE 1: Illustration o thesuperconducting switch behaviorin an unpatterned sandwichsample with the structure (in nm):glass/1 Cr/ 1.5 EuS/6 Al/7.5 EuS/15Al2O3.

FIGURE 2: An SEM image o e-beam patterned nanostrips. Asingle li t-o step is used in its

abrication.

REFERENCES

[1] G. X. Miao, K. S. Yoon, T.S. Santos, J. S. Moodera,Infuence o spin-polarizedcurrent on superconductivityand the realization o largemagnetoresistance, Physical Review Letters, vol. 98 , pp.267001:1-4, June 2007.

[2] P. G. de Gennes, Couplingbetween erromagnets througha supercnducting layer, PhysicsLetters, vol. 23, pp. 10-11, Oct.1966.



ElEctronic DEvicEs

nAnotEcHnoloGY

cha ge t a p s ud e s g e- y a o ga F e d-e et aK. V. Raman, J. S. MooderaSponsorship: ONR, KIST

PHotonics

The research is motivated by the current developmentin the eld of organic electronics [1]. Organic materialsprovide cheap, low-cost, mechanically exible, andchemically tunable devices with performances comparableto or even better than amorphous Si. Also, these materialspossess relatively good spin-transport properties [2-4],generating signi cant interest in these materials.We have investigated charge transport in single crystals of organic semiconductor (OS), rubrene, with ferromagneticelectrode (FM) viz Co in addition to the conventional Au electrodes. Unlike that of gold, the surface stabilityof these electrodes to air is crucial and requires smart

processing and fabrication steps to have clean FM-OSinterfaces. A thin layer of Al (~ 6-10, grown at lowtemperature (80K)) was used to protect the Co surfaceand was found to give lower contact resistance. Onexposure to air, an Al2O3 layer is formed that serves asa good tunnel barrier for charge injection. Figure 1shows the four terminal-transfer characteristics of ourFET devices. A mobility of 2cm2 /V-s is reported with theobservation of source-drain current saturation at higher

gate bias, attributed to the strong columbic interactiof the polaron charge carriers in the accumulationlayer. Such effects have been reported before in high-dielectrics like Ta2O3 [5]. However, our results showthat by considerably increasing the charge density (our case by having large gate capacitance Ci ~ 35nF/cm2),these effects show up. To further con rm the origin such effect to the intrinsic nature of charges in rubremeasurements were performed using Au electrodesshown in Figure 2, showing similar results. This wotries to gain fundamental understanding of the compcharge-transport mechanisms in organic materials analso for the proposed research goal of injection-spininformation in these materials.We would like to acknowledge Professor Marc Bald(EECS) and his graduate student Carlijn Mulder forhelping us use their organic growth facility.

FIGURE 1: Sur ace conductivity vsgate voltage measured at di erenttemperatures or Co/Al electrodes.Inset shows the 4-terminalelectrode geometry (L channellength, D- distance between thesense leads). Current saturationat high gate bias is observedand becomes stronger at lowertemperatures.

FIGURE 2: Sur ace conductivityvs. gate bias measured using Auelectrodes. Current saturation iscon rmed to originate due to theintrinsic nature o charge-carriersin rubrene.

REFERENCES

[1] S.R. Forrest, Ultra-thin OrganicFilms Grown by OrganicMolecular Beam Depositionand Related Techniques, Chem.Rev., vol. 97, pp. 1793-1896,1997.

[2] Z. H. Xiong, Di Wu, Z. ValyVardeny & Jing Shi, Giantmagnetoresistance in organicspin-valves, Nature, vol. 427,pp. 821-824, 2004.

[3] T.S. Santos, J. S. Lee, P. Migdal,I.C. Lekshmi, B. Satpati, and J. S.Moodera, Room-temperaturetunnel magnetoresistanceand spin-polarized tunnelingthrough an organicsemiconductor barrier, Phys.Rev. Lett., vol. 98, 016601, 2007.

[4] . Mermer, G. Veeraraghavan,T. L. Francis, Y. Sheng, D. T.Nguyen, M. Wohlgenannt,A. Khler, M. K. Al-Suti,and M. S. Khan, Largemagnetoresistance innonmagnetic -conjugatedsemiconductor thin lmdevices , Phys. Rev. B, vol. 72,205202, 2005.

[5] S Fratini et al, Currentsaturation and Coulombinteractions in organic single-crystal transistors, New J. Phys.,vol. 10, 033031, 2008.



ElEctronic DEvicEs

MAtEriAls

s a d s -Ge ma um Mag e - u e g-em e B pt aM. van Veenhuizen, D. Choi, J. Chang, Y.-H. Xie, J. MooderaSponsorship: DARPA, KIST-MIT

We investigate a novel approach to spin-injection, basedon the bipolar junction transistor, that has the potential togenerate the large spin-currents inside the silicon neededto make functional spin-devices. Speci cally, we employthe tunneling-emitter bipolar transistor with the emittercontact being a ferromagnet, as a spin-injection device.Tunneling-emitter bipolar transistors with a metallicemitter have been fabricated before [1], but never withthe metal being a ferromagnet. We have successfullyfabricated working transistors out of silicon, and Figure1 shows an SEM micrograph of a device [1]. We nd,however, that the current gain is very low, as seen inFigure 2 [2]. As we describe in [2], this can be attributedto recombination at the oxide-silicon interface due tothe imperfect tunnel-barrier. Our current focus is onimproving the tunnel-barrier quality. In addition, we areworking on integrating this spin-injection device into asilicon-germanium heterostructure in order to inject spininto a silicon quantum well. The high-mobility quantumwell has a very long spin-coherence length and the 2dcon nement allows for the fabrication of functional spin-devices, as for instance the Datta-Das transistor [3].

FIGURE 1: An SEM micrographo a tunneling-emitter bipolartransistor. The base and emittercontacts consist o alternatinglong stripes, separated by athermal oxide (TOX). The emitterconsists o a erromagnet/tunnel-barrier stack; or this device, iron/ magnesium-oxide.

FIGURE 2: Collector currentversus collector-emitter voltage

or di erent base currents or thedevice shown in Figure 1 [1]. Thecurrent gain hFEo the device isonly slightly above 1. Also shown

are ts to the initial and nalslopes. The substantial nal slopevalue is a result o the very thinbase width, approximately 1000 .

REFERENCES

[1] H. Kisaki, Tunnel transistor,PROC IEEE, vol. 61, pp. 1053-1055, 1973

[2] M. van Veenhuizen, J. Chang,J. Moodera, Fabrication andanalysis o Fe/MgO/Silicontunneling emitter bipolartransistors, submitted toJournal o Applied Physics

[3] S. Datta and B. Das, Electronicanalog o the electro-opticmodulator, Appl. Phys. Lett.,vol. 56, pp. 665-668, 1990



ElEctronic DEvicEs

MAtEriAls

A Gan/Gan na w e HEMtM. Azize, T. PalaciosSponsorship: ONR

The high-frequency performance of AlxGa1xN/GaNhigh-electron-mobility transistors (HEMTs) has rapidlyincreased in recent years. Transistors with current gaincut-off frequencies (f T) above 160 GHz and power gaincut-off frequencies (f max) of more than 200 GHz have beenreported [1], [2], which enables the use of these devicesin power ampli ers for mm-wave applications. In spiteof these excellent results, the frequency performance of these devices is still far from its theoretically limit. Accessresistances as well as short channel effects are currentlylimiting this performance. In this project, we aredeveloping nanowire-based nitride HEMTs to overcomethese limitations and to explore the maximum frequencyof nitride devices [3].Our work is based on the top-down fabrication of GaN nanowires on AlGaN/GaN structures grown bymetallorganic chemical vapor deposition (MOCVD) onSi substrates. E-beam lithography is used to fabricatede ne nanowires with diameters (d) in the 30-200 nmrange. After patterning of the nanowire, the sample isetched in a Cl2-based dry-etching systems. Figure 1 showsa scanning electron micrograph of a typical device with

AlxGa1xN/GaN nanowires fabricated between the drainand source contacts. Preliminary measurements of thesedevices show an important improvement in the contactresistance as the nanowire diameter is decreased downto 50 nm (Figure 2), as well as negligible degradation inthe transport properties. These low-contact resistances,in combination with the high electrostatic integrity andmaterial quality of nanowire structures, are expected torender excellent frequency performance.

FIGURE 1: Scanning electronmicroscopy o AlGaN/GaNnanowires between two ohmiccontacts. The diameter and thepitch o the nanowires are 60 nm

electronic devices in mtl annual report 2009

Documents