Index

o Backgroundo Equalizero Pre-emphasiso Continuous-Time Linear Equalizero Decision Feedback Equalizero Digital Equalizero Adapatationo Case study- LE+DFE- Equalizer+CDR- Digital EQ + ADC

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o Backgroundo Equalizero Pre-emphasiso Continuous-Time Linear Equalizero Decision Feedback Equalizero Digital Equalizero Adapatationo Case study- LE+DFE- Equalizer+CDR- Digital EQ + ADC

Background

o Today’s High-Speed Links- Today’s applications require data to be transmitted in Gbps range,often in “unfriendly” environment

- Channels no longer look idealInter-Symbol Interference(ISI), Reflections and cross-talks

- Needs wide bandwidth for high speed signaling by equalization techniques

- Need more circuits to compensate themEqualizers, redundancy encoders/decoders, etc.

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o Today’s High-Speed Links- Today’s applications require data to be transmitted in Gbps range,often in “unfriendly” environment

- Channels no longer look idealInter-Symbol Interference(ISI), Reflections and cross-talks

- Needs wide bandwidth for high speed signaling by equalization techniques

- Need more circuits to compensate themEqualizers, redundancy encoders/decoders, etc.

Background

o Band-limited Channels- Causes the high-frequency signal content to be attenuated much more

severely than the low-frequency content

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Background

o High-Speed Link Architecture with Equalization- Consists of Serializer/Deserializer, Equalizer, PLL and CDR- Most channels are low pass filter

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Equalizer

o Equalization- Boost high-frequencies relative to lower frequencies

(to perfectly counter the attenuation at each freuency)- Ideal equalizer has a transfer function that is the inverse of the channel

transfer function, making it a high-pass filter- This is expressed mathematically as

Heq(f)=H-1channel(f)

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o Equalization- Boost high-frequencies relative to lower frequencies

(to perfectly counter the attenuation at each freuency)- Ideal equalizer has a transfer function that is the inverse of the channel

transfer function, making it a high-pass filter- This is expressed mathematically as

Heq(f)=H-1channel(f)

Equalizer

o Equalizer Design Tradeoffs

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[1] S. Gondi, “A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications,” ISSCC, 2005

Pre-emphasis

o TX FIR filter pre-distorts transmitted pulse in order to invert channel distortion at the cost of attenuated transmit signal(de-emphasis)

o Use EQ technique at Transmitter sideo Attenuates low-frequencies(de-emphasis)- Need to be careful about output amplitude : limited output power

o Challenge :- EMI problem and How to set EQ weights?(unknown channel loss)

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o TX FIR filter pre-distorts transmitted pulse in order to invert channel distortion at the cost of attenuated transmit signal(de-emphasis)

o Use EQ technique at Transmitter sideo Attenuates low-frequencies(de-emphasis)- Need to be careful about output amplitude : limited output power

o Challenge :- EMI problem and How to set EQ weights?(unknown channel loss)

Pre-emphasis

o Two-Tap FIR Filtero ISI gets reduced by boosting transition bits

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Pre-emphasis

o Transmitter with 4-tap FIR filter

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[2] M. Sorna, “A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision-Feedback Equalization,” ISSCC, 2005

Pre-emphasis

o Implementation- Adds 1-bit delayed to Output driver- Compensation gain is digitally controlled(externally)

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Pre-emphasis

o Implementation- Compensation gain boosts up to 9dB (3-bit digital control externally)

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Continuous-time Linear EQ

o Feed-Forward Equalizer(FFE)- Widen bandwidth(BW) to Nyquist of data rate

with boosting high frequency component

o Challenge : poor SNR property- Causes high frequency noise boosting

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o Feed-Forward Equalizer(FFE)- Widen bandwidth(BW) to Nyquist of data rate

with boosting high frequency component

o Challenge : poor SNR property- Causes high frequency noise boosting

Continuous-time Linear EQ

o Linear RX equalizer- Doesn’t discriminate between signal, noise, and cross-talk- Signal-to-distortion (ISI) ratio is improved- SNR(Signal-to-Noise Ratio) is worse

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Continuous-time Linear EQ

o Input amplifier with RC degeneration can provide frequency peakingwith gain at Nyquist frequency

- Cancel both precursor and long-tail ISI

o Potentially limited by gain-bandwidth of amplifier

o Tune degeneration resistor and capacitor to adjust zero frequency and1st pole which sets peaking and DC gain

o Challenge : - Sensitive to PVT variations and can be hard to tune- Amplifier must be designed for input linear range(Often Tx Equalizer provides some low frequency attenuation)

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o Input amplifier with RC degeneration can provide frequency peakingwith gain at Nyquist frequency

- Cancel both precursor and long-tail ISI

o Potentially limited by gain-bandwidth of amplifier

o Tune degeneration resistor and capacitor to adjust zero frequency and1st pole which sets peaking and DC gain

o Challenge : - Sensitive to PVT variations and can be hard to tune- Amplifier must be designed for input linear range(Often Tx Equalizer provides some low frequency attenuation)

Continuous-time Linear EQ

o RC source degeneration structure has a good linearity

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Continuous-time Linear EQ

o Implementation-(I)- 2nd cascaded capacitance degeneration filter(up to 10dB boosting)- Capacitor value is selected 3-bit digital signal externally

162.4Gbps EQ(10dB), 0.35μm CMOS

Continuous-time Linear EQ

o Implementation-(II)- 3rd cascaded RS degeneration with Negative capacitance(up to 25dB)- Varactor(cap) is controlled by adaptive algorithm

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EQ unit cell- 5Gbps EQ(25dB),- 0.13μm CMOS RF

Decision Feedback EQ

o Non-Linear Equalizer- Just subtract post-cursor ISI- Requires a feed-forward equalizer for precursor ISI

o DFE cancels ISI without amplifying noise or crosstalk- Suitable for noisy backplane

o Error Propagation in DFE- Decision errors at the output of the slicer can cause a corrupted estimateof the post-cursor ISI by the post-cursor equalizer

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o Non-Linear Equalizer- Just subtract post-cursor ISI- Requires a feed-forward equalizer for precursor ISI

o DFE cancels ISI without amplifying noise or crosstalk- Suitable for noisy backplane

o Error Propagation in DFE- Decision errors at the output of the slicer can cause a corrupted estimateof the post-cursor ISI by the post-cursor equalizer

Decision Feedback EQ

o Symbol Response for FFE & DFE

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Decision Feedback EQ

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o Challenge : timing constraint- most difficult for the 1st post cursor- smaller input amplitude(larger tcq @DFF)

o To meet the timing- Lower the data rate(half-rate architecture)- Consume more power- Apply loop-unrolling(more power, area and design complexity)

1UI > tD = tc2q + tmulti + tsum + tsetup

Decision Feedback EQ

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o Make decisions for -/+α and MUX selects correct decisiono Loop-Unrolling(speculation) DFE is preferable for Low-Power design

because No High-Speed Analog Feedback Path

Decision Feedback EQ

o If we don’t compromise speed at all,- Power and area increase exponentially

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[3] Yasuo Hidaka, “A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” ISSCC, 2009

Digital EQ

o A common trend in digital communications has been the increasing useof digital signal processing

o A digital DFE equalizer offers advantages over traditional analog DFEequalizer approaches

- Flexibility of Design- Ease of programmability - Consistency of Performance- Extensibility for different channel characteristics, and robustness to

process variations.- Realizing benefits from advancing process technology- Improved production test and debug diagnostics

o challenge : requires ADC to convert digital domain(large power dissipation, large area, high speed operation)

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o A common trend in digital communications has been the increasing useof digital signal processing

o A digital DFE equalizer offers advantages over traditional analog DFEequalizer approaches

- Flexibility of Design- Ease of programmability - Consistency of Performance- Extensibility for different channel characteristics, and robustness to

process variations.- Realizing benefits from advancing process technology- Improved production test and debug diagnostics

o challenge : requires ADC to convert digital domain(large power dissipation, large area, high speed operation)

Digital EQ

o Digital filters using look-up tables for receive EQ.o All post-cursor ISI can be more efficiently cancelled with DFE

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Adaptation Algorithm

Two basic techniques for setting Equalizer Coefficients

o Set and forget- Based on manual channel measurement- Calculate on basis of a single-bit-response

o Adaptation- Use an optimizing algorithm to find ‘minimum’- Optimize multiple variables at once- Adapt once or continuously adaptive

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Two basic techniques for setting Equalizer Coefficients

o Set and forget- Based on manual channel measurement- Calculate on basis of a single-bit-response

o Adaptation- Use an optimizing algorithm to find ‘minimum’- Optimize multiple variables at once- Adapt once or continuously adaptive

Adaptation Algorithm

o Least Mean Square(LMS) Algorithm- Maximizes Vertical Eye opening- Minimizes ξ=E[e2] at center of eye

o Jitter Measurement(Zero-Forcing) Algorithm- Maximizes Horizontal Eye opening- Minimize ISI at the zero crossings- Minimizes ζ=E[e2] at zero crossings

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o Least Mean Square(LMS) Algorithm- Maximizes Vertical Eye opening- Minimizes ξ=E[e2] at center of eye

o Jitter Measurement(Zero-Forcing) Algorithm- Maximizes Horizontal Eye opening- Minimize ISI at the zero crossings- Minimizes ζ=E[e2] at zero crossings

Adaptation Algorithm

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Adaptation Algorithm

o Conventional Continuous-time Equalizer- Only one adaptation loop for high-frequency boosting

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Adaptation Algorithm

o Joint adaptive equalizer- Dual loop architecture to balance low-frequency and high-frequency parts

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[4] J. S. Choi, “A 0.18-um CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain control Method,” JSSC, 2004

Adaptation Algorithm

o Two feedback loops- High-frequency boost control in the equalizer filter- DC level control in the comparator

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[1] S. Gondi, “A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications,” ISSCC, 2005

Adaptation Algorithm

o ISI Detection- Data-dependent ISI detection algorithm- measures minimum bit width when ‘1101’ or ‘0010’ pattern

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[5] Yan-Bin Luo, “A 250Mb/s-to-3.4Gb/s HDMI Receiver with Adaptive Loop Updating Frequencies and an Adaptive Equalizer,” ISSCC, 2009

Case study Io Combined LE + DFE structure- Linear Equalizer(LE) to cancel long-tail ISI- 1-tap speculative DFE to achieve fastest speed

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[3] Yasuo Hidaka, “A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” ISSCC, 2009

LE cancels long-tail ISIexcept 1st post-cursor ISI

1-tap speculative DFEcancels 1st post-cursor ISI

Case study Io Advantages- Fastest achievable speed- Low power and small area- High capability of loss compensation- Low noise enhancement at high frequency

o challenge- Adaptive control

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o Advantages- Fastest achievable speed- Low power and small area- High capability of loss compensation- Low noise enhancement at high frequency

o challenge- Adaptive control

[3] Yasuo Hidaka, “A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” ISSCC, 2009

Case study IIo Merged Equalizer+CDR architecture- Receiver needs to perform CDR as well as equalization- EQ and CDR output are used for LMS algorithm

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[6] Chih-Fan Liao, “A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR” ISSCC, 2008

Case study IIIo Digital Equalizer with ADC- ADC-based SerDes architecture- Consists of two interleaved ADCs, a 2-tap FFE and a 5-tap DFE- Uses Digital Equalizer scheme(FFE, DFE)

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[7] M. harwood, “A 12.5Gb/s SerDes in 65nm CMOS Using a Baud Rate ADC with Digital RX Equalization and Clock Recovery,” ISSCC, 2007

References[1] S. Gondi, “A 10-Gb/s CMOS Adaptive Equalizer for Backplane

Applications,” IEEE, ISSCC, 2005[2] M. Sorna, “A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision

-Feedback Equalization,” IEEE, ISSCC, 2005[3] Yasuo Hidaka, “A 4-Channel 10.3Gb/s Backplane Transceiver Macro with

35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” IEEE,ISSCC, 2009

[4] J. S. Choi, “A 0.18-um CMOS 3.5-Gb/s Continuous-Time Adaptive CableEqualizer Using Enhanced Low-Frequency Gain control Method,” IEEE,JSSC, 2004

[5] Yan-Bin Luo, “A 250Mb/s-to-3.4Gb/s HDMI Receiver with Adaptive LoopUpdating Frequencies and an Adaptive Equalizer,” IEEE, ISSCC, 2009

[6] Chih-Fan Liao, “A 40Gb/s CMOS Serial-Link Receiver with AdaptiveEqualization and CDR,” IEEE, ISSCC, 2008

[7] M. harwood, “A 12.5Gb/s SerDes in 65nm CMOS Using a Baud Rate ADCwith Digital RX Equalization and Clock Recovery,” IEEE, ISSCC, 2007

[8] Stephen H. hall, Advanced Signal integrity for High-Speed DigitalDesigns, Wiley, 2009 36

[1] S. Gondi, “A 10-Gb/s CMOS Adaptive Equalizer for BackplaneApplications,” IEEE, ISSCC, 2005

[2] M. Sorna, “A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision-Feedback Equalization,” IEEE, ISSCC, 2005

[3] Yasuo Hidaka, “A 4-Channel 10.3Gb/s Backplane Transceiver Macro with35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” IEEE,ISSCC, 2009

[4] J. S. Choi, “A 0.18-um CMOS 3.5-Gb/s Continuous-Time Adaptive CableEqualizer Using Enhanced Low-Frequency Gain control Method,” IEEE,JSSC, 2004

[5] Yan-Bin Luo, “A 250Mb/s-to-3.4Gb/s HDMI Receiver with Adaptive LoopUpdating Frequencies and an Adaptive Equalizer,” IEEE, ISSCC, 2009

[6] Chih-Fan Liao, “A 40Gb/s CMOS Serial-Link Receiver with AdaptiveEqualization and CDR,” IEEE, ISSCC, 2008

[7] M. harwood, “A 12.5Gb/s SerDes in 65nm CMOS Using a Baud Rate ADCwith Digital RX Equalization and Clock Recovery,” IEEE, ISSCC, 2007

[8] Stephen H. hall, Advanced Signal integrity for High-Speed DigitalDesigns, Wiley, 2009