80 IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 2, FEBRUARY 2001

Fabrication of Gate-All-Around Transistors UsingMetal Induced Lateral Crystallization

Victor W. C. Chan and Philip C. H. Chan, Senior Member, IEEE

Abstract—Gate-all-around transistor (GAT) is demonstrated.The device can be fabricated on either a bulk silicon wafer or onthe top of any device layers. The fabrication process used a newtechnique called metal-induced-lateral-crystallization (MILC) torecrystallize the amorphous silicon to form large silicon grain inthe active area. Using this technique, the transistor performanceis comparable to a SOI MOSFET. Compared with the single-gatethin film transistor (SGT) and solid phase crystallization (SPC)device, MILC GAT has lower subthreshold slope, lower thresholdvoltage, higher transconductance and nearly double drive current.The impact of short channel length was investigated.

Index Terms—Double gate transistors, gate-all-around transis-tors, metal induced lateral crystallization, SOI, thin-film transis-tors.

I. INTRODUCTION

DOUBLE gate transistor built on a fully depleted siliconon insulator (SOI) wafer has two gate electrodes, which

jointly control the device channel. There is no body effect andthus it reduces short-channel effect. Gate-all-around transistors(GAT) are similar to the double gate transistors, except that thetwo edges of the channel are also controlled by the gate. Bothdevices have been predicted to continue the improvement in de-vice performance down to 0.02m gate length [1], [2]. An ad-ditional advantage of the GATs is that it eliminates the narrowwidth effect of SOI transistor [3].

In the past, many authors have reported double gate devicesand GATs. One method used wafer bonding and polishingtechnique, which involved crucial alignment of two wafers [4],[5]. Another method involved epitaxial growth to construct thechannel [6], [7]. The method of cavity etch on the buried oxidefor the bottom gate was possible and was difficult to controlthe bottom gate length [2]. The application of GAT in SRAMsthrough the use of a dummy nitride pattern has been reported [8],[9], however, the devices could not provide large drive currentand the subthreshold swing was not satisfactory. This was due tothe imperfect crystallization of the amorphous silicon channel.

In this letter, we have successfully fabricated the GAT device.The device can either be fabricated on a bulk wafer or on the topof any device layers. This method uses a dummy nitride patternand forms an air bridge-like channel structure. A new techniquecalledmetal-induced-lateral-crystallization(MILC) techniqueis used to recrystallize the deposited amorphous silicon to form

Manuscript received August 8, 2000. This work was supported by RGC Ear-marked Grant HKUST 6025/97E and CMI99/00.EG05. The review of this letterwas arranged by Editor K. De Meyer.

The authors are with the Department of Electrical and Electronic Depart-ment, Hong Kong University of Science and Technology, Kowloon, Hong Kong,S.A.R. (e-mail: eepchan@ust.hk).

Publisher Item Identifier S 0741-3106(01)01201-0.

large polysilicon grains in the channel region at elevated tem-perature [10]. Conventional fabrication process is used. Withthe recrystallized silicon film and gate-all-around structure, thedevice has good characteristics compared to the single gate tran-sistor (SGT).

II. FABRICATION PROCESS

A 3000 Å thermal oxide was grown on the bulk silicon sub-strate and served as the buried oxide. A dummy gate was formedby the deposition of 2500 Å silicon nitride film and patterned.2000 Å oxide was deposited and etched to form an oxide spacer[Fig. 1(a)]. Subsequently, a layer of 1000 Å amorphous siliconfilm was deposited. MILC was applied as follows [10]. After 50Å of nickel was selectively deposited, lateral crystallization wascarriedoutat560Cfor50h inN ambient.The remainingnickelwas removed. The recrystallization annealing was performed at900 C for an hour to enhance the grain size. A polysilicon filmwith grain sizes over 80m was formed. This large grain polysil-icon film was then patterned by e-beam lithography and formedthedevicechannel [Fig.1(b)]. Ifnograinboundaryoccurredinthechannel, the device performance of this device should be similarto a single-crystalline device. On the other hand, if the device islocatedonsmall grainpolysilicon filmandgrainboundaryexists,the device has poor subthreshold slope, lower carrier mobility,higher and lower drive current.

The remaining silicon nitride was completely removed byhot phosphoric acid. A hollow was formed underneath thesilicon channel [Fig. 1(c)]. In the fabrication process, therewas a 200 Å pad oxide on both sides of the silicon layer. Thus,the silicon layer will be protected and not attacked by the acid.After adjustment implantation, a 120 Å thick gate oxide wasthermally grown under 850C. 2500 Å doped polysilicon wasdeposited and patterned to form the gate electrodes. The topand bottom gates were self-connected during the polysilicondeposition [Fig. 1(d)]. The remaining steps were source/drainimplantation, dopant activation annealing, contact opening andmetallization. Fig. 2 shows the cross-sectional SEM photographof the device. The top gate may be misalign with respect to thebottom gate since the first is controlled by the gate mask and thesecond by the dummy nitride mask. This may cause extra gate tosource/drain overlap capacitance as well as loss of current drive[1]. The misalignment should be less than 10% with respect tothe channel length.

For comparison, conventional device was also fabricatedusing solid phase crystallization (SPC). The fabrication processwas similar to that of MILC device, except that no nickel stripwas placed prior to the crystallization process. The comparison

0741–3106/01$10.00 © 2001 IEEE

CHAN AND CHAN: FABRICATION OF GATE-ALL-AROUND TRANSISTORSN 81

Fig. 1. Schematic diagram of the process flow. (a) After thermal growth ofthe buried oxide, dummy nitride gate pattern and the corresponding oxidespacer formation. (b) After a-Si deposition, MILC process and the activearea definition. (c) After completely removal of the dummy nitride bar. (d)Complete gate-all-around (GAT) structure after gate oxide growth, polysilicondeposition, gate definition and the source/drain implantation.

between the MILC and SPC devices shows the importance ofnickel seed during the recrystallization process. Meng reportedthat [11], from the SIMS analysis, nickel concentration wasrelatively low within the MILC region. It was higher in thenickel seed region and the MILC front.

III. D EVICE CHARACTERISTICS ANDDISCUSSION

The devices were built on thin silicon film fabricated withoutsilicide process and the source/drain doping process was not op-

Fig. 2. SEM micrograph of the GAT.

Fig. 3. NMOS and PMOSI –V curves of MILC GAT and SGT, with SPCand convention SOI devices for comparison.L =W = 0:55=0:47 �m.

timized. The total parasitic resistance was expected to be high.To make a fair comparison, all the drain current measurementswere calibrated with the consideration of the high sheet resis-tance from the source/drain diffusion regions.

Fig. 3 shows the subthreshold characteristics of the newstructure. The new devices comprise two new technolo-gies, namely the silicon recrystallization method and thegate-all-around structure. The device characteristics of theMILC gate-all-around transistors (GAT) were compared to theMILC single-gate transistors (SGT), SPC GAT and SPC SGT,and the conventional SOI devices. All the devices have commonchannel length of 0.55 m gate width of 0.47 m,120 Åthick gate oxide and 800 Å channel thickness. Firstly, itis observed that the MILC SGTs have comparable performanceas the conventional SOI devices. The derived results showthat, the MILC devices have slightly lower mobility than theSOI devices but still in the same order. This may be due to thepresence of grain boundary in the device channel. In addition,compared with the SPC devices, the MILC devices (both GATsand SGTs) have steeper subthreshold slope, lower thresholdvoltage, higher drive current and higher field-effect mobility.This suggests that the channel of the MILC device located ina single crystal region without any grain boundary. When the

82 IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 2, FEBRUARY 2001

Fig. 4. Saturation current versus effective channel length atjV j = jV j+2:5V for (a) NMOS and (b) PMOS MILC devices, withW = 0:48 �m.

Fig. 5. Threshold voltage versus effective channel length atjV j = 0:05 Vfor (a) NMOS and (b) PMOS MILC devices withW = 0:48 �m.

device is scaled down, the channel region to cover multiplegrains decreases and results in better device performance andhigher uniformity. Furthermore, compared to SGT, GAT devicehas almost double drive current, steeper subthreshold slopeand lower threshold voltage. Subthreshold swing of 68 mV/decand current on/off ratio of 210 were achieved. Hence, weconclude that the new recrystallization techniques providehigh quality silicon film similar to the SOI, and the GAT hassuperior performance to the SGT.

Fig. 4 shows the drive current of various devices atV. The GATs have saturation current around 1.7 to 2.1

times higher than that of SGTs. GAT has two inversion channels.The device channel is 800 Å thickness. The GAT channel is fullydepleted and the inversion charge centroid is far away from theoxide-silicon interface. This leads to reduced scattering and lessinfluence of surface roughness, which result in higher carrier

mobility. Hence, the GAT has almost double transconductancethan that of the SGT. In Fig. 5, it is observed that the GATshave threshold voltages which are from 0.1 to 0.4 V lower thanthe MILC SGTs. When the channel length is scaled down, thethreshold voltage variation of the GATs becomes smaller. Forthe SGTs, when the drain voltage becomes higher, the electricfield induces more inversion charge at the back interface and thisleads to threshold voltage shift. On the other hand, for the GATs,both the top and bottom interface charges are fully controlled bythe gate and hence suppress this degradation.

IV. CONCLUSION

GATs have been demonstrated. Using this method, the GATcan be fabricated from either on bulk wafer or on the top of anydevice layers. The conventional fabrication process and MILCare used. From the device characteristics, the MILC devicehas similar performance as the SOI device. Compared with thesingle gate transistor, the GAT provides better subthresholdslope, lower threshold voltage and larger drive current. Inaddition, it has better short channel characteristics. It is suitablefor high performance, low voltage, low power and memoryapplications.

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