final lecture review step 7 deliverables final course information

Final Lecture

Review Step 7 Deliverables

Final Course Information

ECE Lab IV Lecture 9 2

Quiz 2 Opens Friday Aug. 22nd at 9am Closes Friday Aug 29 at 5pm Covers topics addressed in all parts of

the voice recorder design including simulation, control circuitry, and specific chip performance

(Hint, be sure you understand what it means to be edge triggered)


Extended Lab Hours Eric will be available for extended lab hours starting

this week. Week 9 and 10

Monday 12pm-4pm Wednesday 11am-5pm Friday 9am-4pm

Finals Week Tuesday 12pm-4pm Wednesday 12pm-4pm

Unless discussed with me otherwise all lab reports and disassembled boards are due Wednesday September 3rd by 4pm!!!!


Step 7 Goals Control the ADC Modify the RAM control according to the

chosen timing strategy Add the RAM chip to the circuit Optimize performance Test the circuit


ADC ControlADC0804 Pins

CS = Chip SelectRD = ReadWR = WriteINTR = Interrupt

1

3

5

7

9

2

4

6

8

10 11

13

15

17

19

12

14

16

18

20CS

RD

WR

CLK IN

INTR

DB0

DB7

•

•

•

•


ADC ControlFree-Running Circuit

Rising transition on WR begins the conversion

100 ns min


ADC ControlFree-Running Circuit

RD must be low for data to appear at outputs. When RD is high, outputs are Hi-Z.


ADC Control Hint

To avoid designing and wiring a lot of new logic, use the outputs and unused gates of your current RAM control as much as possible

Verify ADC control on the logic analyzer BEFORE adding RAM chip to circuit

The first task is to make sure the 555 clock and the ADC internal clock are coordinated.

If WE_ never rises, no conversions will occur.

If there are no conversions, INTR_ will stay high.

There should be no pulses on WR_ in READ mode.

When RD_ is high the ADC output is high-impedance.

OE_ is low in READ mode.


Optimizing the Circuit Goal: Record audio to your specs Storage is limited

131,072 sites in RAM (217) 65535 sites in RAM (216)

Acquisition speed is limited ADC internal clock must make about 72 cycles per

conversion High speed = high bandwidth High speed = short capture time


Optimize the Circuit You have a design goal for how you

want your circuit to function If necessary to meet this goal:

Adjust the ADC internal clock frequency Adjust the on-board (555) clock


Test the Circuit Display analog input (sine or ramp) and

analog output on scope During the RAM WRITE cycle, the data on

the bus comes from the ADC The DAC automatically converts it back to

analog. At low frequencies, the DAC output should

be identical to the analog input


Test the Circuit Display analog input (sine or ramp) and

analog output on scope During the RAM READ cycle, the data on

the bus comes from the RAM The DAC automatically converts it back to

analog The DAC output should be identical to the

analog input of the previous acquisition cycle


Test the Circuit Note the length of the acquisition (WRITE)

cycle. Does it equal 131,072 times the period of the on-board clock?

Note the length of the READ cycle. Does it equal 131,072 times the period of the on-board clock?

If you want to see if the circuit is really working, pull the RAM chip Your output should be 0 during the READ cycle


Experimental Results


Deliverables Test 1 - Bandwidth

Analog in, analog out Determine failure frequency

A = (Goal - Measured)/Goal A ≤ 0 (measured exceeds goal) 20 pts 0.95 ≤ A < 1 18 pts 0.90 ≤ A < 0.95 16 pts A < 0.90 14 pts


Deliverables Test 2 - Address Generator

Working 17 bits 20 pts Working 17 bits, novel design 22 pts Working 16 bits 16 pts < 16 bits 10 pts


Deliverables Test 3 - RAM/ADC Control

Working and in sync 20 pts Working not in sync 15 pts Not working 10 pts


Deliverables Test 4 - Timing

ADC internal clock period INTR period 555 timer period Record time Playback time


Deliverables Test 4 - Timing

For record time: R = (Calculated - Measured)/Calculated If R ≥ 0.9 10 pts If R < 0.9 5 pts


Deliverables Test 5 - Playback

Is DAC output from stored data? Yes 20 pts No 10 pts


Deliverables Test 6 - Construction

Has the circuit been constructed neatly and with a reasonable floorplan?

0 to 10 pts


Deliverables Test 7 - Understanding of Circuit

Each group member will be asked questions to show that the entire group understands circuit operation and design choices and criteria


Deliverables Test 8 - Return Board

Has the circuit been returned in good condition?

Good Condition multiplier = 1.0 Not Returnedmultiplier = 0.0


Deliverables - Final Lab Report Write up your ADC control design:

Design criteria what were the specs you wanted sketch the desired output waveforms

Sketch the ADC control schematic Show any equations used, and define

terms if necessary


Deliverables-Final Lab Report Write up your ADC control design:

Discuss what changes were made to the circuit to optimize performance

How effective were they? Document the performance change


Deliverables - Final Lab Report Have eric verify functionality and quality

of work Comment on your observations and

provide conclusions on the entire experiment

Any improvements to this Step? Any improvement to the lab course?

final lecture review step 7 deliverables final course information

Documents

circuitece lab iv lecture

interruptece lab iv

clockece lab iv lecture

triggeredece lab iv

analog inputece lab

lab reports

extended lab hourseric

adc output