Flip-Flopovi i memorije

1

0

D

LE

QLE

LELE

LE

DQ Q

Q

Standard sequential circuits – D latch

LE = 1

D Q

Q

LE = 0

D Q

Q

D

LE

Q

S Q

R QS

QR

Q

Standard sequential circuits – SR latch

R S Q[n+1]

0 0 Q[n]

0 1 1

1 0 0

1 1 ?

f

S

f

R

Q Q

Q

D

Cp

D Q

QCp

D Q

LE

D Q

LE Q

Standard sequential circuits – D FF

D Cp Q[n+1]

x 0 Q[n]

0 0→1 0

1 0→1 1

x 1 Q[n]

D FF master-slave operation

Cp = 1

D

Cp = 0

Q

D Q

D

Cp

Q

D FF with preset and clear D Q

Q

S

R

Registers

• n-bit register is a set of n D flip-flops,

one per bit

• Data inputs are D0, D1,…,Dn-1

• Data outputs are Q0, Q1,…,Qn-1

• Common Clock for all flip-flops

• Optional preset or clear

D Q

Cp

D Q

Cp

D Q

Cp

...

Dn-1

D0

D1

CLK

Q1

Q0

CLK

D0D1...

D7

Q0

Q1

Q7

...

Qn-1

8-bit

register

n bit latch

• n-bit latch is a set of n single bit

latches, one per bit

• Data inputs are D0, D1,…,Dn-1

• Data outputs are Q0, Q1,…,Qn-1

• Common LE for all latches

• Optional preset or clear

ROM 4 6bit

2:4

DEC

A0A1

Y0Y1Y2Y3Y4Y5

Word 0: 010101

Word 1: 011001

Word 2: 100101

Word 3: 101010

Source Drain

GateFloating gate

tox

tox

Substraten+n+ p

5VDDV

2.5VTV

5VDDV

5VTV

DS

20 V

20 V

DS

0 V

0 V10V5V -5 V

DS

5 V

5 V-2.5 V

Avalanche injection.

Removing

programming voltage

leaves charges

trapped

Programmingresults in

higher VT

- - - - - - - -

- -

- -

• 8-transistor cell

– Bit_i is the data bus

– Sj is the word line

• Bus drivers

– Sense Amplifier (inverter with high gain) used for fast switching

– Make sure inverters in cell are weaker than the combination of “write buffer” and pass transistor

Rd/WR

Sj

Sj

biti biti

Memory Cell: Static RAM (8 transistors)

Memory Cell: Static RAM (6 transistors)

• 6-transistor cell

– Must adjust inverters for input

coming through

n-type pass gate

• Bus drivers

– Must adjust senseAmp for input

coming through

n-type pass gate

– Harder to drive 1 than 0 through

write buffer (high resistance via n-

transistor)

– One side is sending 0 anyway (bit

or bit’)

written correctly

Rd/WR

Sj (WL)

biti (BL) biti

6-Transistor Memory Array

• 8 words deep RAM,

2 bits wide words

• To write to word j:

– Set Sj=1, all other S lines

to 0

– Send data on the global

bit0, bit0’, bit1, bit1’

• To read word k:

– Set Sk=1, all other S

lines to 0

– Sense data on bit0 and

bit1. Rd/WR

bit1 bit1

Rd/WR

bit0 bit0

S0

S1

S7

bit1 bit1 bit0 bit0

Dynamic RAM 4-Transistor Cell

• 4-transistor cell

• Dynamic charge

storage must be

refreshed

• Dedicated busses for

reading and writing

WR

data in data out

Rd

Dynamic RAM 3-Transistor Cell

• 3-transistor cell

– No p-type transistors

yield a very compact

layout for cell

– No Vdd connection

– Sense Amplifier must

be able to quickly

detect dropping

voltage

WR

data in data out

Rd

precharge

Dynamic RAM 1-Transistor Cell

• 1-transistor cell

– Storage capacitor is source of cell

transistor

– Special processing steps to make

the storage capacitor large

– Charge sharing with bus

capacitance

(Ccell << Cbus)

– Extra demand on sense amplifier to

detect small changes

– Destructive read (must write

immediately)

Si (WL)

Storage capacitor

Precharge to middle voltage level

Bi

Komparatori

V1

FREQ = 500kVAMPL = 30VOFF = 0

0

D1 D2

R1

300k

V2

5Vdc

0

R2

100k

+

-

V+

V-

OUT

U1A

TL082

V

V

T i m e

4 0 u s 4 1 u s 4 2 u s 4 3 u s 4 4 u s 4 5 u s 4 6 u s 4 7 u s 4 8 u s 4 9 u s 5 0 u s

V ( R 2 : 1 ) V ( R 1 : 1 )

- 4 0 V

0 V

4 0 V

S E L > >

I ( V 2 )

- 4 0 m A

0 A

4 0 m A

8 0 m A

Diferencijalni komparator

• Po strukturi pojačavač

• Identičan simbol kao kod operacionog pojačavača

• sličan raspored pinova na integrisanom kolu kao

kod operacionog pojačavača

• Interna struktura različita

I1

Vcc

-Vee

Vout

+

-

V1

FREQ = 500kVAMPL = 30VOFF = 0

0

D1 D2

R1

300k

V2

5Vdc

0R2

100k

OUT7

+2

-3

G1

V+

8

V-4

B/S6B

5

U1

LM311

T i m e

4 0 u s 4 1 u s 4 2 u s 4 3 u s 4 4 u s 4 5 u s 4 6 u s 4 7 u s 4 8 u s 4 9 u s 5 0 u s

V ( R 2 : 2 ) V ( R 1 : 1 )

- 4 0 V

0 V

4 0 V

I ( V 2 )

- 1 . 0 m A

- 0 . 9 m A

- 0 . 8 m A

- 0 . 7 m A

S E L > >

V1

FREQ = 500kVAMPL = 30VOFF = 0

0

D1 D2

R1

300k

V2

5Vdc

0R2

100k

OUT7

+2

-3

G1

V+8

V-4

B/S6B

5

U1

LM311

R3

100C1100n

0

T i m e

4 0 u s 4 1 u s 4 2 u s 4 3 u s 4 4 u s 4 5 u s 4 6 u s 4 7 u s 4 8 u s 4 9 u s 5 0 u s

V ( R 2 : 2 ) V ( R 1 : 1 ) I ( V 2 )

- 4 0

0

4 0

I ( V 2 )

- 1 . 0 m A

- 0 . 5 m A

0 A

S E L > >

Operacioni pojačavač

• Ne radi dobro funkciju

komparatora

• Radi dobro sa

negativnom

povratnom spregom

Komparator

Ne radi dobro funkciju

pojačavača

Ne radi dobro sa

negativnom povratnom

spregom

Poređenje ima smisla za isti red veličine cene

Komparatori sa histerezisom

Šmitova kola

T i m e

0 s 0 . 1 m s 0 . 2 m s 0 . 3 m s 0 . 4 m s 0 . 5 m s 0 . 6 m s 0 . 7 m s 0 . 8 m s 0 . 9 m s 1 . 0 m s

V ( U 3 : O U T ) V ( V 5 : + )

- 2 0 V

- 1 5 V

- 1 0 V

- 5 V

0 V

5 V

1 0 V

T i m e

1 2 0 u s 1 3 0 u s 1 4 0 u s 1 5 0 u s 1 6 0 u s 1 7 0 u s 1 8 0 u s 1 9 0 u s 2 0 0 u s

V ( U 3 : O U T ) V ( V 5 : + )

0 V

2 . 0 V

4 . 0 V

6 . 0 V

T i m e

1 4 5 . 0 0 u s 1 4 5 . 5 0 u s 1 4 6 . 0 0 u s 1 4 6 . 5 0 u s 1 4 7 . 0 0 u s 1 4 7 . 5 0 u s 1 4 8 . 0 0 u s 1 4 8 . 5 0 u s1 4 4 . 5 6 u s

V ( U 3 : O U T ) V ( V 5 : + )

0 V

2 . 0 V

4 . 0 V

6 . 0 V

OUT7

+2

-3

G1

V+8

V-4

B/S6B

5U3

LM311

R5

1k

R6

100k

V3

FREQ = 1kVAMPL = 10VOFF = -8

0

D6 D7

R3

300k

V4

5Vdc

0

R4

100k

V5

FREQ = 5MegVAMPL = 0.1

VOFF = 0

T i m e

1 4 0 . 0 0 u s 1 4 2 . 0 0 u s 1 4 4 . 0 0 u s 1 4 6 . 0 0 u s 1 4 8 . 0 0 u s1 3 8 . 1 7 u s 1 4 9 . 8 2 u s

V ( U 3 : O U T ) V ( V 5 : + )

- 1 . 0 V

0 V

1 . 0 V

2 . 0 V

3 . 0 V

74HC14