fowlp & embedded die packages - chip ... - chip scale · pdf filefowlp & embedded die...

© 2012

Copyrights © Yole Développement SA. All rights reserved.

Texas

Instruments

FOWLP & Embedded die Packages

Embedded wafer-level-package activity is expected to pick-up by 2015

above $200M overall driven by major wireless chip players worldwide

Nokia

STATs ChipPAC

AT&S Infineon

© 2012 • 2


– Equt & Material Tool-Box for Embedded die . 129

• Technology flavors for embedded package

• Chip first versus chip last?

• Single die embedding versus SiP module?

• Challenges related to yield & supply chain

– Cost structure for Embedded package

manufacturing ………………………………….... 134

• Comparison with competitive package alternative

that Embedded die technology is looking for direct

replacement (QFN, BGA, WLCSP, SOT, PoP…)

• Cost structure target of Embedded die for different

application cases (RFID, IPD, Power MOSFET /

IGBT, DC/DC converters, PMU, Wireless

Connectivity ICs, Digital Baseband, Memories, etc

…)

– Conclusion on “sweets spots” for the

introduction of Embedded die technology in the

short / medium / long term ……………………. 138

Table of Content (1/2)

• Scope of the Report & Definitions …...……. 4

• Executive Summary ………………………… 11

1) Embedded die in substrates of active ICs &

passive components ………………….……. 48

– Motivations and Drivers ………………... 49

– Application focus for Embedded die package

commercialization …………………..…... 64

• Cell-phone & Consumer applications

• Automotive applications

• Medical applications

– 2010-2020 market forecasts for Embedded

packages ………………………………….... 91

• In Package shipments (M units)

• In Packaging revenues ($M)

– Supply chain emerging for embedded dies

………………………………….…………….. 98

• Players and position in the electronic value

chain

• Who is the most aggressive in

commercialization?

• Who is doing what: partnerships identified

FCI NXP

© 2012 • 3


– FOWLP patent activity summary …... 233

– Cost structure for FOWLP ………..…. 265

• Competitive package alternative that FOWLP

technology is looking for direct replacement

• Cost structure for FOWLP by application

– Evolution to Panel-scale-packaging .. 252

• Conclusion & Perspectives ….………… 281

• Appendix ……....…………….…..….…… 287 – Yole Developpement company

presentation & services

Table of Content (2/2)

2) Fan-Out WLP technology development … 140

– Motivations and market drivers …………... 144

• Form factor, Cost and electrical performance

• Thermal performance of FOWLP package

compared to FC-BGA package solution

– Supply chain emerging for FOWLP ……… 162

• Players and position in the electronic value chain

• Who is the most aggressive in commercialization?

• Who is doing what: partnerships identified

– 2010-2020 market forecasts for FOWLP type of

packages ……………………………………... 174

• In Package shipments (M units)

• In epoxy wafer production (wspy eq.)

• In Packaging revenues ($M)

– FOWLP technologies & challenges …….. 202

• Who owns the IP in this space?

• 1st generation versus 2nd generation FOWLP

• “Passive integration with FOWLP technologies

– Equipment & Materials for FOWLP ............ 213

• Challenges in new material selection and missing

equipment

• Technology roadmap for FOWLP development

– 2.5D integration trends based on FOWLP and

silicon / glass interposer mix ……….……. 227

StatsChipPAC

© 2012 • 4


FOCUS of this report update

Scope of the Report

PANEL / Wafer-Scale-Packaging Platforms

Wafer-Level Electrical Redistribution

Flip-chip & Wafer-Level Stacking / Integration

WL CSP ‘Fan-in’

FOWLP ‘Fan-out’

Glass / Silicon

Flip-chip wafer bumping

on BGA

3D IC

& TSV

Embedded die in PCB / laminate

Wafer-Level Interface / Encapsulation

3D WLP For MEMS & sensors

(also called 3D SiP sometimes)

LED & Sensors

WLOptics 2.5D

interposers

• Wafer-level-packaging encompass multiple different technology platform flavors

but leverage similar type of process manufacturing know-how

© 2012 • 5


Definitions

• Embedded Packages refers to different concepts, IP, manufacturing infrastructures

and related technologies. However, it is still possible to distinguish 2 main categories

of embedded packages:

based on a Molded Wafer infrastructure based on a PCB / PWB substrate infrastructure

Embedded

Wafer-Level-Packages

Hidden die

eWLB

EOMIN Chip first

ECP – Embedded Component Packaging

IMB

iQFN

Embedded Active Module

EMBIDS / EDC

Wafer-Level Ball Grid Array

UTCP

NANIUM StatsChipPAC

Imbera

© 2012 • 6


Objectives of the Report

• This is the second report update on Embedded Wafer-Level-Packaging

technologies and markets from Yole Developpement

• The objectives of this first report are the following:

– Analyze both FOWLP and Embedded die package technologies

– Key market drivers, benefits and challenges by application

– Market trends & figures with detailed breakdown by application

– Technology roadmap and description of the complete manufacturing tool-box

for embedded wafer-level-packaging:

o Key equipment: for 200mm / 300mm / Panel manufacturing

o Specific material selection coming from both FE / BE / PCB / LCD areas

– Analysis of several embedded package target prices for a few key applications

– Supply chain perspectives, key players and emerging infrastructure for

embedded wafer-level-packaging

o Analysis of the rationales behind the different possibilities of FOWLP and embedded

die package implementation (chip first / chip last, single die / multi-die / SiP / PoP

module, etc …)

© 2012 • 7


Who should be Interested in this Report?

• Integrated semiconductor Device

Manufacturers and fabless IC companies

– Benchmark the industrialization status of

embedded packaging technologies within the

industry

– Identify possible partnerships or second

source packaging subcontractors for your

forthcoming developments

• Assembly and Test Service companies

– Get the list of the main companies interested

in Embedded WLP

– Screen possible new applications and

technologies to support diversification

strategy with embedded packaging platform

• Equipment and Material suppliers

– Understand the differentiated value of your

products and technologies in this emerging

but fast growing market

– Identify new business opportunities and

prospects

• Electronic module makers and Original

Equipment Makers

– Evaluate the availability and benefits of using

embedded package components in your end

system

– Monitor different embedded WLP suppliers

to adjust your sourcing strategy

• PCB and IC substrate manufacturers

– Monitor the evolution of IC packaging,

assembly and test, especially linked to

emerging chip embedding

– PCB-based technologies, FOWLP, IPD and

3D interposers

© 2012 • 8


Companies Cited in this Report

3D-Plus, ADL Engineering, ADTEC Engineering, Amkor, ams, Analog

Devices, AT&S, Aptos, Asahi Glass, ASE, ASM, Atotech, Broadcom,

Bosch, Camtek, Casio Micronics, CIRETEC, CMK, Compass

Technology, CSR, Datacon, Daeduck, Denso, Dialog Semiconductor,

Dow Corning, DuPont Electronics, Dyconex, Epic, Epcos TDK,

EVGroup, Fico Molding, Flip-chip International, Fraunhofer-IZM,

Freescale, Fujitsu, HD Microsystems, HEICO, SK Hynix, Ibiden,

Imbera, IME, IMEC, Infineon, Invensas, IPDiA, ITRI, King Dragon

International, KYEC, Leti, Lintec, LG Electronic, Micron, MicroChem,

Mitsui, Murata, Nagase ChemteX, NANIUM, NEC Electronics, Nitto

Denko, Nokia, NSC, NXP, OptoPac Oki Electric, ORC, Panasonic,

PPT, Qualcomm, Renesas, Rohm & Hass, Rudolph technologies,

Samsung, SEMCO, Shinko Electric, SPIL, STATS ChipPAC, ST-

Ericsson, STMicroelectronics, SPTS, SMIC, Shin-Etsu, SÜSS

Microtec, Taiyo Yuden, TDK, Tessera, Texas Instruments, tok, Tong

Hsing, Toray chemical, Toray Engineering, Toshiba, Towa, Triquint,

UMTC, Unimicron, Unovis, UTAC, Vertical Circuits, Wolfson

Microelectronics, Yamada and more…

© 2012 • 9


About the authors of this report

Jerome Baron – Jerome is the business unit

manager of the semiconductor

packaging market research at

Yole Developpement. He has

been following the 3D packaging

market evolution since its early

beginnings at the device,

equipment and material levels.

He was granted a Master of

Science degree from INSA-Lyon

in France as well as a Master of

Research from INL – Lyon

Institute of Nanotechnology

Contact: [email protected]

Lionel Cadix – Lionel joined Yole after the

completion of several projects

linked to the

characterization and modeling of

high density TSV and 3DIC chip

stacking in collaboration

with CEA-Leti and

STMicroelectronics during his

PhD. He is author of several

publications and 8 patents in

the field of 3D Integration Contact: [email protected]

© 2012 • 10


Concepts of FOWLP / Embedded di in package

• Two types of Embedded Wafer-level-packages are emerging

– FOWLP is based on a reconfigured molded wafer infrastructure

– Embedded die in package is based on a PCB type of Panel infrastructure

FOWLP 1st generation

Embedded die Single chip

Embedded SiP

Embedded PoP

FO MCP

FO SiP

FO PoP

Embedded MCP

Courtesy of AT&S

AT&S

NANIUM

© 2012 • 11


Chip Embedding / Fan-Out WLP Geometry definitions

• Shift in manufacturing technologies is expected – Geometries of the two emerging packaging technologies will shrink with time as to allow for higher

routing density, highly integrated passive inductors and baluns, and integration of ICs with no prior

RDL on the device wafer

– There is a move (at least for fan-out WLP) from currently used mask aligners to front-end steppers to

support this reduction of the feature sizes

Chip embedding

FOWLP

1st generation

(up to 2012)

2nd generation

(2012-2014)

3rd generation

(2014-2020)

spacing

width Line Spacing / Width (µm)

40/40 25/25 15/15

20/20 10/10 5/5

Courtesy of AT&S

Courtesy of NANIUM

© 2012 • 12


FOWLP / Embedded Die Packaging Roadmap

FOWLP

WL CSP

FC BGA

WB BGA

MATURE tech EMERGING tech FUTURE tech

(2000 - 2010) (2008 - 2014) (> 2014 - 2018)

FO MCP

FO SiP

FO PoP

Embedded MCP

Embedded PoP

QFN

RF connectivity, PMU, Analog

RF Transceiver, Baseband

PMU

SOT / TSOP

IPD

MOSFET

Digital Baseband SOC

RF Transceiver

NFC / Connectivity SOC

ASIC / DSP / FPGA

Specific Analog IC & Sensors

RFID, thin-film IPD, MOSFET,

IGBT, DC-DC converters, IC drivers,

MEMS & Sensors , RFEM…

Power modules, IPD

protection network modules

Digital / Analog partitioning …

Digital + memory modules,

Analog + Digital + memory

modules, Sensor modules,

Radio FEM module …

Digital + memory modules,

Analog + Digital + memory

modules, Sensor modules …

RF connectivity modules,

Audio modules, Sensor

modules, Radio modules …

Embedded die Micro-SiP module

© 2012 • 13


Narrow commercialization window of present eWLB / FOWLP 1st generation technology

• As of today (2012), the commercialization eWLB / FOWLP 1st generation technology is quite restricted to a quite narrow application window from 40-300 IO pin-counts, 4x4 to 7x7mm2 package body size

– Package / devices below 4x4mm2 and 40 IOs: FOWLP will struggle to compete with Wire-bonded BGA/leadframe, Embedded die package and 3DIC wafer-to-wafer assembly platform An extra niche to be found by developing FO-MCP / SiP platform here

– Package / devices of more than 15x15mm²: flip-chip and 2.5D interposer are the best packaging solutions today new flip-chip and 2.5D version of FOWLP technology will be adapted to compete on cost

– Between 4x4mm2 and 15x15mm²: the solutions are not yet decided and the battle is hard between most every packaging technique and this is where the biggest part of the IC packaging business is in volume!

FO-MCP / SiP (for analog / digital SOC partitioning)

FOWLP (commercialized TODAY)

FO-PoP (for BB/APE)

2.5D FOWLP (for APE / ASIC + memory + analog)

Flip-chip FOWLP (for large die ASIC / FPGA)

I/O#

numbers 4 – 10 IOs 10 – 40 IOs 40 – 300 IOs 300 – 700 IOs 700 – 1000’s IOs

7x7 mm2 4x4 mm2 15x15 mm2 25x25 mm2 2x2 mm2 package

body size Embedded die

3DIC (W2W) FC-CSP / BGA

WB BGA /

QFN / TSOP

Logic n Logic n+1 Logic n+2 Logic n+3

2.5D interposers (C2W)

© 2012 • 14


Packaging Value Chain Comparison* Comparison ratio of the packaging, assembly & test value

Substrate Supplier

PRODUCT

FOWLP

Embedded

die in PCB

FC BGA

PRODUCT

PRODUCT

Wafer Fab (RDL)

Wafer

Bumping Assembly & Test

Wafer Fab + FOWLP

assembly

Wafer

Test +

Final

Test

Substrate Supplier

& Assembly

Wafer Fab (RDL & Cu pad)

Wafer Test

+ Final

Test

20% 25% 10% 45%

85% 15%

55% 30% 15%

Inve

nto

ry

• New shift in the packaging, assembly & test value chains – FOWLP implies a simplification and consolidation of the packaging, assembly & test in a “Mid-end”

type of infrastructure

– Embedded die packaging opens the door to substrate suppliers to realize themselves the whole

packaging, assembly and test on a Panel “PCB based” infrastructure

* Comparison

scenario for the

case of 64 I/Os,

0.4mm pitch IC

© 2012 • 15


Package IC Co-Design is Necessary Before Embedded WLP

SERIAL IC Design Package IC Co-Design

PRODUCT

Manufacturing

Digital IC design

Analog IC design

Tool A

Tool B

Tool C

Tool D

FE / BE Manufacturing

PRODUCT

Digital IC

design

Analog IC

design

Packaging

development

DfM Designed for manufacturing

Infrastructure Common Tool-Box

Packaging design

Substrate

Package outline

FE/BE process

• Package IC co-design drives to silicon die and process optimization, for e.g.

– to avoid RDL at the IC wafer level before the embedded WLP process

– RF chip package co-design is also necessary to integrate to take package parasitics into accounts

© 2012 • 16


Embedded Wafer-Level-Packages Status of commercialization

Embedded die in

package (Single chip modules)

Embedded die

SiP / PoP module

packages

2006 2007 2008 2009 2010 2012 2014 2016 2018

X

X

X

Casio / CMK – Watch module

Murata – Cellular terrestrial digital module

NXP – RFID / IPD modules

IFX / Intel Mobile – Wireless Baseband SOC

X SST – EEPROM memories

X STEricsson – RF Transceivers

X

X

X

X

X

X

X X

X

X

X

X X

X

X

X

X

X

X TI – DC/DC converter

FOWLP 1st generation / single die

FO MCP

FO SiP

FO PoP

Embedded SiP Embedded PoP

2nd generation

FOWLP

StatsChipPAC

Renesas – ASIC

Maxim IC – PMU

Rohm – DC/DC converter

ADI

ams

Infineon

Broadcom – ASIC

X Toshiba – FPGA

X Altera – FPGA

© 2012 • 17


First eWLB Package in High Volume Production!

• First design win for eWLB – Infineon (GE) was the first company

to commercialize its own eWLB

packaging technology in an LGE

cell-phone in early 2009

– ASE, StatsChipPAC have been

qualified as subcontractors

for eWLB manufacturing

– Infineon’s chip is a wireless

baseband SOC

with multiple

integrated functions (GPS, FM radio, BT…)

– Same eWLB

product is now in

production in

some Nokia

handsets

since 2010

First eWLB

package with

Infineon’s

wireless

Baseband SOC

was found in

an LG cell-

phone (Reverse

Engineering

pictures courtesy

of SystemPlus

Consulting and

Binghamton

University )

© 2012 • 18


• Mobile and wireless applications using FO-WLP packaging – LGE was the first OEM to integrate the eWLB to the wireless baseband in the following models

• PMB8810 phone, T310 phone, T300 phone, GD350 phone, GB220 phone, GB230 phone, GS170 phone, GU230 phones

– We can also find eWLB in Samsung cell phones (baseband modem)

• S3350 phone, Galaxy Tab tablet, Galaxy S phones

– Some Nokia’s phones use eWLB for the baseband modem and RF tranceiver

• S30 series platform (2010 phone version), S40 series platform (2010 phone version), 1 smart-phone line (to be identified)

• Extension of the technology platform to a wider field of application areas is in

preparation – FO-WLP is expected to be integrated as well as some point in the automotive and medical

applications

Current end-products using eWLB / FOWLP

2009 2010 2011

© 2012 • 19

Copyrights © Yole Developpement SA. All rights reserved.

$0M

$100M

$200M

$300M

$400M

$500M

$600M

$700M

2008 2009 2010 2011 2012F 2013F 2014F 2015F 2016F 2017F 2018F 2019F 2020F

TOT FOWLP (M$) $13M $48M $75M $107M $114M $107M $118M $195M $280M $374M $477M $571M $641M

FO

-WL

P R

eve

nu

es (

M $

)

FOWLP activity Revenues (M$) Overall evolution since eWLB technology introduction

Yole Developpement © October 2012

FOWLP activity market evolution & forecast

• After growing fast since Infineon / Intel Mobile’s push for eWLB technology commercialization, the FOWLP

market activity reached the $100M market valuation last year

– This young industry will probably need to wait for 2015 – 2016 time frame to reach the $250M market valuation as the technology

to ramp-up in HVM, the demand moving from IDMs to fab-less wireless IC players (such as Qualcomm, Broadcom, Mediatek,

etc…) and supported by a solid infrastructure and supply-chain of OSATs

CAGR ~ 0% Intel Mobile /

IFX eWLB driven

Transition phase

Ramp-up with fab-less wireless

IC players and wide FOWLP

infrastructure / supply-chain

© 2012 • 20


Optimistic scenario (1/2)

• To bend the rules, we decided in this report to propose an alternative scenario for FOWLP

market evolution

• Indeed, regarding the numerous rumors linked to this space, several feedbacks pushed us

to propose an optimistic forecast model, making the market starting growing fast as soon as

2013

• This enthousiastic scenario would be linked to the following players’ activity

– Spreadtrum (CN)

– Maxim (US)

– ADL (TW)

– Mediatek (TW)

• In this alternative model

– A 30% penetration rate have been

applied for FOWLP as soon as

2013, for existing products already

using this platform

• Digital Baseband Processor

• APE/BB wireless SoC

– Volume production for the other

applications would start 1 year

sooner than in our initial model (for

RF tranceiver, PMU, ASIC,

Touchscreen Controller, RF

Connectivity devices)

0

200

400

600

800

1 000

1 200

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

FO-W

LP R

even

ues

(M

$)

FOWLP Revenues (optimistic scenario) Breakdown by application area (M$)

Medical

Automotive

Industrial

Consumer

Mobile - Wireless

Yole Developpement © October 2012

© 2012 • 21


Optimistic scenario (2/2)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Waf

er c

ou

nt

(12

’’e

q. w

afer

s) M

illio

ns

FOWLP wafer forecast (optimistic scenario) Breakdown by IC type (12’’eq wafers)

DRAM

Touchscreen Controller

RF Connectivity Combo

PMU

NAND Flash Memory

Memory Controller

MEMS & Sensors

NFC

RF Tranceiver

ASIC / FPGA

Audio/Video Codec

Digital Baseband Processor

BB/APE wireless SoC

Yole Developement © October 2012

• According to this model the market would grow at a 30% CAGR on the 2010-2020 time frame,

leading to a ~ $1B market in 2020

• It would lead to nearly 500,000 wafers shipped in 2020 and more than 2.8 billion in 2020

• Now we just have to wait and see if the rumors come true and if the infrastructure of this

young industry will be strong enough to support this fast growing evolution

© 2012 • 22


FOWLP 2011 revenues market shares (in M$)

• NANIUM (Pt) and STATschipPAC (Sg) shares more than 80% of the activity, mainly driven by

Intel Mobile volume demand on eWLB production

– ASE (Tw) is shutting down its 200mm eWLB line. Other OSATs have qualified other FOWLP technologies

such as ADL (Tw), Amkor (Kr) and NEPES (Sg)

– Additional packaging houses are coming on board as well such as TSMC (Tw), SPIL (Tw) and J-Devices (Jp)

STATSChipPAC (Sg) $46M 43%

NANIUM (Pt) $41M 38%

ASE (Tw) $14M 13%

Others * $6M 6%

FOWLP 2011 revenues market shares (in M$) Breakdown between main players

Yole Developpement ©

October 2012

* Others: ADL (Tw),

Amkor (Kr), NEPES (Sg)

TOT

~$107M

© 2012 • 23


PANEL Infrastructure for Embedded Chip Packaging

• Embedded die packaging technology will leverage an entirely new infrastructure

based on large PANEL, low cost PCB manufacturing techniques!

– Typically able to integrate more than 10,000 – 40,000 dies per panel!

AT&S’s first generation production is based on 18x24 sq.

inch panels. 2nd gen on 21x24 sq. inch panels!

Courtesy of AT&S

© 2012 • 24


AT&S step into HVM for Embedded MicroSiP packages

Teardowns courtesy of SystemPlus Consulting

• Texas Instruments (US) is the first customer to qualify into HVM

the embedded die package line of AT&S

– First application is a DC-DC converter MicroSiP™ module:

© 2012 • 25


DNP’s Embedded active & passive substrate in HVM

• DNP (JP) is supplying Sony’s camera module with embededded passive and active

components in HVM since 2010 already

– Auto-focus driver IC and DC-DC converter WLCSP dies are placed within the coreless cavity substrate

Teardowns courtesy of SystemPlus Consulting

http://www.dnp.co.jp/eng/

© 2012 • 26


Embedded die package PANEL infrastructure Roadmap

2010 - 2012 2013 2014 2015 > 2016

POWER & ANALOG small SiP module applications:

- DC/DC converter

- IPD

- AF driver

- Small ASICs

- MOSFET

- IGBT

- RFID

1/4 PANEL

1/2 PANEL

Full

PANEL

4”x20” – 102x508mm /

PCB laminate substrate

8”x20” – 204x508mm /


16”x20” – 400x505mm /


YIELD % to increase

RF & MIXED SIGNAL large SiP module applications :

- PMU / PMIC

- RFEM (SAW, PA, etc…)

- RF connectivity (WLAN/BT/FM)

- Audio/Video Codec

DIGITAL thin PoP module applications

- BB / APE

RF & MIXED SIGNAL SiP module applications :

- PMU / PMIC

- RFEM

- RF connectivity (WLAN/BT/FM)

- Audio/Video Codec

OSAT players driven

Substrate players driven

YIELD % to increase

YIELD % to increase

© 2012 • 27


First Conclusions on Embedded Wafer-Level-Packages

• 1st generation FOWLP and Embedded die packages is a high volume reality and the two

infrastructures are now clearly settled and proven in HVM in each of their very different

application space

– Today, first generations of Embedded die package and FOWLP technologies are not really competing

at all as they are driven by different players and initially target very different applications.

• However, this situation will totally change in the future with “2nd generation” derivatives of

the technologies that are currently under development for future SiP and PoP module

realizations, likely on larger format

– We are likely to be witness to a fascinating battle in the years to come in the 3D Packaging space with

on one hand, embedded die packaging technologies supported by large panel PCB infrastructure and

FOWLP technologies on the other hand, which is looking for moving to larger wafer format, likely

square 300mm PANEL first and possibly later on larger PANEL mixing PCB, semiconductor back-

end, semiconductor WLP and LCD large area processing know-how

© 2012 • 29


Fields of research activity

• Yole Developpement is a market research and strategy consulting company, founded in 1998. We are involved in the following areas:

• Yole Développement has 25 full time analysts, with both technical and marketing/management background and operate worldwide since 1998

MEMS &

Sensors

Photovoltaic

Advanced

Packaging

Microfluidic

& Bio-tech

Power

Electronics

LED &

Compound Semi

© 2012 • 30


Our Global Presence & Activity

Yole Inc.

Yole Développement

Lyon (HQ).

Yole Europe

Yole Japan

30% of our activity is

in North America

30% of our activity is

in Asia

40% of our activity is in

EU Countries

[email protected]

[email protected]

[email protected]

Yole Taiwan

Yole Korea

[email protected]

[email protected]

© 2012 • 31


Via First / Via Last? 3D integration Scenarios

I

M

E

C

S

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x

F

r

e

e

s

c

a

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N

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D

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P

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TSV+ Cost Analysis Tool for

your 3D IC manufacturing

3D IC & TSV 2010 Market Analysis

I

M

E

C

S

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l

e

x

F

r

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s

c

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N

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$27

7% $23

6%

$109

26%

$82%$37

9%$92%

$317%

$168

41%

TSV Scenario Cost structure breakdown

Via / Etching Drilling

Via Isolation

Via filling

Temporary bonding

Thinning

Stress release

BEOL (Pads)

Bonding

IPD - Thin-film Integrated Passive Devices

WL CSP 2012 Report update

N

o

k

i

a

2.5D Glass & Silicon

interposers - 2010 Report

© 2010


MEMS Packaging Market & Technology Trends

1995

Sidebraze DIP

1996-2002

Plastic PDIP

1999 - today

SMT SOIC

& Die Down

2006

Stacked Die

QFN

~125 sq mm ~100 sq mm ~25 sq mm

6 & 6 mm

1995

Sidebraze DIP

1996-2002

Plastic PDIP

1999 - today

SMT SOIC

& Die Down

2006

Stacked Die

QFN

~125 sq mm ~100 sq mm ~25 sq mm

6 & 6 mm

Our latest advanced packaging

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© 2010

Copyrights © Yole Développement SARL. All rights reserved.

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Wafer Packaging Fabs

DATABASE

© 2009

Copyrights © Yole Développement SARL. All rights reserved.

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