frequency domain design demo i ee 362k (buckman) fall 03
DESCRIPTION
Frequency Domain Design Demo I EE 362K (Buckman) Fall 03. Start with a nasty, complicated plant with not one but two strong resonant frequencies: more complicated than anything we’ve tackled so far. . . Showing Plant only. - PowerPoint PPT PresentationTRANSCRIPT
Frequency Domain Frequency Domain Design Demo IDesign Demo I
EE 362K (Buckman) Fall 03EE 362K (Buckman) Fall 03
Start with a nasty, complicated plant with not one but two strong Start with a nasty, complicated plant with not one but two strong resonant frequencies: more complicated than anything we’ve resonant frequencies: more complicated than anything we’ve
tackled so far. . .tackled so far. . .
Two resonances
Frequency-domain info even helps in describing the plant: note how 2 resonances not obvious in time-domain
Showing Plant only
Turning on the unity feedback reveals another problem: Turning on the unity feedback reveals another problem:
Bad steady state error
Need more gain at low frequencies
Problems identified:Problems identified:• Steady-state error: need more gain near DC
try pole on real axis • Two resonances: need less gain at:
=3.15 =9.13
• Try two complex-conjugate pairs of zeros
Start with a real pole in Start with a real pole in C(s),C(s), at at = -50= -50
Pole at = -48.45 introduced here
This pole is too far left in the s-plane to have any observable effect on either the frequency or the time-domain response of the closed loop system: both are unchanged!
Bringing this new controller pole to the right starts boosting the gain at Bringing this new controller pole to the right starts boosting the gain at low frequencies at aboutlow frequencies at about
= -0.4 = -0.4
Low-frequency gain increased
Steady-state error still bad
It might be tempting to just increase the overall gain….BUTIt might be tempting to just increase the overall gain….BUT
The peaks come back.Although, SSE is a bit less.
Since the peak near Since the peak near =3 is now the most obvious problem, attack it next: =3 is now the most obvious problem, attack it next: introduce a complex conjugate pair of zeros, starting with a large negative introduce a complex conjugate pair of zeros, starting with a large negative
real part. . .real part. . .
New zeros
No observable changes in frequency- or time-domain behavior yet: zeros are too far away from the w-axis to have any effect
We also backed down the DC gain
You can suppress the low-frequency oscillations completely by bringing You can suppress the low-frequency oscillations completely by bringing this pair of zeros closer to the this pair of zeros closer to the -axis and adjusting the -axis and adjusting the value slightly: value slightly:
No low-frequency peak
No low-frequency oscillations
Adjusted slightly to make the zeros “cancel” the low-frequency pair of poles. This is most easily done looking at the pole-zero plot.
Cranking up the DC Gain reveals that the high-frequency resonance is now Cranking up the DC Gain reveals that the high-frequency resonance is now threatening to drive the closed-loop system unstablethreatening to drive the closed-loop system unstable
Poles about to cross -axis
Phase shift becoming discontinuous
So once again, back down the DC gain and introduce another pair of zeros So once again, back down the DC gain and introduce another pair of zeros near the high-frequency resonancenear the high-frequency resonance
New pair of zeros supresses high-frequency peak, cancels poles
Try increasing DC gain now:Try increasing DC gain now:
+2% risetime
About 2% steady-state error
The only thing wrong with this picture is the unrealistic controller:The only thing wrong with this picture is the unrealistic controller:
More zeros than poles for C(s)
Gain increasing without bound at high frequencies
4 zeros, 1 pole indicates 4 more poles needed
Put in two pole pairs at Put in two pole pairs at ss=-40=-40++j0.0, and move the real pole to –0.12:j0.0, and move the real pole to –0.12:
Stays within +3% in 0.55
You can do better on risetime and steady-state error, but it requires even You can do better on risetime and steady-state error, but it requires even more controller gain than this:more controller gain than this:
Max gain = 41dB
Translated to digital, this design holds up well down to a sampling Translated to digital, this design holds up well down to a sampling frequency of 30:frequency of 30:
Shifting the two pole pairs from –40 to –100 lets you bring the sampling Shifting the two pole pairs from –40 to –100 lets you bring the sampling frequency down to 8.0 and still maintain performance:frequency down to 8.0 and still maintain performance:
Frequency-domain design Frequency-domain design summarysummary
• Careful placement of poles and zeros in the controller C(s) lets you smooth out peaks and valleys in the closed loop transfer function H(s).
• First, identify problems with the frequency-domain shape of H(s):– Too little gain at low frequency– Peaks or dips to smooth out
• Increasing DC gain will accent the biggest problem areas: fix them first• Fix frequency-domain of H(s) using more poles and zeros, keeping DC
gain relatively low until the final steps• Introduce extra poles if necessary to keep your C(s) realistic• Translate your controller C(s) to a digital design D(z), lowering
sampling frequency to realistic levels.