fundamental of loic synthesis

8/16/2019 Fundamental of Loic Synthesis

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Fundamentals of Logic Synthesiswith Design Compiler

Imran Mirza


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Verdana regular 7pt.

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Some Key Terminologies & Definitions

• Logic Synthesis is a process by which a circuit represented in anabstract form of HDL/RTL is implemented in terms of logic gates.

Alternatively, it can simply be defined as a process of transformingRTL description of a design into standard cell gates of technologylibrary.

• Standard Cells represent logic cells that belong to a technologylibrary that is characterized for a particular process. e.g. AND, OR,

INVERTER, Flip Flops etc.• Netlist is post synthesis abstraction of a design.

• “Netlist” description represents a design in terms of aninterconnection of Std cells that are connected via wires alsoreferred to as nets in Synthesis world.

• Netlist representation of a design is used for down stream flowsduring ASIC flow. e.g. for gate level simulation and place & routeetc.


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Major Synthesis Steps

• Synthesis process is comprised of 3 main steps of Translation,Optimization & Mapping.

– Translation is a process of converting RTL description into intermediateformat represented in form of Boolean equations. Boolean form is thanimplemented using intermediate generic cells (GTECH). GTECH cellssimply describe functionality without any timing info and othercharacteristics.

– Optimization is a process of finding optimal solution to intermediate logic

structures/equations based upon a criteria (constraints) specified beforesynthesis.

– Mapping is process of translating optimized generic gates to cells in targettechnology library (Std. Cell Library).

Target_library

(p1265)

HDL

If (sel == 1) {Out


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Synthesis Steps cntd.• Typically, after initial mapping during synthesis process; synthesis

tools continue to perform iterative Optimizations & Mapping steps inan effort to achieve the best solution.

– Initial optimization phase involves technology independent algorithms toselect best structure for logic functions.

– During “mapping” circuit logic is mapped to gates of technology library to

transform the circuit to network of gates.

– Followed by technology dependant optimization algorithms to performfurther logic minimization.


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Design Ware (DW) Libraries

• DW library is a selection of technology independent and pre-verifiedsynthesizable IP blocks supplied by synopsys.

• DW libraries are used during High Level Optimization (HLO) ofsynthesis process.

• DW IP blocks range from simple logic functions of AND,NAND,NOR toarithmetic functions (+,-,


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HDL

Synthetic library

Operators in HDL (+, - etc.)

Synthetic OperatorsADD_UNS_OP

ADD_SUBADD ALU

CLARipple Custom IP

Have Bindings to SyntheticModules :

Several ImplementationsOf Modules Exist inDesign Library

High Level Optimization tasks likeresource sharing etc. is relatedto this phase

Implementation selectionOf synthetic modules is done fromvarious implementationavailable in Design Library.During Optimization processConstraint-driven ImplementationSelection takes place to meet

timing/area goals. DWimplementation is eventuallymapped to target-library andfurther optimized.


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3 Levels of Optimization

Logic Optimization occurs at 3 levels:– Architectural

– Logic

– Gate Level.

• After initial high level architectural optimization, Design Compilermostly iterates between Logic & Gate level optimization.

• DC moves the logic functions back and forth between logic & gate

level representations to fully take advantage of various optimizationtechniques.

• Optimization process continues until no further improvements in thelogic structure are possible.– i.e. No further improvements to “Optimization Cost function” are

possible.

Note: These optimization steps can be guided by user.


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• Architectural Optimization: This type of Optimization occurson HDL description and is also referred to as high level optimization(HLO). It includes several sub phases:

– DW Implementation Selection.– Arithmetic or Data path Optimization.

– Resource sharing.

– Reordering operators.

• Design is represented in terms of GTECH cells after HLO.

• Except DW Implementation most of the above mentioned tasksoccur only in the beginning i.e. during optimization of unmappeddesign. Therefore it is technology independent.

• Implementation selection is the process of mapping HDL logic to alibrary of DesignWare (DW) components (also reffered to asGTECH).– Initial mapping to DW is constraint independent. But later in the process

synthesis tools evaluate speed/area tradeoffs to select bestimplementation e.g for adders selecting carry look-ahead (for speed) oreven better Brent-Kung (fastest) vs ripple carry (smallest) etc.


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Implementation Selection process:

Z


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• Logic Optimization: After high level architectural optimization,design is represented in terms of GTECH components.

– Logic optimization works on GTECH representation (representation after

elaborate).

– During logic synthesis, tools try to improve logic structure by reducingSOP form via minimization of product terms. This is achieved using 2techniques:

• Structuring.

• Flattening.

• Structuring: It is the logic optimization technique by which tooladds intermediate variables and logic structures to a design,resulting in reduced logic area. Typically tool tries to search for sub-functions that can be factored out.

– It is ON by default in timing driven mode. i.e. timing driven structuring

improves structures on critical paths without touching non-timing criticallogic paths.

– Structuring works best on random logic strcutures such control logic. It isnot very effective on adders, ALU’s etc.


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Example of Structuring:

•Before structuring:func_1 = ab + ac

func_2 = b + c+ d

•After structuring:

t0 = b + c

func_1 = t0.a

func_2 = t0 + d

• DC command to play with structuring options is “set_structure”.


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AB

C

func_1

D

func_2

Before

structuring

After

Structuring

A

B

C

D

func_1

func_2


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• Flattening: Flattening is a logic optimization technique by which allintermediate variables are removed; consequently related logic

structures.– Boolean distributive laws are used to remove all parenthesis. Removingpoor intermediate variables helps synthesis tools to achieve more efficientfunctions.

– Flattening is off by default because default timing-driven structuring canimprove critical paths & flattening can potentially increase area.

– It is independent of constraint unlike structuring.– Result of flattening is a two level Sum of Product form

– Result of flattening can be input to structuring phase to find optimalsolution to logic equations.

Example:Before flattening

out = t1 t2

t1 = a + b(c + f)

t2 = d + e’

After flattening

out = ad + bcd + bdf + ae’ bce’ + be’f


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– Snippet from DC log file:Beginning Pass 1 Mapping

------------------------

Processing 'mux2_32_1‘

Processing 'edff1_32_0

Beginning Implementation Selection

----------------------------------

Processing 'eu_spedp_DW01_cmp2_5_0‘

Beginning Mapping Optimizations (Ultra High effort)

Structuring 'eu_staging'

Mapping 'eu_staging'Beginning Delay Optimization Phase

----------------------------------

Beginning Design Rule Fixing (max_transition)

----------------------------


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Design Compiler (DC) tool Interface.

• Design Compiler (DC) is industry standard Logic Synthesis tool from “Synopsys”.

• Tool interface and commands used for this training will be DCcentric.

Design Compiler

RTL/NetlistConstraints TechnologyLibrary

MacroLibrary

WLM

Synthesizeddatabase i.e.Netlist/ddc

SynthesisReports


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Synthesis Setup• Some basic variables to be included in synthesis setup are as

follows:

– target_library : Specifies the library used by synthesis during

optimization process to map logic to standard cell gates from specifictechnology library. e.g. p1265_lp_rsss_1.15v_110c.db.

• Traditionally this is a single library.

• New features in DC allows for multiple libraries (MVDD, MVT etc)

– link_library : This variable contains the names of all libraries that areused to “link” the design. i.e. standard cell and macro libraries that

contain leaf cell definitions of cells instantiated in the design.– In DC, term “link” is used to imply resolving references of allinstances in the design. Or simply put find all references in thedesign.

– Linking also Means Correct Design Composition w.r.t cell names,ports/pins directions, vector range and connectivity etc.

– In a hierarchical design the lower level designs themselves become

part of link variable collection.


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Synthesis Setup

– search_path: Is used to include paths to directories containingtarget_library, link_libraries and any reference designs. Tool searches for

libraries & ref designs in all directories specified with search_pathvariable.

– synthetic_library : This is an optional variable and points to DesignWarelibs. Basic DW libs are loaded by default. Use this to add advancedlibraries.


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Setup Examples:

• Example:set link_library {* p1265_lp_rsss_1.15v_110c.db}

set target_library {p1265_lp_rsss_1.15v_110c.db}

set synthetic_library {dw_foundation.sldb standard.sldb}

set search_path [concat /nfs/adg_pde_8/Eval65/library/stdcell_lp_frams/LM \ $search_path]

OR

set search_path “/nfs/adg_pde_8/Eval65/library/stdcell_lp_frams/LM \ $search_path”

Example:

module test_fub (a, z);

inputs a;

outputs z;sub_fub_1 U1 (.a(a), .b(net_1));

sub_fub_2 U2 (.m(net_1), .o(z));

endmodule


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Technology Library

• Lets examine technology library a little (p1265_lp_rsss_1.15v_110c.lib):

library ("p1265_lp_rsss_1.15v_110c") {

/* *************************************************************************** Intel Confidential

****************************************************************************

revision : "lp_lib";

date : "Mon Aug 22 14:22:11 MST 2005" ;

comment : "PROCESS: p1265, MODEL: lp, VOLTAGE: 1.15v, TEMP: 110c, SKEW: rsss; " ;

/* ************************************

• ** UPF used : p1265_1x0r1v1.upf

• ** Shrink applied : 1

• ************************************* */

technology (cmos) ;

delay_model : table_lookup ;

time_unit : "1ps";

pulling_resistance_unit : "1kohm" ;

capacitive_load_unit(1,pf) ;

voltage_unit : "1V" ;

current_unit : "1uA" ;

leakage_power_unit : "1pW" ;


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Library header cntd:

operating_conditions("rsss_1.15v_110c") {

process : 1.0;

temperature : 110.00;

voltage : 1.15;

tree_type : "balanced_tree";

}

nom_process : 1.0 ;

nom_temperature : 110.00;

nom_voltage : 1.15;

default_max_transition : 1100 ;

default_fanout_load : 1.0 ;default_output_pin_cap : 0.0 ;

default_inout_pin_cap : 0.010 ;

default_input_pin_cap : 0.010 ;

default_cell_leakage_power : 0.000001;

default_operating_conditions : rsss_1.15v_110c;

default_wire_load_mode : enclosed;

default_wire_load_capacitance : 0.0000873;

default_wire_load_resistance : 0.100;

default_wire_load_area : 15.5;


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Library Cell Description:

/* Begin cell: lp0in00x6 */lu_table_template (delay_outputslew_template_5X5_lp0in00x6) {

variable_1 : total_output_net_capacitance ;variable_2 : input_net_transition ;index_1 ("1.0, 1.1, 1.2, 1.3, 1.4");index_2 ("2.0, 2.1, 2.2, 2.3, 2.4");

}power_lut_template (internalPowerTable_5X5_lp0in00x6) {variable_1 : total_output_net_capacitance ;variable_2 : input_transition_time ;index_1 ("1.0, 2.0, 3.0, 4.0, 5.0");index_2 ("1.0, 2.0, 3.0, 4.0, 5.0");

}cell ("lp0in00x6") {nandgates : 3 ;area : 3.696 ;cell_footprint : lp0in00 ;

cell_leakage_power : 49512 ;pin ("o") {

direction : output ;


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Lib cell description cntd:

function : "!(a)" ;max_capacitance : 1.17877 ;

timing() {

cell_fall ("delay_outputslew_template_5X5_lp0in00x6") { /* Simulation data for spec: ̀ tp_a_xy_o_10_max' */index_1 ("0.0032143, 0.0915343, 0.2415343, 0.6015343, 1.6575343") ;index_2 ("25.0000000, 699.9990000, 850.0000000, 1000.0000000, 1100.0010000") ;values (\ "18.0516507, 80.9752712, 91.3866032, 100.8858463, 107.5135250",\ "62.9328920, 232.2513450, 254.3557764, 274.5694844, 288.2005986",\ "128.4946355, 377.2112071, 411.7081601, 443.4568683, 464.3401994",\ "284.0081877, 616.2618329, 669.1884016, 718.0893649, 749.9088390",\ "740.2694301, 1139.8097050, 1214.0552580, 1287.8451130, 1336.2840450"\ );

}cell_rise ("delay_outputslew_template_5X5_lp0in00x6") {

/* Simulation data for spec: ̀ tp_a_xy_o_01_max' */index_1 ("0.0032143, 0.0915343, 0.2415343, 0.6015343, 1.6575343") ;index_2 ("24.9990000, 700.0010000, 850.0000000, 1000.0000000, 1100.0010000") ;values (\

"15.2790723, 0.0000000, 0.0000000, 0.0000000, 0.0000000",\ "61.2986975, 145.3533894, 149.7023032, 153.4330957, 153.3298057",\ "131.3437529, 290.6696952, 307.1302922, 321.4521477, 327.8411756",\ "299.1350892, 533.7899475, 568.5006742, 599.4795268, 616.5449063",\ "791.1555851, 1082.2604470, 1135.6769800, 1186.8994620, 1217.9290430"\ );

}


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fall_transition ("delay_outputslew_template_5X5_lp0in00x6") {

/* Simulation data for spec: `tp_a_xy_o_10_max' */

index_1 ("0.0032143, 0.0915343, 0.2415343, 0.6015343, 1.6575343") ;

index_2 ("25.0000000, 699.9990000, 850.0000000, 1000.0000000, 1100.0010000") ;

values (\

"10.1024224, 96.0716241, 113.2238550, 129.4873606, 141.0555352",\

"56.7503343, 196.0574868, 220.1910273, 244.6424514, 260.7628678",\

"136.9945580, 295.4627289, 326.1557160, 355.8550934, 376.5465104",\

"334.6133697, 484.4706030, 520.9409643, 559.2599686, 582.9060445",\

"920.5215483, 1025.3939690, 1060.9164640, 1088.7083360, 1114.7036800"\

);

}

rise_transition ("delay_outputslew_template_5X5_lp0in00x6") {

/* Simulation data for spec: `tp_a_xy_o_01_max' */index_1 ("0.0032143, 0.0915343, 0.2415343, 0.6015343, 1.6575343") ;

index_2 ("24.9990000, 700.0010000, 850.0000000, 1000.0000000, 1100.0010000") ;

values (\

"12.0370839, 100.1307945, 116.6247064, 132.6044484, 143.3954581",\

"76.5285867, 214.6937751, 240.8224270, 263.3653485, 278.8470840",\

"192.3296389, 341.3812802, 372.7134246, 403.8706037, 422.3452089",\

"468.3673746, 591.1956305, 628.3677618, 665.3410636, 689.3084127",\

"1284.3755410, 1348.5314550, 1386.3845050, 1424.2627460, 1438.6392750"\

);

}


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timing_sense : negative_unate ;

related_pin : "a" ;

}

}

pin ("a") {

capacitance : 0.00965679129 ;

direction : input ;

}

}

/* End cell: lp0in00x6 */


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Read Design

• Commands to read design:– read_file -format verilog rtl_file_name

– read_file -format vhdl rtl_file_name– analyze/elaborate i.e:

define_design_lib work -path ./worklib

analyze -f verilog ${DESIGN}.v

elaborate ${DESIGN}

“analyze” reads RTL description and if there are no syntax issues; savesthe intermediate binary format to “work” library.

“elaborate” is used to to actually build the design, so its ready forsynthesis with “compile” command.

• If input format is RTL, analyze/elaborate commands arerecommended.

• If input format is gate level netlist use read_file commands.

Preferred Methodfor RTL designs


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DC script building with commands learned

• Lets start building a script using commands as we learn them:

• Setup file .synopsys_dc.setup will look like :set sh_enable_line_editing true

set text_editor_command {xterm -fn 8x13 -e vi %s &}

set link_library {* p1265_lp_rsss_1.15v_110c.db}

set target_library {p1265_lp_rsss_1.15v_110c.db}

set synthetic_library {dw_foundation.sldb standard.sldb}

set search_path "./rtl

/nfs/ch/disks/ch_com_disk026/design_kit/p1265_1/stdcell_lp/synthesis/1.3/synopsys/2000.11 $search_path“

• Lets start synthesis script “training.tcl”:


source -echo read_file

analyze -f verilog ${rtl_list}

elaborate exunit


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Constraining the Design

• Design constraints are circuit goals to ensure that final chip worksafter manufacturing. They are used to specify performance (timing),

area & power goals of your design.

• Optimization process uses design constraints to guide the tool toachieve required goals. Constraints are classified under followingcategories:

– Optimization Constraints.– Design Rule Constraints.

– Environmental Constraints (operating conditions, K-factor & WLM etc.).

• Optimization constraints are timing, area constraints.

• Design Rule Constraints are electrical requirements that must bemeet to ensure chip functionality e.g. max_capacitance,max_fanout, max_transition etc.


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Optimization Constraints

• Timing Constraints: Are used to specify designs timing specifications

to guide synthesis process.– By default timing constraints have higher priority over area.

• Order of cost priorities can be changed (to be discussed later)

– Clocks are used to specify operating frequency of the design.

– Clock definition is needed to constrain internal paths i.e. flop2flop paths.

create_clock -name clk -period 15000 [get_ports clk]

– In pre-layout synthesis clocks created with “create_clock” are assumedideal by default.

– “Ideal” nets are nets with “zero” delay (i.e. 0 clock network latency &

transitions).

– DC synthesis does not insert any buffers/inverter on clock nets i.e. timingcheck & optimization is off.

– Ideal nets are also free of DRC constraints.


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Clock uncertainty

• Clock uncertainty is used to model difference in arrival time of clockedges. It includes following items:– Clock Jitter:

• Jitter is the unpredictability of the PLL/Oscillator output in terms of exact timewhen a clock edge is going to arrive.

• A perfect oscillator would have rising edges occurring at precise moments in timethat would never vary. This, of course, is impossible in real electronics, which havesources of noise and other imperfections.

– Expected Clock Skew.

– Process Guardband.

• In DC uncertainty is specified using following commands:

set_clock_uncertainty 500 [get_clocks clk]

set_clock_uncertainty 200 -from [get_clocks clkB] -to [get_clocksclkA]


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Clock Latency

• Clock latencies are used to model delay in clock network.

– Clock source latency models clock insertion delay to the

clock definition point. i.e. time taken by clock signal topropagate from clock generation point to clock definitionpoint.

– Clock network latency is used to model delay due to clocknetwork from clock definition point to register clock pin.

set_clock_latency 1000 [get_clocks clk]

NOTE: Use “-source” option to model clock source latency.Clock Source Latency can be used to model reality of toplevel tree delay in a hierarchical chip (if there is hugedifference in clock arrival time between APR blocks).


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Figure 1: Clock constraining internal timing

D

CLK

Q Q

CLK

D

Clock origin

point

Clock Definition

point

Clock Launch

EdgeClock Capture

Edge

15 ns clock period

skew + jitter

etc.

Flop 2 Flop path w.r.t 66 MHz

clock Frequency

Combinational

logic

PLL

Ideal Clock

Non Ideal Clock


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Constraining Interface Paths

• Constraining the Input Path.– Your inputs come from the outside world or blocks designed by other

designers. When do they come during the clock cycle? Do they come at4ns after the rise of clock ?

– The synthesis tool needs to know this to figure out how much time itreally has left to meet the timing on path.

set_input_delay -max 4000 -clock clk [get_ports A]– This tells the tools that external world uses 4000ps (4ns) of time based on

the clock period of clk. If clk was 66MHZ (15ns) the tool has 15-4 = 11nsfor all it internal logic.

– For setup analysis, input_delay is the worst case delay value (-max).

– For hold analysis, input_delay will be the best case delay value (-min). i.e.

shortest delay value.


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set_driving_cell

• This command impacts input ports transition delay and is a DRCconstraint in reality.

• It helps with more accurate timing calculation on input ports byannotating non-zero transition delay on input ports.

• There can be more optimistic input path timing without modelinginput transition time. Without set_driving_cell at input ports, defaulttransition delay is zero.

set_driving_cell -library p1265_lp_rsss_1.15v_110c -lib_cell lp0bf00x3 –pin o[remove_from_collection [all_inputs] [all_clocks]]

• To be pessimistic use a weak cell driving the inputs ports.

•

set_input_transition is another way of doing the same thing.


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set_output_delay• It constrains output interface. i.e

set_output_delay 7000 -max -clock clk [get_ports B]

•This means that out of 15 ns of clock cycle time available; 7 ns is taken byexternal logic. i.e. 15-7=8ns is the remaining time left for logic cone ending inport B.

Note: set_input_delays are applied w.r.t launching clock edge and

set_output_delay is done w.r.t latching clock edge.

D

CK 1

Q 7 ns4 ns

CK 2CK 1

DD QQ

create _clock

set_input_delay set_output_delay

Input/Output Delays


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Set_load

• On output ports need to specify external capacitive load to accurately

calculate timing and accordingly size the driver of output ports during timingoptimization. Command to use is set_load e.g.

set_load load_value [get_ports]

or

set_load [expr [load_of p1265_lp_rsss_1.15v_110c/cell/pin] * 2] [get_ports A]

•

Usually it is specified on output ports but can also be specified on input ports.But not recommended for input ports as it can make input loading constraintunnecessarily pessimistic since usually “set_max_capacitance” is alreadyused for input ports.

• For budgeting of set_load on output ports, it’s a good idea to have designknowledge to gauge how many blocks does the output port talk to.

• “set_load” sometimes is also referred to as environmental constraint.


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A C i


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Area Constraint

• To enable area optimization in DC you need to use:– set_max_area 200

• By default DC performs very little area optimization as timing hashigher priority over area cost unless higher priority is placed onArea.

• By default area optimization happens only on paths that meettiming.

• Typically value for area constarint used is “set_max_area 0”. Tooltries to achieve the smallest area possible.

• Area optimization can be turned off by using a switch to “compile”command.

•

Area units are dependant upon library. i.e. area is usually in terms ofsq. microns. It can be normalized in terms of NAND gates.

D i R l C t i t


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Design Rule Constraints

• Design Rule Constraints (DRC) must be meet to ensure that designfunctions correctly.

• DRC have higher priority than optimization constraints.

• DRC constraints are typically defined by default in technology libraryfor the tool to use.

• User can also specify explicit DRC constraints.

• Synthesis tool will try to meet more restrictive constraints.• DC tries to address DRC violation using repeater insertion & cell

sizing techniques.

• Types of DRC:– Maximum transition time

– Maximum fanout– Minimum and maximum capacitance


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t it


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set_max_capacitance

• Max_capacitance design rule constraint is also imposed implicitly viatechnology library.

•DC compiler tries to ensure that total capacitive load on a net (i.e.interconnect cap + load pin cap ) is less than max_capacitanceattribute of driver pin.

• Explicit max_capacitance attribute can also be specified on design orinput ports using command, “ set_max_capacitance”.

•In presence of both library max_capacitance & designsmax_capacitance value, DC adheres with more restrictive constraint.

Note: max_tran & max_fanout constraint also impactmax_capacitance constraint of nets indirectly.

t f t


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set_max_fanout

• Max_fanout is another type of DRC constraint that can be placed ona design or input ports.

• If its placed on a design it applies globally to all driver pins of nets inthe design.

• In the presence of global max_fanout on design or explicitmax_fanout on ports, DC honors most restrictive.

• If this attribute exists, DC tries to ensure that its meet by ensuring

that sum “fanout_load” atttribute on all input pins driven by net inquestion is less than max_fanout attribute specified by

“set_max_fanout ” command or if implicit default max_fanoutattribute exists in the library.

T i i t l


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Training.tcl




elaborate exunit

current_design exunit

link


set_clock_uncertainty -setup 450 [all_clocks]

set_input_delay 750 -max -clock clk [remove_from_collection [all_inputs] [all_clocks]]

set_output_delay 750 -max -clock clk [all_outputs]

set_load [expr [load_of p1265_lp_rsss_1.15v_110c/lp0an02x2/a] * 2] [all_outputs]

#Try to be conservative on your selection of driving cell.

set_driving_cell -library p1265_lp_rsss_1.15v_110c -lib_cell lp0bf00x3 -pin o[remove_from_collection [all_inputs] [all_clocks]]

Const aint p io ities


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Constraint priorities

• Design Rule constraints have higher priority over optimization constraints.

• Default order of constraint priorities honored by DC is as follows:– DRC– Max_delay (setup violations)– Min_delay (hold violations)– Area.

Note: This precedence order can be changed by user, especially the setup/hold priority

• DC’s optimization algorithms rely on minimizing “cost functions”.

•

During Optimization process, DC strives to reduce costs of various types of constraintsdown to zero and finally gives up when no further improvements to cost functions arepossible. e.g. Cost function for max_delay constraint is given by sum of worst violatoracross all path groups e.g. if there are “m” path groups:

v1.w1 + v2.w2 + v3.w3 + ………+vm.wm

Where :

v = worst violator of given group.

w = weight assigned to each path group.


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K Factor


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K-Factor

K-factors are used to simulate alternate choices for cell delays in the

timing libraries by using a scaling factor (less than or greater than1.0).

• It is not possible to characterize 1000s of stdcell for all possiblesilicon applications in a particular process.– So, library developers typically re-design/characterize few sample cells

and find a number thru extrapolation to be used in timing alalysis.

• Operating Conditions and K-factors can be embedded in the .lib fileor can be defined through tool commands (DC/PC/PT/Astro).


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Delay Scaling Formula with K Factor


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Delay Scaling Formula with K-Factor

D(scaled) = D_original_from_LookUp_Table(1 + d'process * K-process) \

(1 + d'temp * K-temp) \

( 1 + d'voltage * K-voltage)Where,

d’process = (process_operating_cond - process_nominal )

d’temp = (temp_operating_cond - temp_nominal)

d’voltage = (voltage_operating_cond - voltage_nominal)

In most cases

• K-process for cell_rise/fall = 1

• K-process rise/fall_transition = 1

• K-voltage = 0

• K-temp = 0

Hence in most cases:

D(scaled) = D_original_from_LookUp_Table (1 + d'process * K-process) (1 + 0) ( 1 + 0)

= D_original_from_LookUp_Table (1 + d'process * K-process)

Wireload models


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Wireload models.

• WLM contain information to estimate nets interconnect delay (i.e nets RC) and area etc.

• WLM are statistical estimates based on nets fanout numbers.

• Estimates are generated based upon designs that have gone thru place & route and

used same process technology in the past.wire_load_table("1.9_million") {

fanout_length( 1, 20.8158);

fanout_capacitance( 1, 0.0055);

fanout_resistance( 1, 35.2344);

fanout_area( 1, 2.1840);

fanout_length( 2, 50.1063);fanout_capacitance( 2, 0.0133);

fanout_resistance( 2, 70.4688);

fanout_area( 2, 2.7300);

• Command:

set_wire_load_model -name "poulsbo2d_core_custom_wireload" -library

"poulsbo_custom_wireload"


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U1 U2

U3

Fub_A Fub_B

Fub_A

U1 U2

U3

Fub_A_0 Fub_B

Fub_A_1

After Uniquify

Before

Uniquify

Compile Strategies


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Compile Strategies

• You are now all prepped up to start design optimization.

• Primarily two types of synthesis approaches are commonly used.

• Top-down vs bottoms-up:– Top-down:

partition ------------- Compile.

unit_A

unit_B

unit_C– Bottoms-up:

partition ------------- link here or “compile –top”

unit_A ------------- Compile

unit_B ------------- Compile

unit_C ------------- Compile

Advantage and Disadvantages


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Advantage and Disadvantages

Top Down

Pros:

•Only top level constraints needed

• Better results due to optimization across boundaries

Cons:

• Longer Compile Times

• Incremental Changes require complete re-synthesis

Bottom Up

Pros:

• Sub-blocks changes shorter turn-around time.

• Divide & conquer approach and maybe somewhat easy to debug issues.

Cons:• Many scripts to coordinate, update, and “budget”

• Top level may need incremental compile to fix DRC

Compile Strategies


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Compile Strategies

• There are endless design optimization strategies that can be tried.

• Lets take a look at some common synopsys suggested strategies.

1) Run “compile” with default settings i.e:compile -map_effort medium –scan

if constraints meet, you are done.2) If initial compile does not work, you can try tightening the constraints by

10% to 15%.3) Try two pass back2back compile approaches i.e.

compile -map_effort medium –scancompile -incremental_mapping –scan –map high

For 2nd pass you can also use following without “high” effort; if only gate level re-mapping will fix issues:

compile -incremental_mapping –scan

Compile Strategies cntd


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Compile Strategies cntd.

4) Use DC Ultra license feature. DC ultra uses advanced critical pathresynthesis (CPR) algorithms when used with “high” effort compile toimprove performance. This feature is turned on with “set_ultra_optimization”command.– Set_ultra_optimization helps with critical path synthesis by duplicating fanin cones to

reduce loading of critical paths.

– It also maps to complex wide fanin cones.

5)Use critical_range during synthesis (will be discussed in Advanced section).

6) Perform path group segregation using “group_path” approach.

7) Several things can be tried with DesignWare Components. E.g. if critical pathcontain DW components, ungroup DW hierarchy for further optimization.

8) Ungroup smaller designs if they contain critical path to take advantage oflogic merging.

9) For area critical designs compile for area first followed by timing if timing is

easily meet.

10) Constant propagation with set_logic_one, set_logic_zero, set_unconnected,set_logic_dc etc. it simplifies logic connected to constants.

Compile options switches/options


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Compile options switches/options

dc_shell-xg-t> compile -help

Usage: compile # compile design

[-map_effort effort] (map effort: low, medium, high)[-area_effort effort] (area effort: none, low, medium, high)

[-incremental_mapping] (perform only incremental mapping changes)

[-exact_map] (sequential cells to be mapped exactly as indicated in HDL)

[-ungroup_all] (ungroup all hierarchy)

[-boundary_optimization]

(optimize across hierarchical boundaries)

[-auto_ungroup automatically ungroup small hierarchies]

(auto ungroup: area, delay)

[-no_design_rule] (don't fix design rules)

[-leakage_mode] (Use leakage power as the secondary cost)

[-no_map] (don't map design; leave as generic logic)

[-only_design_rule] (only fix design rules)

[-only_hold_time] (only fix hold time violations)

[-top] (optimize the interface logic of the hierarchical sub-designs)

[-scan] (replace all sequential elements by scan equivalent)

Power of compile ultra


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Power of compile_ultra

• This is one of the new feature of DC that provides push buttonapproach to achieving convergence for high-performance designs.

• Embedded two-pass approach under the hood.

• No need to use two back to back runs like “compile”. But it won’thurt to try

• Uses DC-Ultra license & feature.

• This command does delay-based auto ungrouping of designhierarchies by default.

• By default, it ungroups DW hierarchies during 2nd pass phase.

• Hierarchical boundary-optimization also turned ON by default.

Compile ultra switches/options


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Compile_ultra switches/options

dc_shell-xg-t> compile_ultra -help

Usage: compile_ultra # compile design

[-no_autoungroup] (supress delay-based auto_ungroup)

[-no_uniquify] (no uniquify is needed)

[-exact_map] (sequential cells to be mapped exactly asindicated in HDL)

[-scan] (replace all sequential elements by scanequivalent)

[-no_boundary_optimization]

(do not run hierachical boundary optimization)


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Advanced Compile strategies with critical range,


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p g _ g ,group_path & group/ungroup commands

• By default DC works only on critical path in the design.

• To enable optimization of near-critical paths, two common approaches usedare:– Synthesis with critical_range.

– Grouping specific paths into separate path groups with group_path.

• Critical_range Optimization is turned on using “set_critical_range” command:

set_critical_range 1000 [current_design]• Critical range defines the range of violations over which compile works to

improve violations.

• It works on TNS instead of WNS i.e. it works on improving overall delay costof the design instead of worst violator by improving near_critical paths.

• Improving TNS can make WNS better as a pleasant side effect, if cones of

logic are shared (e.g. incase of structured logic, datapath logic etc.)• Critical_range optimization will not improve sub-critical paths if it worsens

the critical path.

group path


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group_path

• By default DC creates a separate path group for every clock domainin the design and works on optimizing WNS independently within

each path_group.• WNS in one path_group does not prevent optimization in other

(different) path_groups. i.e. cost function for max_delay only takesinto account worst violator within each path group seperately.

• Using Divide & conquer approach with “group_path” helps by

dividing timing critical designs into possibly several separate pathgroups making it easier for DC to meet timing.


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Example:


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Example:

• You can even further break it down to more path groups, to maketools job even easier:

group_path –name input_interface –from [all_inputs]

group_path –name output_interface –to [all_outputs]

group_path –name FEED_THRU –from [all_inputs] –to [all_outputs]

group/ungroup


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group/ungroup

• Removing level of hierarchy is one of the strategies to achievingdesired timing goals.

• Command “compile_ultra” performs delay based ungroup bydefualt.

• Similarly “compile” switch “-auto_ungroup” can also be used toenable ungrouping during synthesis.

– Note: compile switch for ungrouping is used in conjunction with followingvariable settings that define threshold for ungrouping:

compile_auto_ungroup_area_num_cells = "30"

compile_auto_ungroup_delay_num_cells = "500“

(if design hier has less than 500 cells “compile –auto_ungroup delay” will ungroup that level ofhierarchy)

• In addition, DC provides the capability to modify hierarchy OR re-partition blocks using group/ungroup commands.

Group/ungroup


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p/ g p

• Command “ungroup” can be used remove level of design hierarchy.

• This is also referred to as “flattening” the design.

Usage: ungroup # ungroup hierarchy

[-all] (ungroup all cells)

-prefix ] (prefix to use in naming cells

[-flatten] (expand all levels of hierarchy)

[-simple_names] (use simple, non-hierarchical names)

[-small ] (ungroup all small hierarchy)

[-force] (ungroup dont_touched cells as well)

[-soft] (remove group_name attribute)

[-start_level ] (flatten cells from level:

Value >= 1)

[cell_list] (list of cells to be ungrouped)

• To completely flatten the design, you can do:ungroup –all -flatten

Group command


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p

• Command “group” is used to create a new level of hierarchy.• Example: to understand group/ungroup:

– Consider following hierarchy:Chip

fub_1 U1

fub_2 U2

fub_3 U3

Lets “group” instance U1 & U2 into new design called “grouped_design”

group -design_name grouped_design–cell_name U12 {U1 U2}

Now design hierarchy will look like:Chip

grouped_design U12

fub_1 U1

fub_2 U2

fub_3 U3

Now perform ungrouping: ungroup U12 -start_level 2

Chip

grouped_design U12

fub_3 U3

Saving optimized database & generating


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g p g greports:

• To save database after optimization you can use several types of

commands:

• To save in db format (old synopsys binary format)write -format db -h -o ./outputs/${DESIGN}.db

• Now it is recommended to use new internal binary format called “ddc” format. It is supported in XG-mode:

write -format ddc -h -o ./outputs/${DESIGN}.ddc

• To save in verilog netlist format:change_names -hierarchy -rules verilog

write -format verilog -hierarchy -o ./outputs/${DESIGN}.vg

Note: In addition to logical information about the design; ddc (& db mode)also contain any constraints and any attribute information.

Training.tcl


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elaborate exunit

current_design exunit

link


set_clock_uncertainty -setup 450 [all_clocks]

set_input_delay 750 -max -clock clk [remove_from_collection [all_inputs] [all_clocks]]

set_output_delay 750 -max -clock clk [all_outputs]

set_load [expr [load_of p1265_lp_rsss_1.15v_110c/lp0an02x2/a] * 2] [all_outputs]

#Try to be conservative on your selection of driving cell.

set_driving_cell -library p1265_lp_rsss_1.15v_110c -lib_cell lp0bf00x3 -pin o [remove_from_collection [all_inputs] [all_clocks]]

set_operating_conditions -max_library p1265_lp_rsss_1.15v_110c -max rsss_1.15v_110c

###############################################

# If you wanted to define OC for min corner do:

###############################################

##set_operating_conditions -max_library p1265_lp_rsss_1.15v_110c -max rsss_1.15v_110c -min_library p1265_lp_rfff_1.50v_n30c -minrfff_1.50v_n30c

############################################

# Write Outputs

############################################

#write -format ddc -h -o ./outputs/exunit.ddc

change_names -hierarchy -rules verilog

#write -format verilog -hierarchy -o ./outputs/${DESIGN}.vg

Write SDC file & SDF.


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• You can also write out SDC file to be used by APR. Command used is

“write_sdc ${DESIGN}.sdc”.

• SDC has constraints such as clock definition, I/O timing, set_loads,FP, MCP’s etc.

• SDF file can also be written out for PT timing analysis or GLS.

• This SDF is based on WLM so accuracy is questionable.– Meaningful SDF/set_load is generated from post-Route database.

Reports.


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p

• There are several type of reports available for design analysis. Butmost common ones are as follows:

– report_area ----------------- Reports area information.– report_timing ----------------- Reports path timing information

– report_constraint --------------- Reports summary of violated constraints

– report_qor ---------------------- Reports quality of results summary.

– report_net ---------------------- Reports on designs nets

– report_net_fanout ----------- Reports net fanout info.

– report_clock ----------- Reports clock information, skew etc.

– report_cell ----------- Reports cell instance information.

– Check_design ----------- Checks for possible design issues.

– Check_timing ----------- Check for possible timing related issues.

• For details do “man” on dc_shell-t prompt:– man report_clock

Advanced topics (set_cost_priority)


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p ( p y)

• Previously, mentioned order of

constraint priorities as DRC,max_delay, min_delay & Area.

• Default order of cost priorities canbe changed using “set_cost_priority ”

command.

• To use this command effectively

need to further break downconstraint priorities as given intable:

Constraint priority in

descending order

Constraint Type

min_capacitance DRC

max_transition DRC

max_fanout DRC

max_capacitance DRC

cell_degradation DRC

max_delay Optimization Constraint

min_delay Optimization Constraint

Power Optimization Constraint

Area Optimization Constraint

Static Timing Analyses (STA) using Design Compiler


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• You are done with your synthesis session. Now what?

•

You should be able to analyze the database, look at the timingreports etc.

• Analyzing timing reports in DC is very similar to performing statictiming analysis (STA) using industry standard FC timing sign-offtool, PrimeTime.

•

Timing engine embedded in DC is called DesignTime. Although PT’stiming engine is not the same but tool interface/commands are verysimilar.

• STA is a process of validating timing performance of design withoutrunning long and time consuming dynamic simulations.

•

No test vectors needed for STA.• STA is fast and checks all timing paths exhaustively.


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Components of delay calculation


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• In timing reports total path delay is typically a function of following factors.

– Delay model from library e.g. generic cmos, Non-Linear Delay model. Usually it’sNon-Linear delay model.

– Interconnect delay model is used to model type of distributed RC Network.– WLM used for numerical estimates of RC values to be used for net parasitics.

– PVT from operating conditions.

• Cell Delays are computed from non-linear delay models specified in library.

• Cell delays are a function output loading & input pin transition.

•

Input pin transition & output loading also determine transition delay of netattached to output pin (driver pin).

• This net transition contributes to input transition of next stage of cells.

• Net delays are a function of WLM, tree_type & interconnect RC delay.

Types of Interconnect RC delay model


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• There are basically three RC tree_types for Interconnect models:

– Best_case: Both driver & reciever are considered adjacent to each othercausing zero resistance and so zero interconnect delay.

Delay = 0

– Balanced_case: All loads are on equal branches of net segments such thateach net segment incurs equal percentage of nets R & C.

Delay = (Rnet /N) * (Cnet /N + Cpin)

– Worst_case: Driver and receiver are assumed far form each other suchthat ecah load incurs fully lumped R & C.

Delay = Rnet(Cnet +Cpin)

Sample timing Path


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dc_shell-xg-t> report_timing

****************************************

Report : timing

-path full-delay max

-max_paths 1

Design : exunit

Version: X-2005.09-SP1

Date : Tue May 2 15:46:59 2006

****************************************

# A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: rsss_1.15v_110c Library: p1265_lp_rsss_1.15v_110c

Wire Load Model Mode: enclosed

Startpoint: se_astat_x1f[5]

(input port clocked by clk)

Endpoint: eu_dreg_g1f[17](output port clocked by clk)

Path Group: clk

Path Type: max

Timing path cntd:D /Cl t/P t Wi L d M d l Lib


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Des/Clust/Port Wire Load Model Library

------------------------------------------------

exunit 500_k p1265_lp_rsss_1.15v_110c

eu_rfctl 40_k p1265_lp_rsss_1.15v_110c

mux8_16_16 40_k p1265_lp_rsss_1.15v_110c

mux4_32_5 40_k p1265_lp_rsss_1.15v_110c

Point Incr Path

--------------------------------------------------------------------------

clock clk (rise edge) 0.00 0.00

clock network delay (ideal) 0.00 0.00

input external delay 750.00 750.00 r

se_astat_x1f[5] (in) 0.00 750.00 rrf_ctl/ccin_x1f (eu_rfctl) 0.00 750.00 r

rf_ctl/U3/o (lp0in00x16) 14.91 764.91 f

rf_ctl/U362/o (lp0na02x4) 22.98 787.88 r

rf_ctl/U124/o (lp0na02x4) 32.39 820.27 f

rf_ctl/U127/o (lp0no02x4) 33.18 853.45 r

rf_ctl/U354/o (lp0no02x4) 27.11 880.56 f

rf_ctl/U156/o (lp0na03x4) 31.80 912.37 r

rf_ctl/U157/o (lp0cb00x16) 65.06 977.42 r

Timing path cntd.


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rf_ctl/storesell_g1f[2] (eu_rfctl) 0.00 977.42 r

rf_store_g1f_int_lmux/sel[2] (mux8_16_16) 0.00 977.42 r

rf_store_g1f_int_lmux/U189/o (lp0in00x6) 25.96 1003.39 f

rf_store_g1f_int_lmux/U192/o (lp0no03x4) 85.42 1088.81 r



rf_store_g1f_int_lmux/U173/o (lp0no03x4) 42.59 1233.56 f

rf_store_g1f_int_lmux/U157/o (lp0na02x4) 28.32 1261.88 r

rf_store_g1f_int_lmux/U135/o (lp0ci00x8) 31.40 1293.28 f

rf_store_g1f_int_lmux/U177/o (lp0ci00x16) 22.97 1316.26 r

rf_store_g1f_int_lmux/z[1] (mux8_16_16) 0.00 1316.26 r

rf_strmux/i2[17] (mux4_32_5) 0.00 1316.26 r

rf_strmux/U333/o (lp0an02x2) 72.33 1388.58 r

rf_strmux/U367/o (lp0no02x4) 31.24 1419.83 f

rf_strmux/U427/o (lp0na02x4) 33.97 1453.80 r

rf_strmux/z[17] (mux4_32_5) 0.00 1453.80 r

eu_dreg_g1f[17] (out) 0.32 1454.12 rdata arrival time 1454.12

Timing Path cntd:


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clock clk (rise edge) 2250.00 2250.00

clock network delay (ideal) 0.00 2250.00

clock uncertainty -450.00 1800.00

output external delay -750.00 1050.00

data required time 1050.00

--------------------------------------------------------------------------

data required time 1050.00

data arrival time -1454.12

--------------------------------------------------------------------------

slack (VIOLATED) -404.12

Report_timing analysis.


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• By default report_timing shows full cell delay annotated to theoutput pin of cell.

•But if you use “–input” option than it also shows delay annotated toinput pin. Snippet:

rf_store_g1f_int_lmux/U189/a (lp0in00x6) 0.51 977.94 r


rf_store_g1f_int_lmux/U192/b (lp0no03x4) 0.20 1003.59 f


• Yet with even more option i.e. “-input” , “-net”, “-cap” “-tran”; itshows nets attached to pins, fanout, capaitive load & transition delayat output pin. Same snippet from above:

rf_store_g1f_int_lmux/U189/a (lp0in00x6) 37.59 0.51 977.94 r

rf_store_g1f_int_lmux/U189/o (lp0in00x6) 18.03 25.45 1003.39 f

rf_store_g1f_int_lmux/net371276 (net) 3 0.01 0.00 1003.39 f

rf_store_g1f_int_lmux/U192/b (lp0no03x4) 18.47 0.20 1003.59 f

rf_store_g1f_int_lmux/U192/o (lp0no03x4) 99.27 85.22 1088.81 r

rf_store_g1f_int_lmux/net281862 (net) 3 0.02 0.00 1088.81 r

Cell Delay Calculation Example


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Fanout Cap Trans Incr Path

rf_ctl/U157/o (lp0cb00x16) 36.46 64.72 977.42 r

rf_ctl/storesell_g1f[2] (net) 7 0.09 0.00 977.42 r

rf_ctl/storesell_g1f[2] (eu_rfctl) 0.00 977.42 r

rf_storesell_g1f_2_ (net) 0.09 0.00 977.42 r

rf_store_g1f_int_lmux/sel[2] (mux8_16_16) 0.00 977.42 r

rf_store_g1f_int_lmux/sel[2] (net) 0.09 0.00 977.42 r

rf_store_g1f_int_lmux/U189/a (lp0in00x6) 37.59 0.51 977.94 r

rf_store_g1f_int_lmux/U189/o (lp0in00x6) 18.03 25.45 1003.39 f

rf_store_g1f_int_lmux/net371276 (net) 3 0.01 0.00 1003.39 f

Degradedinput pinTransition

InterconnectRC

Cell delayannotatedto output

pin

Cap load

Fanoutnumber

Worst delayedge

Transition delayat output pin

Timing Library LookUp Tablecell_fall ("delay_outputslew_template_8X8_r14cip00hx120") {/* Simulation data for spec: ̀ tp_ckb_xy_o_10_min_max' */index_1 ("0.0023242, 0.0464835, 0.0929670, 0.1394510, 0.2324170, 0.3253850, 0.4648350, 0.6972530") ;index 2 ("0 0050000 0 0720000 0 1330000 0 1940000 0 2660000 0 3250000 0 4330000 0 6500000") ;

Understanding a

2D LookUp Table


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index_2 ( 0.0050000, 0.0720000, 0.1330000, 0.1940000, 0.2660000, 0.3250000, 0.4330000, 0.6500000 ) ;values (\"0.0094544, 0.0185783, 0.0214518, 0.0236007, 0.0253379, 0.0262552, 0.0272282, 0.0275904",\"0.0162273, 0.0331686, 0.0396203, 0.0439910, 0.0480818, 0.0509845, 0.0540329, 0.0590189",\"0.0229267, 0.0445651, 0.0545321, 0.0611686, 0.0671197, 0.0700321, 0.0753469, 0.0851278",\"0.0295431, 0.0544924, 0.0670831, 0.0758769, 0.0836995, 0.0867423, 0.0949430, 0.1071260",\"0.0427102, 0.0726367, 0.0882396, 0.1007730, 0.1110430, 0.1172860, 0.1290020, 0.1461220",\"0.0557998, 0.0886394, 0.1074140, 0.1221190, 0.1356480, 0.1436800, 0.1586330, 0.1804830",\"0.0754076, 0.1105390, 0.1338060, 0.1511390, 0.1675510, 0.1777430, 0.1972450, 0.2262090",\"0.1082070, 0.1435670, 0.1730870, 0.1953680, 0.2154180, 0.2272280, 0.2517220, 0.2892730"\);

fall_transition ("delay_outputslew_template_8X8_r14cip00hx120") {/* Simulation data for spec: ̀ tp_ckb_xy_o_10_min_max' */index_1 ("0.0023242, 0.0464835, 0.0929670, 0.1394510, 0.2324170, 0.3253850, 0.4648350, 0.6972530") ;index_2 ("0.0050000, 0.0720000, 0.1330000, 0.1940000, 0.2660000, 0.3250000, 0.4330000, 0.6500000") ;values (\"0.0061389, 0.0186050, 0.0271472, 0.0330667, 0.0409234, 0.0477795, 0.0586398, 0.0787963",\"0.0146870, 0.0298953, 0.0417526, 0.0504997, 0.0592868, 0.0668663, 0.0808903, 0.1052830",\"0.0245473, 0.0410504, 0.0528621, 0.0639379, 0.0748730, 0.0845219, 0.1018660, 0.1263720",\

"0.0340386, 0.0497603, 0.0632419, 0.0754232, 0.0882203, 0.1016720, 0.1160920, 0.1442230",\"0.0525267, 0.0680215, 0.0831561, 0.0963495, 0.1118690, 0.1224300, 0.1423730, 0.1773050",\"0.0711111, 0.0841070, 0.1015420, 0.1170980, 0.1355360, 0.1428940, 0.1648110, 0.2031320",\"0.1012570, 0.1112820, 0.1274450, 0.1473200, 0.1665090, 0.1762910, 0.1964440, 0.2373340",\"0.1467670, 0.1540650, 0.1700650, 0.1904480, 0.2104150, 0.2204380, 0.2469340, 0.2914650"\); Timing Report

Startpoint: FF_1 (r ising edge-triggered flip- flop clocked by clk)Endpoint: out_1 (output port clocked by clk)

Path Group: clkPath Type: max

Point Fanout Cap Trans Incr Path

------ --------------------------------------------------------------------------------------------------

clock clk (rise edge) 0.0000000 0.0000000clock source latency 2.0000000 2.0000000

clk (in) 0.1330000 0.0000000 2.0000000 r

clk (net) 1 0.0400261BUF_1/ckb (r14cip00hx120) 0.1330000 0.0010161 2.0010161 r

BUF_1/o (r14cip00hx120) 0.0831561 0.0875449 + 2.0885611 f

n1 (net) 1 0.2324170

BUF_2/ckb (r14c ip00hx120) 0.0831561 0.0059004 + 2.0944614 f

BUF_2/o (r14c ip00hx120) 0.0300929 0.0325592 2.1270206 r

n2 (net) 1 0.0400261

BUF_3/ckb (r14c ip00hx120) 0.0300929 0.0010161 2.1280367 r

BUF_3/o (r14c ip00hx120) 0.0189827 0.0211189 2.1491556 f

I n d ex _1 I n c r e a s i n g C A P

Index_2 Increasing TRAN

TRAN Index is Column

Selector

CAP Index is Row Selector

2D LookUp Table

Things to look for to debug timing issues.


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• Big delay cells & possible causes.

• Relaistic interface timing constraints.

• Many back2back buffers/inverters.

• Traverse levels of logical hierarchy in path.

• Unrealistically high level of logic cells.

• Revisit compile strategy.

Timing exceptions


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• Timing exceptions are needed to account for non-default behaviourof synchronous paths.– False Paths (FP).

– Multicycle Paths. (MCP).• False Paths (FP):

– Are paths that are free of any timing constraints.

– Consequently such paths are skipped during timing optimization in DC.

– Command “set_false_path” is used to remove/disable timing constraintsfrom a path.

– Correct identification of FP is very critical for quality synthesis & timingclosure.

– Some example of paths that could be declared as false are.

• Cross clock paths i.e paths that are launched and captured by differentclocks that are asynchronous w.r.t each other e.g. clocks with differentfrequencies

• Paths that are functionally never executed or don’t impact designoperation.

– set_false_path –from [get_clocks clk1] –to [get_clocks clk2]


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Multiple Clocks & Virtual clocks


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• In real designs usually there are more than one clock within singleblock or across multiple blocks.

• DC determines and uses the worst case relationship between clock

edges to optimize the path for worst case scenario.

• Virtual clocks are the clocks that are physically non-existent indesign under synthesis but may exist in another block.– Virtual clocks do not have a clock entry port (clock definition point) in the

design being synthesized.

– Virtual clocks are typically used for applying constraints between crossclock paths.

Virtual/Multiple Clock


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ComboCombo ???

3ns

5 ns

in out

CK 1

CK 2

CK 3

0 2010 4030

20151050 25 30 35 40

423528211470

CK 3 (14 ns period)

CK 2 (10 ns period)

CK 1 (20 ns period)

Virtual/Multiple Clock

example

Virtual Clock Example 1:


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• In previous figure which clocks determine worst case setuprelationship???

• What should be the max delay allowed for “yellow” cloud of logicduring synthesis???

– create_clock –name CK1 –period 20000 [get_ports CK1]

– create_clock –name CK2_virtual -period 10000– create_clock –name CK3_virtual –period 14000

– set_output_delay 5000 –max –clock CK3_virtual [get_ports out]

– set_output_delay 3000 –max –clock CK2_virtual -add_delay [get_portsout]

Note: Since block under synthesis does not contain CK2 &CK3 ports, therefore virtual clocks were defined for assigninginterface timing constraint.

Answers to Example:


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• CK1 edge @ 20 ns -> CK3 edge @ 28 ns determines the worst case

relationship.• Logic cloud “yellow” should be synthesized to 3 ns.


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Help & Useful Commands:


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dc_shell-xg-t> help all*

all_clocks # return all clocks in the current design

all_connected # return objects connected to a net, port, or pin

all_critical_cells # return critical cells

all_designs # return all designs

all_dont_touch # Returns all dont touch objects

all_fanin # return pins or cells in transitive fanin

all_fanout # return pins or cells in transitive fanout



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dc_shell-xg-t> help set*

set_clock_latency # set clock_latency

set_clock_transition # set clock_transition

set_clock_uncertainty # set clock_uncertainty

set_ideal_net # set_ideal_net

set_ideal_network # set_ideal_network

set_ideal_transition # set_ideal_transition

set_input_delay # set input_delay

set_output_delay # set output_delay



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• Following gives list of all matching commands:– dc_shell-xg-t> help set*

• Once you know the command, to look at its switches do following:dc_shell-xg-t> set_output_delay -help

Usage: set_output_delay # set output_delay

[-clock clock_name] (relative clock)

[-clock_fall] (delay is relative to falling edge of clock)

[-level_sensitive] (delay is from level-sensitive latch)

• To look at full man page:– dc_shell-xg-t> man set_output_delay

Some helpful solvenet articles on Compilestrategies:


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strategies:

https://solvnet.synopsys.com/retrieve/901881.html



Acknowledgements & References


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• Special thanks to following individuals for proof reading the foils:

– Pokhrel, Khem C (FM)– Gourlay, Stephen (HD)

• References:– Synopsys Documentation.

– Khem Pokhrels STA document.


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fundamental of loic synthesis

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