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FVTX Monthly/Quarterly ReportMarch 2009

Cost Summary

Schedule Summary

Current technical status of each WBS item

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Changes to Management Plan Costs - January

• Cost Savings/Increases of previous Quarters not repeated• Current Expectation is that FNAL will spend ~$90k of $145k on FPHX

Round I prototyping• We are transferring $30k to LANL for FPHX testing, covering part of

Jon K.’s salary (not used by FNAL)• $30k of sensor testing funds transferred to LANL to cover Jon (covered

in baseline)• $40k added to design PCB-version HDI• $40k for Clock and DAQ Interface boards (not explicitly called out from

ROC/FEM previously, so currently include this as added cost)• $37k for ROC FPGA programming and testing added• $61k less spent for Electrical Integration than budgeted in MP

Overall contingency remains approximately the same ($940k) as MP ($927k)

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New Cost Information

• We have our first quote on HDI production: $185k (with 10% spares and assume small HDIs same cost as large)$177k in MP (including contingency)

• HYTEC Design estimate increased by $30k, may increase more when cable routing tasks are added

Overall contingency $908k compared to MP-$927k

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FPHX Prototype tests

• No significant new information since January report (working on preparations for wedge test)

• Gave list of proposed changes to FNAL; they gave preliminary estimate for time to complete work (analog ~1 week, digital may be few weeks)

• Working to make contact with Ray Yarema to determine 2nd round schedule

• FPHX Review scheduled for Thursday afternoon (PHENIX internal)

64 channels unmasked

16 channels pulsed

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FVTX Technical Status - HDI and Sensors

High Density Interconnect, UNM + LANL

• Kapton HDI in shipment• HDI PCB expected end of this week• SiDet prepared to bond to both versions of HDI• LANL test stand prepared to read out 13

chips/connector• Preparing for basic tests of HDI before it goes

to wedge assembly

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FVTX Technical Status - Sensors

• UNM completed verification of Hamamatsu tests – all agreed• UNM will ship few to SiDet for assembling onto HDIs

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FVTX Technical Status - DAQ

ROC board communicating with single FPHX chip, oscilloscope and computer readout.

ROC

FPHX

• ROC board delivered to LANL• Few board re-works needed, but all handled easily at LANL• Successful readout of chip, good calibration data collected. All looks good so far.• 13-chip readout mocked up by fanning out single chip data to 13 inputs• FVTX ROC design in progress• FEM in progress

DATA“13 chips”

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FVTX Technical Status - Assembly• SiDet will assemble first kapton and PCB HDI wedges• SiDet actively working with components that they have• Assembly preparation work at BNL continues• Rapid-prototype cage purchased

Chips placed on HDI Sensor inserted

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Summary

FPHX, sensor tests• LANL/Tom Zimmerman analog tests completed and no major issues• Some issues with beam clock output on large events• Sensor testing all good (strip numbering missing only small issue)

HDI• Preparing for tests of HDI before wedge assembly

Wedge tests • Expect wedge assembly to begin soon• SiDet tested assembly process, small mods to chip placement especially

ROC/FEM • Roc prototype testing underway• Prototype ROC will be used for wedge tests• FEM still behind schedule, but not on critical path