fvtx substrate fea during power outage

FVTX at Power Outage 1

FVTX Substrate FEAduring Power Outage

C. M. Lei

October 06, 2006


Goals

• To use FEA as a design tool to understand if the module and substrate are structurally safe during power outage


The Layup of the Multi-chip Module

Substrate (.12 cf + .38 tpg + .12 cf = .62 mm)


FEA Model

Half Modules with 4 chips

(took advantages of symmetry and all modules evenly positioned)

Bump bond layer were modeled as a continous layer with adjusted properties based on an area ratio 21.33 (with eutectic solder bond diameter 0.035 mm assumed).

Effective Heat flux from ROC = 5.868 mW/mm^2Effective heat flux from sensor = 0.25 mW/mm^2Total heat load = 2.8W for half model

Cooling contact area 5mm wide at +7C


Material Library Used in this FEA

70 # # 292080 # # 343290 # # 3784

100 # # 3984150 # # 3624200 # # 2600250 # # 1960

273.2 # # 1784300 # # 1600350 # # 1352400 # # 1168500 # # 904600 # # 744

Temp in K K in W/m-K

All materials were assumed to be isotropic with constant properties except - TPG in which the thermal conductivity varies- Anisotropic carbon fiber facing and bump bonds

Young’s modulus E, MPa

Poison’s ratio Thermal k, w/m-K

CTE

HDI 30e3 0.30 0.26 17e-6

Silicone glue 2 0.36 0.24 100e-6

Silicon sensor 110e3 0.30 141 2.6e-6

Silicon ROC 110e3 0.30 141 2.6e-6

TPG 83e3 0.20 table -1e-6

Eutectic solder 32e3 0.051 24.7e-6

TPG Thermal K

Carbon fiber 0/90facing:Einplane = 1.48e5 Mpa, Eout-of-plane =7445 Mpa, kinplane = 55.85 W/mK, kout-of-plane = 0.69 W/mK, ainplane = -0.04e-6 ppm/K, aout-of-plane

=30.17e-6 ppm/KEutectic solder bump bond layer: Ex = Ez = 0.15 Mpa, Ey = 1500 Mpa, kx = kz = 0.33e-3 W/mK, ky = 2.38 W/mK, a = 24.7e-6 ppm/K


When heat load = 0, Temperature everywhere is equal to the coolant temperatue at +7C

Heat Load = 0W , Half Model with 4 chips

RESULTS WITH CF/TPG/CF SUBSTRATE 0.62 mm (0.12+0.38+0.12) mm7oC COOLING AT ENDS, POWER OUTAGE with Surrounding Temperature at 0oCSubstrate Glue: 2 Mpa silicone; Module Glue: 2 Mpa silicone


When heat load = 0, Temperature everywhere at +7CMax resultant disp. = 86.8 micronsMax displacement of silicon = 55.3 mircons



Stress Z Plot (out-of-plane 900direction)

TPG LayerMax Resultant Stress = 2.5 MpaMax Stress_Z = 0.1 Mpa

Flexural Strenth = 36.7 Mpa Z = 38.5 Mpa //

Tensile Strength < 0.69 Mpa Z = 6,897 Mpa //

OK!




OK!

Carbon Fiber LayerMax Resultant Stress = 5.3 MpaMax Stress_Z = 0.1 Mpa

Flexural Strenth = 669 Mpa 00

Tensile Strength =1950 Mpa 00

= 28 Mpa 900



OK!

Silicone Glue Layers between HDI and Substrate and between HDI and Module

Max Stress = 0.07 Mpa

Strength_NEE001 = 1.1 Mpa



OK!

HDI Layer


Tensile Strength_Kapton = 166 MpaTensile Strength_Copper = 320 MPa



OK!

Sensor and ROC Layers


Strength_Si = 120 MPa



Bump Bond Layer

Strength of eutect solderTensile Yield = 43 MpaUltimate = 52 MPa

Max resultant stress = 0.383*21.33 = 8.2 Mpa

OK!



Max resultant disp. = 128 micronsMax displacement of silicon = 81.4 mircons

RESULTS WITH CF/TPG/CF SUBSTRATE 0.62 mm (0.12+0.38+0.12) mmNo coolant flow, Power Outage with Surrounding Temperature at 0oCSubstrate Glue: 2 Mpa silicone; Module Glue: 2 Mpa silicone






OK!




OK!




= 28 Mpa 900



OK!






OK!

HDI Layer





OK!






Bump Bond Layer



OK!



Max resultant disp. = 245 micronsMax displacement of silicon = 156 mircons

RESULTS WITH CF/TPG/CF SUBSTRATE 0.62 mm (0.12+0.38+0.12) mmNo coolant flow, Power Outage with Surrounding Temperature at -20oCSubstrate Glue: 2 Mpa silicone; Module Glue: 2 Mpa silicone






OK!




OK!




= 28 Mpa 900



OK!






OK!

HDI Layer





OK!






Bump Bond Layer



OK!



Max resultant disp. = 76.9 micronsMax displacement of silicon = 49 mircons

RESULTS WITH CF/TPG/CF SUBSTRATE 0.62 mm (0.12+0.38+0.12) mmNo coolant flow, Power Outage with Surrounding Temperature at +35oCSubstrate Glue: 2 Mpa silicone; Module Glue: 2 Mpa silicone






OK!




OK!




= 28 Mpa 900



OK!






OK!

HDI Layer





OK!






Bump Bond Layer



OK!



Temperature Settings

Exposed Temperature, C any 0 -20 35

Coolant temperature, C 7 n/a n/a n/a

Temperature Differential caused the cte mismatch, C -14 -21 -41 14

FEA Resultant Displacements

Overall Displacement, microns 87 128 245 -77

Silicon Displacement, microns 55 81 156 -49

FEA Resultant Stress in Mpa

Material Layer Strength, Mpa

TPG, in plane 6897 2.5 3.7 7.1 2.2

TPG, out of plane 0.69 0.10 0.17 0.30 0.07

Carbon Fiber, axial 1950 5.3 7.7 14.8 4.6

Carbon Fiber, lateral 28 0.1 0.2 0.3 0.2

Silicone Glue 1.1 0.07 0.11 0.21 0.07

HDI, effective 166 4.9 7.2 13.7 4.3

Silicon 120 3.3 4.8 9.3 2.9

Bump Bond, effective 43 8.2 12.0 23.0 7.2

Summary of Results


Remarks

• when power supply to chips is off but coolant is still running, substrate and modules are all in coolant temperture 7C . This is bascially independent on surrounding temperature. (if possible, the coolant temperature should be set back to room temperature to eliminate any thermal effects.)

• When power supply to chips is off and coolant is not running, substrate and modules are all basically at the same temperature as of the surrounding.

• All stresses were within the tensile range when surrounding temperature was between -20C and +35C.

• FEAs were done based on an assumption that a compliant low-modulus (E = 2 Mpa) adhesive can be used. Results would be different if the final choice of adhesives are different.

fvtx substrate fea during power outage

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