high multiplicity fvtx trigger for run15
TRANSCRIPT
High Multiplicity FVTX Trigger for Run15
Toru Nagashima, Yomei Fukushima
(Rikkyo University)
Shoichi Hasegwa
(J-Parc)
Itaru Nakagawa
RIKEN
and
FVTX Group
1
Jan. 19 RadLab meeting
OVERVIEW
• FVTX trigger design
•Hardware status
• Software status
2
#track>5track/east
AND
EAST
WEST
Δφ=15°
limitedto1bit
#hits>3/4sta ons
#hits>3/4sta ons
OR
#track>5track/west
FEM-IBFPGA
FEMFPGA
TRIGGER
3
• At least one hit in 3 out of 4 stations is required within a half sector ((Df=7.5o). -> TrackFlag.
• If there are more than two tracks within a given sector (Df=15o), the second one won’t be counted.
We Request Two Trigger bits (one per arm) for FVTX trigger.
Limited to 1bit
Mainly developed by Aaron Key (UNM)
Mainly developed by Toru Nagashima
FEM – FEMIB Cable
4
FEM end
FEM-IB end
FEM FEMIB
Visual scaler
test signal
The serial line cable
# of FEMIB trigger
# of FEM trigger= 100%?
Signal transmission test
7
Signal transmission test
6
Signal rate #FEMIB trigger/#FEM trigger
3kHz 100%
300kHz 100%
4.7MHz (BCO/2) 100%
Worked well up to 4.7MHz as long as the cable is connected to the test pin properly.
FEM Trigger
FEM-IBTrigger
Discri.
TTL->ECL
ECL-> TTL
RB
IB
GL1
BCLK 0 9 14 17~18
collision
1 B
CLK
pro
cess + 4
BC
LK w
ind
ow
1 B
CLK
pro
cess+ 1
BC
LK M
ulit
FEM w
ind
ow
+ 1 B
CLK
latch+ d
elay
20
FVTX Trigger Timing Chart
7
To be tested in 1008
BCLK
Trigger for GL180ns
Delay
For timing adjustment
Trigger signal = 573Hz
8
Delay Accepted rate
0ns 573Hz
20ns 573Hz
30ns 572Hz
40ns 364Hz
50ns 0Hz
60ns 0Hz
GL1 didn’t recognize the signal depending on the timing. Need to adjust using another subsystem(MPC, BBC etc.)
BCLK
Trigger for GL1
Wedge trigger logic
9
Hit counter
# of hit/event > threshold?
“active” flagYES
NO
FEM FPGA
Efficiency =# of trigger
# of hits > threshold
1wedge
# of hits/event
Trig
ger
stat
e Trigger threshold
#hits vs #trigger
Trigger threshold
Efficiency ~ 94%
# of hits/event
# o
f tr
igge
r/ev
ent
10
6% inefficiency?
Trigger threshold
# of hits/event
# o
f tr
igge
r/ev
ent
11
Trigger turn onTriggerthreshold
Fire
d e
ven
t/N
ot
fire
d e
ven
t
The trigger threshold works as #hits>thresh. rather than #hits>=thresh.Turned out it doesn’t work when the threshold = 0. Need to be debugged.
Ongoing study
• External trigger parameter control.
• New Expert GUI for FVTX.
• Input the trigger information into the data stream from the FEM.
13
Test plan
• Timing tune with BBC- Using the BBC laser pulse- Or wait for the beam?
• Cosmic- need to setup the DAQ- MuID will be used as a trigger.- few Hz of the trigger rate is expected.
• Trigger logic test- Consistency check between the trigger logic & trigger rate. The severer, the few the rate should be.
14
Summary• Signal transmission test- No issue was observed for now, up to 4.7MHz.
- Need to adjust the timing using BBC trigger.
• Trigger efficiency- Turned out the threshold worked 1hit more than expected. Need
to debug since we need #hit>=1 for the multi track algorithm.
• Test in 1008- FEMIB & FEM FPGA is ready. Will start testing once the Expert
GUI to control the trigger logic.
- Trigger timing adjustment & trigger logic will be tested using the cosmic.
15
Backup
16
FVTX Readout
17
FPGA
Slow
Co
ntro
l
All hits are sent to FEM
regardless of trigger request
FEM
FEM-IB
FVTX Trigger Design
18
FPGA
Slow
Co
ntro
l
FEM-IB
Raise a “track flag” if track like hit pattern
is found.
Track flag
TRIGGER GL1
If the number of flagged FEMs are more
than threshold, then issue a trigger
FEM
Signal transmission test
FEM FEMIB
oscilloscope
19
High frequency (300kHz) signal
0 state signal
No cross talk was observed as long as the cable is connected to the test pin properly.
Twisted cable
FEM – FEMIB cable test
• If the cable is not connected to FEM side, it picks up the noise. Works as a kind of antenna?
20
FEMIB
Open
21
To be tested in 1008
Output clock signal from FEMIB, and checked the frequency GL1 accepted.
FEM Trigger
FEM-IBTrigger
Discri.
TTL->ECL
ECL-> TTL
RB
IB
GL1
BCLK 0 9 14 17~18
collision
1 B
CLK
pro
cess + 4
BC
LK w
ind
ow
1 B
CLK
pro
cess+ 1
BC
LK M
ulit
FEM w
ind
ow
+ 1 B
CLK
latch+ d
elay
20
FVTX Trigger Timing Chart
22
To be tested in 1008