half adder workbook
TRANSCRIPT
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7/31/2019 Half Adder Workbook
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Digital System DesignHalf Adder
Department of Electronics Engg., P.V.P.I.T., Budhgaon
(Entity Level)
(Architectural Level)
Inputs Outputs
0 00 11 01 1
a s h_adder
b c
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7/31/2019 Half Adder Workbook
2/4
Digital System DesignHalf Adder
Department of Electronics Engg., P.V.P.I.T., Budhgaon
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7/31/2019 Half Adder Workbook
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Digital System DesignHalf Adder
Department of Electronics Engg., P.V.P.I.T., Budhgaon
a. Device Family :
b. Device :
c. Package Pins :
d. Speed Grade :
a. ISE Simulator
b. Model-Sim Simulator
a. XST synthesizer
b. Leonardo Spectrum
(Names Only)
a.
b.
c.
d.
e.
f.
a. Slices : ____ out of _______ ______ Percent
b. I/O Blocks : ____ out of _______ ______ Percent
c. Look Up Tables : ____ out of _______ ______ Percent
d. Flip Flops : ____ out of _______ ______ Percent
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7/31/2019 Half Adder Workbook
4/4
Digital System DesignHalf Adder
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Pins Description:
a
b
s
c
2.
a. Maximum Pad to Pad Delay :
a. Maximum Power Dissipation :
b. Static Timing Report: