hazards in cmos circuits

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Hazards in CMOS circuitsSREELA SASI a b & DAMU RADHAKRISHNAN aa Department of Electrical Engineering , University Idaho , Moscow, ID 83843, U.S.A.b Department of Computer Science , University of Kerala , Trivandrum, Kerala, IndiaPublished online: 24 Feb 2007.

To cite this article: SREELA SASI & DAMU RADHAKRISHNAN (1990) Hazards in CMOS circuits, International Journal ofElectronics, 68:6, 967-990, DOI: 10.1080/00207219008921238

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Hazards in CMOS circuits

SREELA SASItS and DAMU RADHAKRISHNANt

This paper addresses both the detection and elimination of hazards in different configurations of CMOS circuits. The analysis of hazards in combinational circuits using logic gates and their hazard-free designs have already been treated in detail in many standard text books. However, the current trend in the design of switching circuits have shifted from the mere interconnection of logic gates to more complex networks of MOS transistors. This necessitates the analysis of hazards in CMOS and pass networks, and their elimination in these networks. This paper gives the necessary and sufficient conditions for the presence of hazards in CMOS networks. The presence of hazards have been verified using SPICE simulation. Different methods of eliminating hazards in these networks are presented. In addition, new design techniques for the hazard-free design of optimal CVSL circuits are also given in this paper.

1. Introduction

CMOS is one of the leading technologies of today for the design of VLSI circuits. A large variety of CMOS networks is available. These networks are all designed based on certain idealized assumptions regarding the operation of the MOS switches. The transistors are assumed to respond instantaneously to input signals and the signal propagation time is assumed to be zero. In practice, however, the delays associated with switching components cause non-instantaneous changes of states, which in turn may result in hazards.

A hazard is a situation in which a single input variable change might cause a momentary incorrect output, when in fact the output should remain constant. Whether o r not such an incorrect output actually occurs in a CMOS circuit depends not only on the exact amounts of delay associated with the various circuit elements, but also on whether there exists a path to pull up the output to supply voltage or to pull it down to ground. These hazards are of no concern in the design of synchronous sequential circuits. However, with the trend towards miniaturization and faster operation, asynchronous designs are gaining much popularity in VLSI designs. In these designs hazards play a major role. Hence a detailed study of hazards and ways of designing hazard-free circuits in CMOS gate networks are treated in this paper.

2. CMOS gate networks

CMOS gate networks in general consist of two separate networks, one to pull-up the output to logic 1 and the other to pull down the output to logic 0, as shown in Fig. 1. The pull-up network is connected between the output node and V,, and is purely a PMOS network (P-net) to pass good '1's to the output. The pull-down network on the other hand is connected between the output node and V,

Received 19 October 1988; accepted by P. A. Lindsay, 5 December 1989. t Department of Electrical Engineering, University of Idaho, Moscow, ID 83843, U.S.A. f Department of Computer Science, University of Kerala, Trivandrum, Kerala, India.

0020-7217190 S3.W 1990 Taylor L Francis Ltd.

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S. Sasi and D. Radhakrishnan

Vss 4 Figure 1. CMOS gate network.

and is purely an nMOS network (N-net) to pass good '0's to the output. Thus CMOS gate logic networks are a special class of CMOS pass networks with the pass variables restricted to either '0's or '1's (Radhakrishnan et al. 1985). A number of CMOS configurations exist today which include: CMOS complementary logic, pseudo-nMOS logic, dynamic CMOS logic, domino logic, and cascade voltage switch logic (CVSL) (Krambeck et al. 1982, Weste and Eshraghian 1985). Since hazards are of no concern in clocked circuits, only CMOS complementary logic, pseudo-nMOS logic, and static CVSL logic are treated further in this paper. For a more clear understanding, some of the notation and definitions used throughout this paper are given next.

2.1. Notation and definitions

f represents the switching function of a network f(1) partial pass function obtained by combining the '1's of the function f(0) partial pass function obtained by combining the '0's of the function f boolean expression for the P-net; this is obtained from f(1) by dropping the

pass variable 1 and complementing all the literals f, boolean expression for the N-net; this is the same as f(0) with its pass

variable 0 removed

The following relationships are valid for switching functions:

A pass transistor is an nMOS or PMOS transistor used to block or conduct logic signals in MOS circuits.

Definition 2

A pass network is the interconnection of a set of pass transistors to achieve a particular switching function.

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Hazards in CMOS circuits 969

A pass implicant Pi(Q represents a series connection of transistors passing the signal V( with Pi representing the product of the variables controlling the transistors. The pass variable V( can be 0, 1, Xi, or Xi.

A pass implicant P,(VJ can be obtained from the K-map as follows:

Step 1. 2' cells in the K-map, each cell in the implicant has 'i' adjacent cells in the implicant. The product term defining the implicant is identical with the tra- ditional implicants.

Step 2. The pass variable % is equal to one of the element 0, 1, X,, or Xi. 5 must be equal to one of these elements throughout the implicant.

Any switching function f can be represented in pass notation as a sum of pass implicants by:

Definition 4

A pass prime implicant is a prime implicant which subsumes no other pass implicant having fewer literals which imply the function.

Definition 5

A complementary sum (CS) is defined as Si = PAX,) + P;(X,), where Xj and X, are either pass variables or complementary sums by themselves.

Definition 6 A binary tree structured pass network (BTS) is defined as a pass network in which

exactly two branches join at every node, and the control term of one branch is the complement of the control term of the other branch.

A BTS pass function is a special case of a complementary sum Si, where Si denotes the switching function f (Feizi and Radhakrishnan 1985). Design procedures for BTS pass networks are given by Peterson and Maki (1984).

The notion of pass implicants is very important in the minimization of pass networks in the same manner as prime implicants are in the minimization of gate networks. A minimal pass function includes all essential pass prime implicants and, in addition, a minimal set of pass prime implicants to cover the function. For a thorough discussion on pass networks the reader is referred to Xadhakrishnan et al. (1985).

2.2. C M O S complementary logic

It consists of two full blown networks-a P-net and an N-net. Each of these networks can be obtained from the K-map. Three different realizations are possible for CMOS complementary gates (Weste and Eshraghian 1985). They are:

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970 S. Sasi and D. Radhakrishnan

( I ) design the N-net and the P-net separately from f(0) and f(1) respectively,

(2) design the N-net from f(0) and its dual for the P-net, or

(3) design the P-net from f(1) and its dual for the N-net.

2.3. Pseudo-nMOS logic

Pseudo-nMOS logic consists of an N-net passing the '0's of the function and a P-net consisting of a single PMOS transistor passing the '1's of the function, as shown in Fig. 2. The N-net can be designed in two different ways; one by finding the N-net expression fN by complementing the switching function f, and the other by taking the dual of the P-net expression fp. In both cases, the pull-up transistor stays the same.

2.4. Cascade voltage switch logic (CVSL)

The basic form of this type of gate is a fully differential network which consists of two complementary nMOS networks connected to a pair of cross-coupled PMOS pull-up transistors as shown in Fig. 3. The N-networks may be further minimized from the fully differential form using logic minimization algorithms. This structure is slower than the conventional CMOS complementary gate employing a P-net and an N-net.

As in the CMOS complementary logic, three different realizations are possible for a fully differential CVSL network. The two N-networks realizing the function are labelled as N, and No in Fig. 3. Their corresponding logic expressions are denoted by fN, and IN,, respectively. fN, can either be obtained from f(0) by simply dropping

vss & Figure 2. Pseudo-nMOS gate.

Figure 3. Fully differential CVSL gate,

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Hazards in C M O S circuits 97 1

the pass variables or from f(1) by dropping the pass variables and complementing the expression. In a similar manner f,, can be obtained either from f(1) or from f(0).

The transistor count for a CVSL structure can be reduced using pass logic design techniques (Sasi 1988). As a first step in this procedure a minimal pass function is found. The following procedure can now be used to form a CVSL gate with outputs f and f'.

Procedure 1

Step 1 . For i = 1 to n, select the pass implicant P i ( v ) ,

Step 2. If = 0, then form a series nMOS network for Pi between f and Vs. If I( = 1, then form a series nMOS network for Pi between f ' and V,. If 6 = X, then form a series nMOS network for Pi from V, and connect i t to f and f ' through transistors controlled by X' and X respectively. If 1/;. = X', then form a series nMOS network for P i from Vss and connect it to f ' and f through transistors controlled by X' and X, respectively.

Step 3. Repeat step 1.

A modified scheme for the implementation of the CVSL gate is by using BTS pass networks. The procedure for the implementation of a CVSL gate using BTS pass functions is given below.

Procedure 2 Step 1 . Form the BTS pass network for the function.

Step 2. Connect the output node to V,

Step 3. Connect each input node of the pass network to either f or f ' using the following criteria. ( a ) If the pass variable is 0, then connect the input node to f. (b) If the pass variable is 1, then connect the input node to f'. (c ) If the pass variable is X(X'), then connect the input node to f(f ') through

a transistor controlled by X' and to f'(f) through a transistor controlled by X.

The following example illustrates the design of a static CVSL gate using Pro- cedure 2.

Example 1

A three variable K-map is shown in Fig. 4. The BTS pass function corresponding to this K-map is given by:

f = A(B(C) + B(C)) + A(B(C) + B(C))

The BTS pass network and the corresponding CVSL implementation are also given in Fig. 4.

Except in a few special cases (XOR functions), BTS networks use the minimum number of transistors to realize a switching function. For XOR functions it was found that factoring the function by taking the largest complementary sum Si gives the minimum number of literals in its expression. These functions when used to

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Figure 4. CVSL realization from a BTS pass network. (a) BTS pass network; (b) CVSL network. f = A(B(C) + B(C)) + A(B(C) + B(C)).

implement CVSL gates use the minimum number of transistors. However, a search for an example that uses fewer transistors than the above design has been unsuc- cessful. Hence the following conjecture.

Conjecture 1

CVSL design using a modified version of BTS pass networks that use variable sharing gives minimal transistor realization.

3. Hazards in CMOS networks

Hazards occurring in switching circuits are treated in many books (McCluskey 1965, Klir 1972, Kohavi 1978). They occur in the combinational part of a logic network and can be eliminated either by hardware redundancy or by the addition of delay elements. The following definitions are taken from the literature.

Definition 7 A P set (S set) of a switching circuit with respect to a particular output variable

of the circuit is any minimum subset of input variables such that when each variable in the set is equal to 1(0), the respective output variable is equal to l(0) independent of the values of the other variables.

The P sets and S sets for a logic network are formed by subscripted literals indicating the path labelling in the network.

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Definition 8 A P set (S set) that does not contain any pair of complementary literals will be

I called a stable P set (stable S set).

Definition 9

A P set (S set) that contains at least one pair of complementary literals will be called an unstable P set (unstable S set).

Definition 10

The set that results when the subscripts are removed from the literals of a P set (S set) and then repetitions of the same literals are removed will be called a I set (0 set).

Definition 11

A hazard is a potential or actual malfunction of a switching circuit during the transition between two input states.

The existence of a hazard does not necessarily mean the occurrence of a malfunction in the network. The actual behaviour due to the presence of a hazard depends on the duration of the spurious signals and the devices that receive them.

The basic assumptions made in the following discussion on hazards are as follows.

Assumption 1 . The components in the switching circuit do not produce any bounce signals.

Assumption 2. The inputs to the network are changed only when the network is in a steady state.

Assumption 3. The output capacitance of the network is higher than its internal node capacitances.

The different kinds of hazards occurring in switching circuits are mainly charac- terized into three types: static hazards, dynamic hazards and essential hazards. Static and dynamic hazards occur in combinational logic circuits, whereas essential hazards occur in asynchronous sequential circuits. The detection and elimination of static hazards in gate networks and relay networks are treated by McCluskey (1965). Even though CMOS gate networks resemble relay networks in many respects, the procedures available for the design of hazard-free relay networks are not fully applicable to the design of hazard-free CMOS networks. Only static and dynamic hazards are pursued further in this paper.

3.1. Static hazards

Definition 12

A static hazard in a switching circuit is a transient change of an output value that is supposed to remain fixed during a transition between two adjacent input states. When the output is to remain at the value l(0) and a momentary q1) output is possible during the input transition, the hazard is called a static l(0) hazard.

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Since there are many different realizations for CMOS complex gates, the detection and elimination of hazards in these networks differ.

Theorem 1

A static 1 hazard exists in a CMOS complementary gate if and only if the following conditions are satisfied.

(1) The P-net and N-net are duals of each other

(2) There is a P set of the function fN,

K , = {a:, b:, ..., X i , X i , .. ., $1 in which the same variable may appear with different (multiple) subscripts but exactly one variable (X) appears both complemented and uncomplemented.

(3) There is at least one pair of (adjacent) input states satisfying the following. (a) Both input states produce 1 outputs. (b) The variable X is equal to 0 for one of the states and equal to 1 for the

other state of the pair. (c) Each other (non-X) literal of K , is equal to I for both input states.

Proof First, sufficiency of the theorem will be proved; that is, it is shown that if the

conditions of the theorem are satisfied then there will be a static 1 hazard present. Conditions 1, 2, 3(a), and 3(b) guarantee that the P-net has at least two parallel branches between the output node and V , , , one with X i and the other with X i in it. If the network is now placed in one of the input states satisfying condition 3(a) for which X = 0, all the subscripted literals of K, except X i will become equal to 1 before any further input changes. (This is true because of condition (3) and because it is assumed that an input variable is not changed until all previous input changes have propagated through the network.) Since the P-net and the N-net are duals of each other, this guarantees that there is no closed path in the P-net other than the one with X i in it. If X is now changed to 1, it is possible for X i to become equal to 1 before X; becomes equal to 0. If this happens, all the literals of K, are equal to 1, and hence a closed path exists in the N-net between output node and V,. At the same time in the P-net the path through X i opens. Since X ; changes more slowly and is still equal to 1, the P-net is open producing a momentary 0 output. Even- tually X; will become equal to 0, thereby opening the N-net and closing the P-net which in turn produces a 1 output. Thus, if the conditions of the theorem are satisfied, it is possible to have a spurious 0 output depending on the sequence in which Xi and Xi change.

In order to prove the necessity of the theorem, it will be assumed that a static 1 hazard exists. Thus there must be two adjacent input states, which both produce 1 outputs, such that during a transition between these two states a spurious 0 output may be produced. Let the variable in which these input states differ be X.

The spurious 0 output requires that the network contain a P set in fN with the following properties.

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Property 1 . Each variable which is equal to 0 for the pair of input states must either be absent from the P set or must only appear complemented.

Property 2. Each variable which is equal to 1 for the pair of input states must either be absent from the P set or must only appear uncomplemented. If a variable that is equal to q 1 ) for both input states appeared uncomplemented (complemented) in the P set, it would not be possible for all literals in the P set to be equal to 1 during the transition between the two input states and consequently there could be a closed path in the N-net to produce a 0 output during the transition.

Property 3. If only the literals specified by conditions (1) and (2) were to appear in the P set, all literals of the P set would be equal to 1 for both input states, thus keeping the N-net closed in both the input states. This cannot be, because it was assumed that both input states produce 1 outputs (which means the P-net is closed and the N-net is opened). If either X or X' were to appear in the P set, all literals of the P set would equal to 1 for one of the input states. The only way to have at least one literal of the P set equal to 0, for each input state of the pair of adjacent input states and still satisfy conditions (1) and (2) is to have both X and X' appear in the P set. If another variable such as Y appeared in the P set, both complemented and uncomplemented, it would not be possible to have all literals of the P set equal to I during a single input variable change. When only one variable is changing, only one pair of complementary literals can both equal 1. Conditions (I), (2) and (3) are the same conditions as are given for the P set K , of the theorem. In addition a spurious 0 output implies that the N-net is temporarily closed and the P-net is temporarily opened. This will occur during a transition on X only if no closed paths exist in the P-net during this transition. This implies that there are at least two parallel paths in the P-net, one with Xi in it and the other with Xi in it so that the output will be 1 for both the input states with X = 0 and X = 1. The P set K , and the above conditions will be satisfied only if the P-net and the N-net are duals of each other. Hence the necessity of the theorem is proved.

Theorem 1 is true for static 0 hazards by changing fN tof, in condition (2) and replacing the output to 0 for both input states in condition 3(a). Similarly, the necessary and sumcient conditions for static 1 hazards in pseudo-

nMOS gates is given by Theorem 1 if we delete condition 1. If the changes made for static 0 hazards in CMOS complementary gates are

included in the above, they give the necessary and sufficient conditions for static 0 hazards in pseudo-nMOS gates.

Theorem 2

A static 1 hazard exists in a fully differential CVSL gate only if the following conditions are satisfied.

(1) The two N-nets N, and No are complements of each other.

(2) There is a P set K , of the function fN, and an S set K O of the function fN, in which the same variable may appear with different (multiple) subscripts but

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exactly one variable (X) appears both complemented and uncomplemented, where

K , = {a:, b:, ..., Xi, X i , .. ., 2:)

and

K O = {A: , B:, . . ., Xi, X i , ,. . , 2:) (3) There is at least one pair of (adjacent) input states satisfying the following.

(a) Both input states produce 1 outputs. (b) The variable X is equal to 0 for one of the states and equal to 1 for the

other state of the pair. (c) Each other (non-X) literal of K , is equal to 1 and equal to 0 for K O for

both input states.

Proof

In order to prove this theorem, it will be assumed that a static 1 hazard exists. Thus there must be two adjacent input states, which both produce 1 outputs, such that during a transition between these two states a spurious 0 output may be produced. Let the variable in which these input states differ be X.

The spurious 0 output requires that the network contain a P set infNo and an S set in f,, with the following properties.

Property 1. Each variable that is equal to O(1) for the pair of input states must either be absent from the P set (S set) or must only appear complemented.

Property 2. Each variable that is equal to l(0) for the pair of input states must either be absent from the P set (S set) or must only appear uncomplemented. If a variable which is equal to O(1) for both input states appeared uncomplemented (complemented) in the P set, it would not be possible for all literals in the P set to be equal to 1 during the transition between the two input states and consequently there cannot be a closed path in N o to produce a 0 output during the transition. Similarly, if a variable which is equal to q 1 ) for the pair of input states appeared complemented (uncomplemented) in the S set, it would not be possible for all literals in the S set to be equal to 0 during the transition between the two input states and consequently there cannot be an open path in N , during the transition.

Property 3. If only the literals specified by conditions (1) and (2) appeared in the P set (S set), all literals of the P set (S set) would be equal to l(0) for both input states thus keeping N o closed and N , opened in both the input states. This cannot be, because it was assumed that both input states produce 1 outputs (which means N , is closed and N o is opened). If either X or X' appeared in the P set (S set), all literals of the P set (S set) would equal to l(0) for one of the input states. The only way to have at least one literal of the P set equal to 0, for each input state of the pair of adjacent input states and still satisfy conditions (1) and (2) is to have both X and X' appear in the P set. Similarly, for f,, to be 0 during the transition and 1 in each input state of the pair of adjacent input states

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and still satisfy conditions (1) and (2) is to have both X and X' appear in the S set. If another variable, such as Y, were to appear in the P set (S set) both complemented and uncomplemented, it would not be possible to have all literals of the P set (S set) equal to l(0) during a single input variable change. When only one variable is changing, only one pair of complementary literals can both equal l(0). Conditions (I), (2) and (3) are the same conditions as are given for the P set K , and S set K O of the theorem. The temporary closing of N o and opening of N , during the transition on X implies that there are no closed paths in N , during this transition. This implies that there are at least two parallel paths in N , , one with Xi in it and the other with Xj in it, so that the outputs will be 1 for both the input states with X = 0 and X = 1. The P set K , , the S set K O , and the above conditions will be satisfied only if N , and No are complements of each other. Hence the necessity of the theorem is proved. 0

Theorem 2 is valid for static 0 hazards with the following changes.

Change 1. Condition (2), may be changed to the 'P set K , of the function f,, and S set KO of the function f,,'.

Change 2. Condition 3(a) with 0 outputs for both input states.

3.2. Dynamic hazards

Definition 13

A dynamic hazard is a transition between a pair of adjacent input states, one of which produces a 1 output and the other of which produces a 0 output, during which transition it is possible for a momentary 0 output and a momentary 1 output to occur.

All the theorems used for finding dynamic hazards in gate logic (McCluskey 1965) are also valid in the case of CMOS circuits. The essential conditions for the occurrence of dynamic hazards in CMOS circuits is that there should be three or more signal paths for the same variable, each path having transistors with different delays in switching times. Because of the differences in transistor sizes and junction capacitances at different nodes in the circuit, the switching delays may be different for different transistors in the circuit. This may cause the occurrence of potential dynamic hazards in CMOS circuits.

In CMOS complementary gates the necessary condition is that during the switching of a variable the N-net and P-net should follow the sequence closed-open- closed-open and open-closed-open-closed, respectively, or vice versa. If both N-net and P-net are closed simultaneously at any instant during the transition, then there arises a conflict in the circuit which then determines the occurrence of a dynamic hazard in the circuit. The following theorem is a modified version due to McCluskey (1965).

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Theorem 3 A dynamic hazard exists in a C M O S complementary network, with an N-net as

the dual of a P-net, or vice versa, only if the following conditions are satisfied.

(1) The following P sets and S sets exist in the circuit. (a) An unstable P set of the network (The symbols a*, b*, etc., represent

literals. The symbol x: also represents a literal, but the '+' symbol is consistent in referring to a prime or to no prime. That is, if xi = x i , then x: = x , and ( x f ) ' = xi; or if x: = x i , then x: =x;, (x f ) '= (x ; . ) '= x i , etc.):

(b ) An unstable S set of the network

(c ) A stable P set of the network

(d) A stable S set of the network

(2 ) These P sets and S sets satisfy the following conditions. (a) None of these P sets and S sets contain any pairs of complementary

literals other than those explicitly shown. (b) The underlined literals must be present. The presence or absence of the

literals that are not underlined will have no effect on the existence of a dynamic hazard.

(c ) The two P sets can have literals in common, and the S sets can have literals in common, but no P set can have any literals in common with any S set except for the common literals shown explicitly.

(4 No literal can occur complemented in one P set (S set) and uncomplemented in the other P set (S set) except for those shown explicitly.

(e) Any literal may occur complemented in one or both of the P sets and uncomplemented in one or both of the S sets, or vice versa.

ProoJ To show the necessity of the theorem it will be assumed that a dynamic hazard

exists for a pair of adjacent input states differing only in the value of the X variable. The existence of a dynamic hazard requires that the network output changes for this transition. Let us assume an output transition from 1 to 0 for an input transition of X+ from 1 to 0. The following sequence of events must occur in the network during the transition.

Step I. The P-net is closed and the N-net is open for X C = 1.

Step 2. The P-net opens and the N-net closes when X + is changed to 0.

Step 3. The N-net opens and the P-net closes.

Step 4. The P-net opens and the N-net closes.

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The multiple occurrences of the same variable are denoted using subscripted variables X i , X j , and X , . When X + is changed to 0 it is assumed that the signals change in the following sequence: X: -+ 0, X f -+ 0, X: + 0. Conditions (1) and (2) above are satisfied only if the P-net is closed through a transistor controlled by (X,?)' and all other paths are open for this input state. Also in the N-net there is a path only through (X:)' which closes for X + = 0 while all remaining paths are open. Condition (3) requires that the previous closed path in the N-net be through a series path consisting of (X:)' and X f and the P-net has a closed path through X f which is in a path parallel to the one through ( X l j ' . Condition (4) requires that the above closed path in the P-net be through a series path with X f and (X:)' in it and the N-net must have a closed path with (X:)' and (X:)' in series.

The above requirements imply the necessity of condition 1 of the theorem. The conditions (a) to (e) of condition (2) of the theorem follow directly from the fact that this is a transition between a pair of adjacent input states, and all the P sets and S sets must be effective at some time during the transition.

Similarly, by considering a dynamic hazard during an output change from 0 to 1, a CMOS complementary network can be derived in which the P-net and N-net are duals of the ones derived above. 0

Theorem 4

A dynamic hazard exists in a pseudo-nMOS network if and only if the following conditions are satisfied.

(1) The following P sets and S sets exist for the function f ; : (a) An unstable P set of the function

K l = {. . . , a: , . . . , x:, (x,?)', (xl) '} -- (b ) An unstable S set of the function

KO = { ..., b:, ..., (x:)', d , ( x f ) ' } - (c ) A stable P set of the function

L, = { ..., c: ,..., x : , x f , x , C }

(d) A stable S set of the function

L o = { ..., d:, ..., - x : , x f , x l }

(2) Same as condition (2) in Theorem 3.

Proof First suficiency will be demonstrated by showing that a dynamic hazard is

present if the conditions of the theorem are satisfied. Consider an N-net in which there are nMOS transistors controlled by (X:)',

(X:)', and X f , such that (X:)' is in series with a parallel network with (X:)', and X f in their two different branches. Since the output changes during the transition on X between the two adjacent input states, it follows that there is only one closed path in the N-net between the output node and V' for X + = 0, and all other paths, if any, existing in parallel to the transistor controlled by (X:)' are open for both the

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input states. The network is placed in the input state for which X + = 1, all the remaining (non-X) literals of the P sets, K , and L,, are equal to 1, and all the remaining (non-X) literals of the S sets, KO and L o , are equal to 0. The circuit output must equal 1 for this input state because all the literals of the P set L , are equal to 1. The N-net is open because of the transistor controlled by (X:)'. The input X f is now changed to 0, and it is assumed that the signals change in the following sequence: X: -+ 0, Xf + 0, X+ + 0. When X: becomes equal to 0, the P set L , is no longer effective, but the S set KO has all its literals equal to 0, and therefore the circuit output becomes equal to 0. Under this condition, the N-net is closed through Xf, and (X:)'. The S set KO becomes ineffective when Xf changes to 0, but the P set K , then becomes effective, causing the circuit output to equal 1. For this case the N-net is open because of the transistors controlled by X f , and (X:)'. Finally, X+ changing to 0 makes K , ineffective, the S set Lo effective, and the circuit output equal to 0. Now the N-net is closed through (X:)' and (X:)'. Thus if the signals change in the order specified above, two spurious outputs will be developed during this transition. Similarly it can easily be verified that an N-net structure that is the dual of the above mentioned N-net can also cause a dynamic hazard.

The proof of the necessity of the theorem can be carried out along similar lines to the proof of Theorem 3. 0

Theorem 5 A dynamic hazard exists in a fully differential CVSL network, with No and N,

as complementary networks, only if the following conditions are satisfied.

(1) Same as Theorem 3.

(2) Same as Theorem 3.

Proof The proof of this theorem is similar to the one given for Theorem 3. The differ-

ence is in the network N , , whose network structure is the same as the P-net in a CMOS complementary gate with complementary literals.

4. Hazard free designs

This section deals with design techniques for CMOS complex gates so that the circuits, once designed, are free of hazards.

4.1. Static hazard elimination

Theorem 6 A CMOS complementary gate designed from f(l) for a P-net and its dual for an

N-net contains no static 0 hazards. Similarly, a CMOS complementary gate designed from f(0) for an N-net and its dual for a P-net contains no static 1 hazards.

Proof

If f(1) is obtained from the K-map, there will be no unstable 1 sets and hence no static 0 hazards in the network. However, if the conditions of Theorem 1 are satis-

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Hazards in CMOS circuits 98 1

fied then there may be a static 1 hazard in the network. Similarly if f(0) is obtained from the K-map, there will be no unstable 0 sets and hence by Theorem 1, no static 1 hazards exist in the network, but there may be static 0 hazards.

Corollary 1

A CMOS complementary gate designed from f(1) and f(0) for a P-net and an N-net, respectively, is static hazard-free.

Proof The function f(1) derived from the K-map will have no unstable 1 sets. Similarly,

the function f(0) derived from the K-map has no unstable 0 sets. Hence, by Theorem 6, the circuit is static hazard-free.

Corollary 2 The minimal transistor implementation of a CMOS complementary gate does

not always guarantee hazard-free design.

Proof A minimal transistor realization of a CMOS complementary gate can be

obtained in three different ways depending on the given function.

Case 1 : The number of literals in f(1) and f(0) are equal Implement a P-net using f(1) and an N-net using f(0). According to Corollary 1

this design is hazard-free.

Case 2 : The number of literals in f(1) is less than the number of literals in f(0) Implement a P-net from f(1) and take its dual for an N-net. By Theorem 6, there

are no static 0 hazards. However, if it satisfies the conditions of Theorem 1, then static 1 hazards will be present in the network.

Case 3: The number of literals in f(0) is less than the number of literals in f(1) Implement an N-net from f(0) and take its dual for a P-net. As in Case 2, by

Theorem 6 there are no static 1 hazards but there can be static 0 hazards.

Corollary 3

A minimal transistor implementation of a CMOS complementary gate can always be made hazard-free by the addition of redundant transistors.

Proof

We prove this by exhibiting a synthesis technique for realizing a hazard-free network by adding redundant transistors. From Corollary 2, if the minimal transistor implementation falls under Case 1, then it is hazard-free. On the other hand, if it falls under Case 2 and satisfies the conditions of Theorem 1, static 1 hazards will be present. These hazards can always be eliminated in the following manner.

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Step I . Implement a P-net from f(l).

Step 2. Modify f(l) by adding redundant terms for each pair of adjacent '1's that are not covered by any other pass prime implicant.

Step 3. Find f, from f(1) and form its dual for f, .

Step 4 . Implement an N-net from f,.

The above design procedure guarantees that the N-net is open during all those transitions that are otherwise prone to static 1 hazards. A similar procedure can be adopted if the minimal transistor implementation falls under Case 3. 0

Corollary 4

A pseudo-nMOS gate designed from f(0) is free of any static 1 hazards. Similarly a pseudo-nMOS gate designed from f(1) is free of any static 0 hazards.

Proof

The proof of this corollary follows from the proof of Theorem 6.

Corollary 5 A pseudo-nMOS gate designed from f(0) is static hazard-free if f(0) has pass

implicants covering each pair of adjacent '0's. Similarly, a pseudo-nMOS gate designed from f(1) is static hazard-free if f(l) has pass implicants covering each pair of adjacent '1's.

Proof

The proof of this corollary follows from the proof of Corollary 3.

Static hazard-free designs for fully differential CVSL gates satisfy Theorem 6 and Corollary 3. In using them, the P-net may be replaced by N,, the N-net by No and duality by complementation. The following theorem gives a minimal transistor implementation of a CVSL gate that is static hazard-free.

Theorem 7 A CVSL realization using a BTS pass function is static hazard-free.

Proof Let there be an ordered path X:Xz . . . X t from Vs to f ' and another X:Xz . . .

(Xt)' from V, t o t This corresponds to the pass implicant X:X: . . . Xi+_ ,(X:). Two cases exist:

(a ) the pass variable switches, and

(b) any one of the control variables switches.

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In case (a), if the pass variable X: switches between two adjacent input states, this complements the output and hence there are no static hazards.

In case (b), consider that the switching variable between two adjacent input states is any one of the control variables Xf where j = 1 to i - 1 and j # i.

Assume that there is a closed path from V, to f '(0, viz. X:X: . . . Xj* . . . X:- ,X t for a certain input condition. For a static hazard to occur when X; switches, there must be a momentary closed path to f( f') through X:X: . . . (Xf)' . . . Xi*_ ,X:.

However, for the output to remain constant at either l(0) for both input states, the ordered paths X:X: ... Xj* ... XE,X: and X:X: ... (Xf)' ... Xt-,X: must both be connected to either f ' ( f ) . This is a contradiction; hence the proof. 0

Corollary 6 Optimal CVSL realization using a modified BTS pass function is static hazard-

free.

Proof

The proof of this corollary follows from the proof of Theorem 7.

4.2 Dynamic hazard elimination

Section 3.2 gives the conditions to be satisfied for a dynamic hazard to occur in CMOS networks. One of the necessary conditions in all the three types of CMOS networks (CMOS complementary logic, pseudo-nMOS, and CVSL) is that there must be unstable P sets and S sets in the switching function. This condition is exploited in designing hazard-free networks here.

In the static hazard-free designs given earlier, it can be seen that either unstable 1 sets or unstable 0 sets will be absent in the function. Thus a static hazard-free design automatically also qualifies for a dynamic hazard-free design; hence the following theorem.

Theorem 8 A CMOS gate network design eliminating static hazards is also free of dynamic

hazards.

Proof

A static hazard-free design for a CMOS gate can be obtained from f(l),f(O), or both f(1) and f(0). If the design uses f(l), then it guarantees the absence of unstable 1 sets. Similarly if the design uses f(0) alone, then there will be no unstable 0 sets. Since both the above designs contain no unstable 1 sets and unstable 0 sets simultaneously, this guarantees the absence of dynamic hazards. In the third case when the CMOS network is designed using both f(1) and f(O), the N-net and the P-net are non-duals in CMOS complementary gates, and N o and N, are non-complementary networks in fully differential CVSL (this case does not occur in pseudo-nMOS). Thus the necessary condition for the presence of dynamic hazards is not met; hence the theorem.

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5. Simulation In this paper, HPSPICE is used to analyse the transient behaviour of CMOS

gate networks under various device parameter values, especially in terms of MOS transistor sizes and their delay characteristics.

SPICE simulation was performed on all the three types of CMOS gates for the presence of both static and dynamic hazards. In CMOS complementary gates and pseudo-nMOS gates, both static and dynamic hazards were very prominent under certain conditions. The CMOS complementary gate shown in Fig. 5 was simulated for static 0 hazards. This gate implements the switching function f = AB + A'C. The function J, obtained from f(0) is given by J, = A'C' + AB'. The implementation uses J, for an N-net and its dual for a P-net. The simulation results in Fig. 7 shows a 3.78 V transient pulse for a step input of 5 V.

The above switching function f = AB + A'C when implemented as a CMOS complementary gate from f(1) for a P-net and its dual for an N-net is shown in Fig. 6. The simulation results in Fig. 8 show a transient pulse of 4.2V for a step input of 5 V.

Figure 5. CMOS complementary gate used for static 0 hazard simulation.

Figure 6. CMOS complementary gate used for static 1 hazard simulation

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Figure 7. Static 0 hazards in CMOS complementary gate

A pseudo-nMOS gate implementation for the function f = AB + A'C implemented with f, from f(0) on SPICE simulation gave a static 0 hazard. This hazard shows a transient pulse of 2.45V during the transition 100 to 000. The simulation set-up used a weak PMOS pull-up transistor to produce a good 0 output. The simulation results are given in Fig. 9.

SPICE simulation for static 1 hazards was carried out on a different realization of the same function in pseudo-nMOS logic. The N-net function f, was derived as the dual of the function f, = A'B' + AC' which was derived from f(1). During the input transition from 01 1 to 11 1, simulation results show a very prominent transient pulse of height 4V. The simulation results are given in Fig. 10.

Figure 8. Static 1 hazards in CMOS complementary gate.

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Figure 9. Static 0 hazards in pseudo-nMOS gate.

The CVSL network implementation for the function f = AB + A'C with fN, derived from f ( I ) and fN, as the complement off.,, was then simulated for static 1 hazards. As can be seen from the simulation results, this shows only a very small transient pulse of amplitude 0.05V. To a good approximation, this circuit can be treated as hazard-free. This may be justified because of the slow switching of this network. Under worst-case conditions, it may probably exhibit a more prominent transient pulse. The simulation results are given in Fig. 11.

The above function when implemented with f,, from f(0) and its complement for fN, was then simulated for static 0 hazards. As in the previous case, the simulation

Figure 10. Static 1 hazards in pseudo-nMOS gate.

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Figure 11. Static 1 hazards in CVSL gate.

results show only a very small transient pulse of height 0.34V during switching. These results are given in Fig. 12.

From the above simulation results it can be concluded that CVSL networks are less prone to static hazards compared to other types of CMOS realizations. Next, simulation was carried out to check the presence of dynamic hazards.

A CMOS complementary gate implementation of the function f = AC + A'BC' is shown in Fig. 13. From the network, f, = (A'B' + C)(A1 + C') + AC'. The P-net is implemented as the dual of the N-net. It is seen that this network indicates a potential dynamic hazard for the transition 110 + 111. The simulation results show a

Figure 12. Static 0 hazards in CVSL gate.

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v** -L Figure 13. CMOS complementary gate used for dynamic hazard simulation.

I 0 0 z z : . . . . . . . . . . . . . . . . . 0 0 8 8 4 . 2

TIME (nsecs) 0 N

I

Figure 14. Dynamic hazards in a CMOS complementary gate

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Nazards in CMOS circuits

. . . . TIME

Figure 15. Dynamic hazards in a pseudo-nMOS gate.

transient signal variation switching between 3.92 V and 0.83 V, indicating a prominent dynamic hazard. The simulation results are given in Fig. 14.

A pseudo-nMOS gate implementation of the function f = AC + A'BC' was done with f, = (A'B' + C)(A1 + C') + AC'. The simulation results in Fig. 15 show a tran-

-0 1 = 0 + Y b ' 0 0 1

ss, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . + s d :

5 I + . +

O O 1 0

+ f +

' 9 : + * . . +

0 . * + * * + + . +.. O l * X * . . . . . , . . * + + + . + * . . . . . . . . . . . . . . . . . . . . . . . . . . * 0 l

0 0 1 D 0

B 8 : 0 0 0 0 1 .................................................... . . 0 7 4 . 0 15

T I B E lnrccr)

Figure 16. Dynamic hazards in a CVSL gate.

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990 Hazards in CMOS circuits

sient signal switching between 3.4V and 0.64V during the input transition 110 to 11 1.

In a similar manner, a CVSL network was simulated for dynamic hazards. Here also the same function f = AC + A'BC' was used for implementation. In this case fNo was derived from f(0) and f,, was taken as%. The two functions fNo and fN, are given by fNo = (A'B' + C)(A1 + C') + AC' and fN, = ( (A + B)C' + AC)(A' + C). The simulation results in Fig. 16 show no appreciable transient signal variations.

6. Conclusions Different realizations of CMOS complex gates suitable for VLSI implementation

are analysed for static and dynamic hazards in this paper. The three different realizations studied in this paper are CMOS complementary gates, pseudo-nMOS gates, and CVSL gates. A few design techniques are presented for the design of these different types of C M O S gates based on pass logic principles.

A number of theorems are given to check for any potential hazards, both static and dynamic, in all the three types of CMOS networks. In this way, existing designs can be verified for possible hazards. From a detailed analysis of these circuits it is found that static and dynamic hazards are very prominent in both CMOS complementary gates and pseudo-nMOS gates. These hazards depend heavily on the device sizes as well as the device delays in these networks. CVSL gates are found to be less prone to these hazards. This may be because of the slow switching of these gates compared to other types of CMOS networks. Both theoretical studies and SPICE simulation results indicate this.

The last part of this paper is devoted to the design of hazard-free CMOS circuits. In this connection, it is seen that some of the methods developed for earlier gate networks produce conflicts when applied t o CMOS circuits. During a conflict, the output will be pulled to both V,, and Vss simultaneously. Hence modified design techniques are presented to eliminate these hazards. I t is also seen that, for both CMOS complementary gates and pseudo-nMOS gates minimal transistor designs may not always be hazard-free. O n the other hand minimal transistor designs for CVSL gates are always found t o be hazard-free.

REFERENCES FEIZI, A., and RADHAKRISHNAN, D., 1985, Multiple output pass networks: design and testing.

Proceedings of the I.E.E.E. International Tes t Conference, 907-91 1 . KLIR, G. J., 1972, Introduction t o the Methodology o j Switching Circuits (New York: Van

Nostrand). KOHAVI, Z., 1978, Switching and Finite Automata Theory (New York: McGraw-Hill). KRAMBECK, R. H., LEE, C. M., and LAW, H. S., 1982, High-speed compact circuits with

CMOS. I.E.E.E. Journal ofsolid-State Circuits, 17,614-619. MCCL~SKEY, E. J., 1965, Introduction l o the Theory of Switching Circuits (New York:

McGraw-Hill). PETERSON, G. E., and MAKI, G. K., 1984, Binary tree structured logic circuits: design and fault

detection. Proceedings of the International Conference on Computer Design, 671-676. RAIJHAKRISHNAN, D., WHITAKER, S. R., and MAKI, G. K., 1985, Formal design procedures for

pass transistor switching circuits. I.E.E.E. Journal of Solid-state Circuits, 20, 531-536. SASI, S., 1988, Hazard free design of CMOS circuits. MS. thesis, University of Idaho,

Moscow, Idaho. WESTE, N., and ESHRAGHIAN, K., 1985, Principles of C M O S VLSI Design (Menlo Park, Cali-

fornia: Addison-Wesley).

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hazards in cmos circuits

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