ieee journal of solid-state circuits, vol. 40, …...ac coupling solves the kgd problem [12],...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 4, APRIL 2005 829

Analysis and Design of Inductive Coupling andTransceiver Circuit for Inductive Inter-Chip

Wireless SuperconnectNoriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Fellow, IEEE, and Tadahiro Kuroda, Senior Member, IEEE

Abstract—A wireless bus for stacked chips was developed byutilizing inductive coupling among them. This paper discussesinductor layout optimization and transceiver circuit design. Theinductive coupling is analyzed by a simple equivalent circuit model,parameters of which are extracted by a magnetic field model basedon the Biot–Savart law. Given communication distance, transmitpower, data rate, and SNR budget, inductor layout size is mini-mized. Two receiver circuits, signal sensitive and yet noise immune,are designed for inductive nonreturn-to-zero (NRZ) signalingwhere no signal is transmitted when data remains the same. A testchip was fabricated in 0.35- m CMOS technology. Accuracy of themodels is verified. Bit-error rate is investigated for various inductorlayouts and communication distance. The maximum data rate is1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitterand 2.6 mW in the receiver at 3.3 V. If chip thickness is reducedto 30 m in 90-nm device generation, power dissipation will be1 mW/channel or bandwidth will be 1 Tb s mm2.

Index Terms—High bandwidth, inductor, low power, SiP, wire-less bus.

I. INTRODUCTION

MULTIFUNCTION and high-performance LSI systemsare in increasingly strong demand in recent years. Typ-

ical applications are an application processor for three-dimen-sional (3-D) video games, an imaging processor for high-enddigital cameras, a graphics card for personal computers, and soon. The important key to improve the performance of these LSIsystems is high-bandwidth communication between functions,such as CPU and memory. Conventional system-on-a-board(SoB) implementation with a high-speed serial link techniques[1], [2] has difficulty to develop high-bandwidth interface dueto its long inter-chip distance, which degrades data rate andchannel density, or it requires higher power dissipation andarea for circuits. On-chip network [3], [4] in system-on-a-chip(SoC) technology is one of the solutions to meet the demand.However, cost increase due to the complex embedded processis the problem of SoC. System in a package (SiP) can solvethe problem and 3-D stacking structure reduces chip distancesubstantially ( 100 m), providing motivation to develop alow-cost low-power high-bandwidth interface. From this pointof view, several interface technologies are reported [5]–[11].

Manuscript received August 30, 2004; revised January 24, 2005.N. Miura, D. Mizoguchi, and T. Kuroda are with the Department of Elec-

tronics and Electrical Engineering, Keio University, Yokohama 223-8522,Japan.

T. Sakurai is with the Center for Collaborative Research, University of Tokyo,Tokyo 153-8505, Japan.

Digital Object Identifier 10.1109/JSSC.2005.845560

In wired mechanical approaches, through-silicon via [5] ormicro bump [6] technologies, issues are cost increase causedby additions in process complexity and yield degradation dueto difficulty in screening a known good die (KGD). On theother hand, wireless approaches, wireless superconnect (WSC)by capacitive coupling (WSC-C) [8], [9] or inductive coupling(WSC-IIS) [10], [11] have many advantages over wired interms of power, speed, and cost. The interface, a metal plate forcapacitive coupling or a metal inductor for inductive coupling,can be implemented in a standard CMOS process without anadditional mechanical process which allows significant costreduction of fabrication and high-density channel arrangementby exploiting the process scaling. In addition, the noncontactinterface removes a highly capacitive electrostatic discharge(ESD) protection device to reduce power, delay, and area. Theabsence of ESD protection and a high-pass filtering property ofac coupling solves the KGD problem [12], enabling test at thehigh operating frequency before assembly.

However, capacitive coupling has a limitation. Since it is avoltage-driven scheme, it cannot provide large transmit powerenough to communicate over long distance at low supply volt-ages in scaled devices. As a result, the capacitive coupled in-terface can be employed only in a case where two chips arestacked face-to-face in distance shorter than several microns.It cannot be used when a lower chip is mounted face down inan area bump package. Additionally, in an application wherean upper chip has imaging sensors, the chip has to be stackedface-up, which also limits employing capacitive coupling. Toovercome this limitation, WSC-IIS [10], [11] is developed forlonger inter-chip communication. Fig. 1 illustrates the scheme.Chips are stacked face-up and inductively coupled by metal in-ductors to form a multidrop bus. Since power, ground, and clockcan be provided by bonding wires in a face-up stacked structure,no complex mechanical process (through-silicon via or microbump) is required, while it is required in a face-to-face struc-ture. A transmitter and a receiver each have an inductor andthe transmitter inductor is allocated in the receiver inductor forhigh layout density. Fig. 2 shows the metal inductor layout thatreduces parasitic capacitance between metal layers [13]. Sinceinductive coupling is a current-driven scheme, transmit powercan be increased for longer distance communication even at lowsupply voltages in scaled devices. In addition, transmission gaincan be increased by increasing number of turns of the inductorsby exploiting an increasing a level of the metal layers. Data rateof 1.2 Gb/s/pin in 300 m distance is reported in [10]. Powerdissipation is 43 mW in a transmitter and 2.5 mW in a receiver.

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830 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 4, APRIL 2005

Fig. 1. Wireless superconnect (WSC) with inductive inter-chip signaling (IIS).

Fig. 2. Metal inductor layout.

An ideal scaling scenario may be found if a chip thickness isscaled down. It is reported in [14] that substrate thickness is re-duced 1.7 m without affecting transistor characteristics.

Given communication distance, transmit power, data rate, andsignal-to-noise ratio (SNR) budget, the metal inductor should beminimized for area reduction by optimizing layout parameters(diameter , width , space , and number of turns ). Smallerinductor layout yields higher bandwidth when the inductors areplaced in an array. However, there is no theory for design op-timization, since both electrical circuit and magnetic field areinvolved in designing the inductive coupling.

In this paper, simple and yet accurate models for circuit andmagnetic field design are discussed to derive a theory for opti-mizing inductor layout. Transceiver circuit design for the induc-tive nonreturn-to-zero (NRZ) signaling is described. The anal-ysis and the design is verified and evaluated by measuring a testchip that was fabricated in 0.35- m CMOS technology.

The rest of this paper is organized as follows. In Section II,the inductive NRZ signaling will be proposed. Section III willdiscuss an analysis of inductive coupling with an equivalentcircuit and a magnetic field model, and these models will beverified. Section IV describes transceiver circuit design for theNRZ signaling. In Section V, the design and the analysis in-cluding the transceiver circuit are verified and evaluated by themeasurement of inter-chip communications. The performancesummary and scaling scenario of the proposed interface will be

Fig. 3. Inductive nonreturn-to-zero (NRZ) signaling.

presented in Section VI. Finally, conclusions will be presentedin Section VII.

II. INDUCTIVE NRZ SIGNALING

In a general wireless data communication, a carrier modu-lation technique is often utilized to improve SNR while it re-quires sophisticated RF/analog circuits (mixer, frequency syn-thesizer, passive filter, etc.) which increase power dissipationand area. On the other hand, since a transceiver of WSC-IIScommunicates in close proximity, much higher SNR can be ob-tained without the carrier modulation. Therefore, we can utilizea kind of pulse modulation which eliminates circuit complexitysignificantly. Fig. 3 illustrates our proposed inductive NRZ sig-naling. A transmitter converts transition of baseband binary dataTxdata to a bipolar pulse current . A receiver senses the po-larity of through inductive coupling with a sampling clockRxclk and recovers baseband data Rxdata.

In the inductive NRZ signaling, a received signal is notgenerated when Txdata is held. To prevent metastable state,the sensitivity of the receiver should be set within an appro-priate range so that it can detect signal in when Txdata tran-sits, while it can ignore noise in when Txdata remains thesame. Two receiver circuits are proposed to solve this problemin Section IV.

III. ANALYSIS OF INDUCTIVE COUPLING

A. Equivalent Circuit

Fig. 4(a) depicts a proposed equivalent circuit of the induc-tive coupling. Since the receiver is designed to have high inputimpedance for received-voltage sensing, current through a re-ceiver inductor is small enough to ignore self-induced voltageat the receiver inductor and induced voltage feedback to a trans-mitter from a receiver inductor. In addition, a coupling capac-itor generated between inductors can be abbreviated because oflong communication distance. From Fig. 4(a), transfer functionis given by

(1)

MIURA et al.: INDUCTIVE COUPLING AND TRANSCEIVER CIRCUIT FOR INDUCTIVE INTER-CHIP WIRELESS SUPERCONNECT 831

Fig. 4. Electrical model of inductive coupling: (a) equivalent circuit;(b) frequency characteristics (L = L = 5 nH, C = 500 fF, C = 50 fF,R = R = 100 , k = 0:2, R = 50 ).

Its frequency characteristic is depicted in Fig. 4(b). Thetransmitter inductor is modeled as a parallel resonator whoseself-resonant frequency is given by , andby including transmitter’s output impedance, it behaves asa second-order low-pass filter. The inductive coupling func-tions as a differential operator, or a high-pass filter, whosegain is determined by . The receiver inductor ischaracterized as a low-pass filter whose cut-off frequency isdetermined by . In total, the inductive couplingbehaves as a bandpass filter. Power/ground noise may be effec-tively cut off due to the filter characteristics.

In inductive NRZ signaling, the input signal to the inductivecoupling is approximated by Gaussian pulse which is givenby

(2)

where is peak voltage, is time offset, and is pulse widthdetermined by data rate. Then, the frequency spectrum ofis given by

(3)

Essentially, differential operation of inductive coupling is in-evitable, therefore, becomes the actual frequencyspectrum to be analyzed. Fig. 5 describes the frequency spec-trum of . The peak frequency (fundamental) isgiven by . Bandwidth of at least is required to dampthe received signal and diminish inter-symbol interference (ISI).Fig. 6 shows that gain of the inductive coupling in high-fre-quency decreases as increases. Therefore, a metal inductorshould not be shared by the transmitter and the receiver, sincethe transmitter exhibits large output capacitance for small .Otherwise, fundamental as well as harmonics are attenuated andISI is increased as shown in Fig. 6.

B. Magnetic Field Modeling

In order to extract the electrical parameters in (1), a theoret-ical model for analyzing magnetic field is developed, namely thecurrent density fiber model. As depicted in Fig. 7, magnetic fluxdensity is calculated by integrating contributions from all the

Fig. 5. Characteristics of signals in inductive NRZ signaling in (a) timedomain and (b) frequency domain.

Fig. 6. Received voltage when metal inductor is (a) shared and (b) not shared.

current density fibers that are calculated by the Biot–Savart law.Self-inductances , , and mutual inductance are calcu-lated by integrating penetrating though each inductor, and acoupling coefficient is given by . Since mag-netic flux density generated by a square inductor is given by asuperposition of magnetic flux density generated by four metallines, , can be easily obtained by calculation of only onemetal line. In addition, when metal inductors are aligned con-centrically, can be also obtained by the same calculation be-cause of the symmetry. This model is available to calculatewhen inductors are not aligned concentrically, which is equiv-alent to analyzing crosstalk between channels and it is demon-strated and evaluated by measurements in [15].

C. Experimental Result

Accuracy of the models is examined by measuring metal in-ductors by the second and third metal layers and inductive cou-pling between the first and third metal layer in a test chip. Table Isummarizes measured and calculated self-inductance of two-layer on-chip metal inductors. Calculation based on the currentdensity fiber model has good agreement with the measurementsince the error between them is about 5% in several inductor


Fig. 7. Current density fiber model for magnetic field modeling.

TABLE IMEASURED AND CALCULATED SELF-INDUCTANCE OF METAL INDUCTORS

Fig. 8. Measured and calculated S21 parameter of inductive coupling.

layout parameters. The parameter of on-chip inductive cou-pling has been measured by a network analyzer and calculatedby the proposed equivalent circuit model in Fig. 4(a) with re-placing the current-controlled voltage source to a receiver in-ductance for 50- -terminated measurement. Fig. 8 showsthe results where good agreement between measurement andcalculation are also found.

D. Optimization of Inductor Layout

Relations between electrical parameters ( , , , ) andlayout parameters ( , , ) are approximately given by

(4)

(5)

(6)

(7)

(8)

(9)

(10)

where is communication distance between a transmitter anda receiver. In a face-to-back stacked structure, is almost de-termined by chip thickness. Parameters for two-layer metal in-ductors in 0.35- m CMOS process are used; wire space

m, nH mm, pF mm ,, and output capacitance of transmitter fF.

is one of the layout parameters, but it should be the min-imum value available in a fabrication process to provide largeopening area of an inductor, because the opening area deter-mines a coupling coefficient between inductors, which affectsgain of inductive coupling much more than parasitic capaci-tance between metal lines. From (1), (4)–(10), received signalpower is calculated. Layout parameters for an optimized in-ductor are calculated and presented in Fig. 9 when is mini-mized under given conditions of communication distance, datarate of 1.25 Gb/s (pulse width ps), transmit power of40 mW ( ), and SNR budget of 20 dB. The noisepower assumed in this theory is thermal noise which is inte-grated and estimated as the same power of 20-mV-peak receivedsignal. Therefore, dB denotes that received signalhas 200-mV-peak voltage. The transfer function is maximizedwithin the operating frequency range ( GHz). Thetransmitter and receiver inductors can be placed inside concen-trically for high layout density. Because of the large output ca-pacitance of the transmitter, the transmitter inductor is designedto have smaller self-inductance and series resistance to increasebandwidth, and as a result, metal wires should be wide. There-fore, the transmitter inductor should be placed inside of the re-ceiver inductor concentrically. Otherwise, the opening area ofthe receiver inductor becomes small, which degrades couplingsignificantly.

As shown in Fig. 9, inductor layout will linearly scale downas chip thickness scales. Increasing metal layers of the metalinductor contributes to increasing the gain of inductive coupling,which enables reducing the transmit power or area.

IV. TRANSCEIVER CIRCUIT DESIGN

A. NRZ Signaling

Waveforms of transmitted current and received voltagein the inductive NRZ signaling are illustrated in Fig. 3. A

transmitter is a kind of pulse generator providing bipolar pulsecurrent based on transition of Txdata. A receiver samplesvoltage induced by through the inductive coupling andrecovers data Rxdata. However, since is not generated whenTxdata continues, the sensitivity of the receiver should be setwithin appropriate ranges so that it can detect signals in


Fig. 9. Optimal inductor layout parameters derived from theoretical models(� = 300 ps, R = 50 , SNR = 20 dB).

Fig. 10. Transmitter.

Fig. 11. Sensing-time control receiver.

when Txdata transits, while it can ignore noise in when Tx-data remains the same.

B. Transmitter

A proposed transmitter circuit is depicted in Fig. 10. A simpleH-bridge circuit with a delay buffer is utilized to provide bipolarpulse current . flows in the transmitter inductor at the tran-sition of Txdata for the period of delay time of a delay buffer.The delay buffer can be implemented with an odd-stage inverterchain. When the transceiver is not transmitting data, the loop ofthe transmitter inductor is opened by Tx/ . Otherwise, the in-duced current in the transmitter inductor counteracts the changeof magnetic field and reduces the received byin a stacked bus structure as shown in Fig. 1.

C. Receiver

A sense-amplifier flip-flop circuit, shown in Fig. 11, isadopted as a receiver to detect small induced voltages. isdesigned to have high resistance ( k ) for voltage sensing.Due to this high resistance, current flow in a receiver inductor

Fig. 12. Sensing-time (T ) control in (a) L = 0:4 �m, (b) L = 1:2 �m.

Fig. 13. Majority vote receiver.

becomes less than 1 mA so the receiver inductor does not affectcoupling in a stacked bus structure.

Two circuit techniques are proposed to solve the above-men-tioned problem of metastable state in the inductive NRZ sig-naling. One is a sensing-time-control receiver, shown in Fig. 11.Sensing time ( ) distinguishes between signal and noise.As shown in Fig. 12, the receiver operates erroneously with toolong when the same data continues, while with too short

, the signal may not be able to be received correctly. Timemargin in under process variations can be increased byenlarging channel length of the differential pair transistors, butat the cost of speed degradation. is controlled by a dutycontroller.

The other circuit is called a majority vote receiver, shownin Fig. 13. Two sense amplifiers are employed; one is likelyto output “high” and the other “low.” Rxdata is determined bymajority vote as shown in the table in Fig. 11. The offset isdesigned by employing different channel length to differentialpair transistors in the sense amplifiers. As shown in the SPICEsimulation in Fig. 14, noise margin of mV is secured with

m and 0.65 m for the differential pairs.The above-mentioned two receiver circuits with the trans-

mitter are simulated by using SPICE. Noise is modeled aswhite Gaussian noise and given by voltage sources connectedat receiver’s input resistance . The transceiver is simulatedwith transmitting and receiving pseudorandom binarysequence (PRBS) data. The shmoo plots in Fig. 15 are derived


Fig. 14. Asymmetric differential pair in majority vote receiver.

Fig. 15. Shmoo plots: (a) sensing-time-control receiver; (b) majority votereceiver.

by sweeping and the delay of receiver’s clock . Themajority vote receiver operates faster than the sensing-timecontrol receiver by 6% as shown in Fig. 15.

V. INTER-CHIP COMMUNICATIONS

The dependence of SNR on communication distance is cal-culated by the theoretical models and depicted in Fig. 16. Asthe diameter of the receiver inductor increases and the com-munication distance decreases, SNR is improved. When SNRis increased, the sense amplifier in the receiver recovers datafaster, so the PASS area in Fig. 15 is shifted below. As a re-sult, the timing margin ( margin) of the sensing-time-con-trol receiver at ps is increased up to 200 ps when

dB. By using Gaussian distribution of the clock anddata jitter in measurement system, the bit-error rate (BER) canbe calculated by the timing margin.

A test chip was fabricated in 0.35- m CMOS technology.Table II summarizes microphotographs of our implemented pro-totype transceivers with metal inductors. The layout parametersare the same as that utilized in the calculation in Fig. 16. Thetransmitter inductor has three turns and the receiver inductorswith 100, 200, and 300 m diameter have four, five, and sixturns, respectively. Fig. 17 shows a microphotograph of an ex-perimental setup for evaluating inter-chip communication. Wemeasured the test chip in a laboratory room without any specialthermal/air control and electromagnetic shielding. Chips weremounted face-up on each printed-circuit board. Clock, power,and some digital control signals were provided through bondingwires. Transmitting data was generated by an on-chip linear

Fig. 16. Calculated BER dependence on communication distance.

TABLE IITRANSCEIVERS WITH METAL INDUCTOR AND LAYOUT PARAMETERS

feedback shift register (LFSR). Clock timing and duty ratio werechanged by 70-ps steps by digital control. The upper board andthe lower board with the chip were placed face-to-face. Com-munication distance was changed by moving the upper chip upand down by a micromanipulator in a fine pitch ( m). Inthis experimental setup, the chips communicate in face-to-face,not face-to-back, mounting, described in Fig. 1. The effect ofthe silicon wafer in the propagation was not considered. How-ever, based on a simulation study by a 3-D electromagnetic fieldsolver reported in [10], the difference can be negligible becausethe permeability of materials used in CMOS process (Si, SiO )are the same as air. Reflection and absorption of the materialscan be ignored. In addition, the signal attenuation caused byeddy current in a substrate is around 5% in the simulation re-sults.

The measured maximum communication distance is shownin Fig. 18. The measured results have good agreement withthe calculated results in Fig. 16. A curve ofdenotes dB. Since the receiver’s sensitivity is setto ignore noise, the receiver cannot receive any data when thesignal level is attenuated to smaller than the noise level (

). As a result, no data transition is monitored in the receiveddata. By increasing SNR to 26 dB and the timing margin to200 ps, BER of less than is achieved when communi-cation distance is reduced to less than 60, 120, 150 m when

m, respectively. The maximum data rateis 1.25 Gb/s/ch. Power dissipation is 43 mW in the transmitter


Fig. 17. Microphotograph of experimental setup of inter-chip communications.

TABLE IIIPERFORMANCE SUMMARY AND COMPARISON

Fig. 18. Measured maximum communication distance.

and 2.6 mW in the receiver at 3.3 V. The power dissipation inthe transmitter is linearly decreased by decreasing the clock rateand the switching activity due to the NRZ signaling. Since thereceiver is sensitive to process variation, several chipsets havebeen tested. The effect of process variation cannot be found inthe measurement because the receiver is designed in a longerchannel length to overcome the variation.

VI. PERFORMANCE SUMMARY AND SCALING SCENARIO

Table III summarizes the performance of the proposedscheme and compares it with wired approaches developed in0.35- m CMOS [1], [2]. Data rate of 1.25 Gb/s with powerdissipation of 46 mW was achieved. The minimum area for theinterface is 0.025 mm at communication distance of 60 m.Compared to [1] and [2], the power dissipation is reduced by25% and the area is reduced by a factor of 5 and 32, respectively.

A scaling scenario of the proposed scheme can be derived byscaling the parameters used in the theoretical analysis. In 90-nmdevice generation, the number of metal layers is increased toseven, and supply voltages are scaled to 1 V. By utilizing a90-nm BSIM model in SPICE simulation, data rate and powerdissipation for inter-chip communications of three stacked chipswere calculated, and are summarized in Table IV. Scaling in chipthickness as well as device size is effective in decreasing powerdissipation and increasing bandwidth. When six metal layersare used for the metal inductor, the gain of inductive couplingcan be increased by three times and, due to the voltage scalingby a factor of 3.3, 10 power reduction is obtained in total.In addition, if chip thickness is reduced to 30 m further 4power reduction is obtained, as a result, power dissipation willbe reduced to 1.1 mW/channel or bandwidth will be increasedto 1 Tb s mm with power dissipation of 4.2 W by arranging200 transceivers in 1 mm .


TABLE IVSCALING SCENARIO

VII. CONCLUSION

Inductive coupling for inter-chip communications has beeninvestigated. Theoretical models for circuit design and magneticfield analysis were proposed, and their accuracy has been veri-fied by measurement. A theory to minimize inductor layout sizehas been derived. The loop of a transmitter inductor was openedin the receiving signal to keep the signal from being attenuatedby induced current in the transmitter inductor. Two receiver cir-cuits were investigated to distinguish between signal and noisein the inductive NRZ signaling. The analysis and design hasbeen verified and evaluated by measuring a test chip in 0.35- mCMOS. The maximum data rate was 1.25 Gb/s/channel. Powerdissipation was 43 mW in the transmitter and 2.6 mW in the re-ceiver at 3.3 V.

ACKNOWLEDGMENT

The VLSI chip in this study was fabricated in the chipfabrication program of the VLSI Design and Education Center(VDEC), University of Tokyo, with collaboration by RohmCorporation and Toppan Printing Corporation.

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Noriyuki Miura was born in Oita, Japan, on October29, 1980. He received the B.S. degree in electrical en-gineering in 2003 from Keio University, Yokohama,Japan, where he is currently working toward the M.S.degree.

Since 2002, he has been engaged in research ona 3-D-stacked inductive inter-chip wireless interfacefor System in a Package. In 2002, he was with theHitachi Central Research Laboratory studying CADtools for low-power VLSI circuits. He has made tech-nical presentations and published technical papers at

ISSCC, the Symposium on VLSI Circuits, CICC, and ASP-DAC.

Daisuke Mizoguchi was born in Oita, Japan, onSeptember 7, 1975. He received the B.E. and M.S.degrees in information science and electrical engi-neering from Kyushu University, Fukuoka, Japan,in 1998 and 2000. He is currently working towardthe Ph.D. degree in electrical engineering at KeioUniversity, Kanagawa, Japan.

In 2000, he joined A Priori Microsystems, Inc.,Kanagawa, Japan. He has been engaged in devel-opment and design of high-performance computerusing FPGA boards. In 2001, he joined Keio Uni-

versity, Yokohama, Japan. He has been engaged in research on the inductiveinter-chip communication scheme. Since 2003, he has been working ondeveloping 3-D-FFT logic for Car–Parrinello calculation.


Takayasu Sakurai (S’77–M’78–SM’01–F’03)received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan, in 1981.

In 1981, he joined Toshiba Corporation, wherehe designed CMOS DRAM, SRAM, RISC pro-cessors, DSPs, and SoC solutions. He has workedextensively on interconnect delay and capacitancemodeling known as the Sakurai model and alphapower-law MOS model. From 1988 to 1990, he wasa Visiting Researcher at the University of Californiaat Berkeley, where he conducted research in the field

of VLSI CAD. Since 1996, he has been a Professor at the University of Tokyo,working on low-power high-speed VLSI, memory design, interconnects, ubiq-uitous electronics, organic ICs, and large-area electronics. He has publishedmore than 350 technical publications including 70 invited papers and severalbooks and filed more than 100 patents.

Dr. Sakurai served as a conference chair for the Symposium on VLSI Circuitsand ICICDT, a TPC chair for A-SSCC, a vice chair for ASPDAC and a pro-gram committee member for ISSCC, CICC, DAC, ICCAD, FPGA Workshop,ISLPED, TAU, and other international conferences. He is a plenary speaker forthe 2003 ISSCC. He is an elected AdCom member for the IEEE Solid-State Cir-cuits Society and an IEEE Circuits and Systems Society Distinguished Lecturer.

Tadahiro Kuroda (M’88–SM’00) received thePh.D. degree in electrical engineering from theUniversity of Tokyo, Tokyo, Japan, in 1999.

In 1982, he joined Toshiba Corporation, where hedesigned CMOS gate arrays and standard cells. From1988 to 1990, he was a Visiting Scholar with the Uni-versity of California at Berkeley, conducting researchin the field of VLSI CAD. In 1990, he returned toToshiba, and was engaged in the research and devel-opment of BiCMOS ASICs, ECL gate arrays, high-speed CMOS LSIs for telecommunications, and low-

power CMOS LSIs for multimedia and mobile applications. In 2000, he movedto Keio University, Yokohama, Japan, where he has been a Professor since 2002.His research interests include low-power high-speed CMOS design for wirelessand wireline communications, human–computer interactions, and ubiquitouselectronics. He has published more than 180 technical publications including40 invited papers and 17 books or book chapters, and has filed more than 100patents.

Dr. Kuroda served as a technical program committee chair for the Sympo-sium on VLSI Circuits, a vice chair for ASP-DAC, held sub-committee chairsfor ICCAD, A-SSCC, and SSDM, and was a program committee member forthe Symposium on VLSI Circuits, CICC, DAC, ASP-DAC, ISLPED, SSDM,ISQED, and other international conferences. He is a member of the Institute ofElectronics, Information and Communication Engineers of Japan.

ieee journal of solid-state circuits, vol. 40, …...ac coupling solves the kgd problem [12],...

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