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TRANSCRIPT
3
INTRODUCTION
FEATURES
1. General1) Enhanced IDE interface.2) Internal 5.25 inch, halfheight CD-R/RW Drive.3) 2Mbytes buffer memory.4) Audio CD like tray loading of a disc without using a caddy.5) Power loading and power ejecting of a disc. The disc can also be ejected manually.6) Supports Power saving mode and Sleep mode.7) Vertical and Horizontal operation.8) SuperLink Function.
2. Supported disc formats1) Reads and writes data in each CD-ROM, CD-ROMXA, CD-I FMV, Video CD, and CD-EXTRA2) Reads data in Photo CD (Single and Multi session).3) Reads and writes standard CD-DA.4) Reads and writes CD-R discs conforming to “Orange Book Part 2”.5) Reads and writes CD-RW discs conforming to “Orange Book Parts 3”.
3. Supported write method1) Disc at once (DAO), Session at once (SAO), Track at once (TAO), Variable packet, Fixed packet, and
Multi-session.
4. Performance1) Random 100 ms average access time.2) CD-R Record speed : 8X, 12X, 16X, 22X~40X (PCAV), 48X CAV.3) CD-RW Record speed : 4X, 10X, 12X, 16X, X24(PCAV).4) CD-ROM : Max 7,200 KB/s(Max 48x) Sustained Transfer rate.5) Supports real time error correction and real time layered error correction at each speed.6) PIO Mode 4, Multi DMA Mode 2, UDMA Mode 2.7) Multimedia MPC-3 Spec compliant.8) Support CD-TEXT read/write.
5. Audio1) Output 16 bit digital data over ATA interface.2) 8 Times Digital Filter for CD Audio 3) Software Volume Control4) Equipped with audio line output and headphone jack for audio CD playback.5) Front panel Volume Control for Headphone Output.
This service manual provides a variety of serviceinformation.It contains the mechanical structure of the CD-R/RW Drive and the electronic circuits inschematic form. This CD-R/RW Drive wasmanufactured and assembled under our strictquality control standards and meets or exceedsindustry specifications and standards.This CD-R/RW drive is an internal drive unitdesigned for use with IBM PC, HP Vectra, or
compatible computer. It can write as much as 700Mbytes of digital data into CD-R/RW disc, and canread as much as 650 Mbytes of digital data storedin a CD-ROM, CD-R and CD-RW disc.This CD-R/RW Drive can easily meet theupcoming MPC level 3 specification, and itsEnhanced Intelligent Device Electronics (E-IDE)and ATAPI interface allows Plug and playintegration in the majority of today’s PCs withoutthe need of an additional interface card.
LOCATION OF CUSTOMER CONTROLS
6
1. Disc trayThis is the tray for the disc. Place the disc on theejected disc tray, then lightly push the tray (orpush the eject button) and the CD will be loaded.NOTE: Don’t pull out or push in the disc trayforcibly. This might cause damage to the loadingsection of the drive.
2. Stop/Eject buttonThis button is pressed to open the CD tray.This button works only when power is supplied tothe drive.If an Audio CD is playing, pressing this button willstop it, and pressing it again will open the tray.
3. Emergency Eject HoleInsert a paper clip here to eject the Disc traymanually or when there is no power.
4. Volume controlThis is used to adjust the output volume of theheadphone jack. It can’t be used to adjust theoutput volume for the audio output connectors onthe rear panel.NOTE : Turn the volume down before turning onthe power. Sudden loud noises can damage yourhearing.
5. Headphone jackThis jack is for connecting headphones or mini-speakers.
6. Drive activity indicator(Read/Write)Two colored LED is used to indicate the operationof CD-R/RW Drive.
Headphone Jack
VolumeControl
Drive Activity Indicator
Stop/Eject Button
Disc Tray
Emergency Eject Hole
Front Panel
7
1. Power ConnectorConnects to the power supply (5-and 12-V DC) ofthe host computer.NOTE : Be careful to connect with the properpolarity. Connecting the wrong way may damagethe system (and is not guaranteed). Usually thisconnector can only be attached one-way.
2. IDE Interface ConnectorConnect to the IDE (Integrated DeviceElectronics) Interface using a 40-pin flat IDEcable.NOTE : Do not connect or disconnect the cablewhen the power is on, as this could cause a shortcircuit and damage the system. Always turn thepower OFF when connecting or disconnecting thecable.
3. Jumper ConnectorThis jumper determines whether the drive isconfigured as a master or slave. Changing themaster-slave configuration takes effect afterpower-on reset.
4. Analog Audio Output ConnectorProvides output to a sound card (analog signal).Generally you need this to play a regular audioCD.
5. Digital Audio Output ConnectorProvides output to a sound card (digital signal).
DIGITAL
AUDIO
ANALOG
AUDIO
INTERFACE
POWER
D G
3940
1+5 GND +12
2
C S MS L AR G L
Digital Audio OutputConnector
Jumper Connector
Analog Audio Output Connector IDE Interface Connector
Power Connector
Rear Panel
TROUBLESHOOTING GUIDE
Power check (Malfunction of LED and Tray).
52
Check the connection of 5V, 12V.Check the Reset (Pin 170, 122 of
IC101, pin2 of IC401).Check the input of oscillation (pin
109 of IC401).
Check SCLK, SDATA, XLAT (pin 122, 123, 124 of IC401).
1. Connect only the power cable
BD7907FS6Ch Servo DRIVE
MT1516RF AmpWobbleALPC
General port useEEPROM access
MT1508
DSPDecoderEncoder
ATIP DemodulatorWrite Strategy
Write S/H SignalI / F
Micro Processor
33.8688MHz
IC 101
IC 501 IC 103
IC 401
IC 102
3.3 V
Reset
12V 5V
AT49F002N512KB
Flash ROM
IC 50241
109
44
2
54
31
3
32
10 19 20
31
32
30
44 51 IC 202
2 170 PRST‘ L ’
122/ HRST‘ H ’
74 75
MCLK
55‘ H ’
/XRST
SDRAM
123
124
122
63
62
65SCLK
SDATA
XLAT
CN 100
MT1518
AT49F040
53
Check the Reference voltage(+/- 10%).
Check VC (1.4V) of Drive IC (pin27 of IC501).
Check voltage of VREF(1.4V)(pin 53 of IC101, pin 27 of IC501).
Check voltage of 2VREF(2.8V)(pin 52 of IC101).
Check HAVC/PDVC(2.0V)(pin 34 of IC401, pin 13 of CN201).
Check FVREF/FPDVC (2.8V) (pin 52 of IC401, pin22 of CN201).
Check FPDO(2.8V)(pin 54, 65 of IC401).
BD7907FS6Ch Servo DRIVE
MT1516 RF Amp Wobble ALPC
General port use EEPROM access MT1518
DSPDecoderEncoder
ATIP DemodulatorWrite Strategy
Write S/H SignalI / F
Micro Processor
IC 101
IC 501
CN 201
2.5 V
NJM3414
IC 503
76
75
32
1
IC 506
3
VHAVC
2VREF522.8 V
V28
IC 401
76 VREF531.4 V
V14
27
2
1.4 VVC
OpticalPick-upKRS-340B
LDDrive
17 28 76 134 1803.3 V
34
13
74
52
22
2.0 V
2.8 V
HAVC
VFVREF
FVREF
FPDVC
19FPDO 54
65
FPDO
FPDOLP
PDVC
20
FPDVcc
5 V
2.8V
54
Check the initial operation(Power-on state)
• Check the operating signal of Sled(pin 28, 29 of IC501 : SLIN1, 2).
• Check the output signal of Sled(pin 34, 35, 36, 37 of IC501).
• Check /SLEDIN_SW. (pin 104 of IC401).
• Check the control signal of DriverIC(pin 22, 23 of IC501).
• Check the power of DRIVE ICand VC.
Check SCLK, SDATA, XLAT (pin 122, 123, 124 of IC401).
Sled move to inside.
Spindle motor rotate.
Laser On. Check the Laser.
• Check the Spindle signal(pin 24 of IC501 : SPIN).
• Check FG input(pin 20 of IC101).
• Check the Hall signal(pin 1, 2, 3, 4, 5, 6 of IC501).
Check the operation of FocusFocus up / Down.
Laser Off / Spindle Stop.
BD7907FS6Ch Servo
DRIVE
MT1518DSPI / F
Micro Processor
IC 101
IC 501
FMO
271.4 V
VC
2021FG FG
2524SPIN DMO
18
11
9
OpticalPick-upKRS-340B
STEP Motor
SpindleMotor
65
4
23
CTL2
22
CTL1
29SLIN2
28SLIN1
373635
3
21
U
V
W
HU+ , HU-
7HB
B+ A- A+
27
26
FMO2
MT1516ALPC
General port use
IC 401
102101
123
124
122
63
62
65SCLK
SDATA
XLA T
DR
V-M
UT
E2
DR
V-M
UT
E1
HV+ , HV-
HW+ , HW-
,
,
,
34
B-
104
(From pin 1 of CN402)
/SLEDIN_SW
2 times iteration
55
1. Waveform when Sled moves to inside
SLIN1/SLEDINSW
A+
2. Waveform of Spindle rotation
HU+HV+HW+
3. Waveform of Spindle Kick
SPINFGU
Zoom in wave
Zoom in wave
Zoom in wave
Zoom in wave
When the sled moves to the inner position,the sine wave(refer to Fig1) inputs toSLIN1/SLIN2 (the input pins of drive IC).When Pick-Up unit approached to innermostposition, the /SLEDINSW signal(CN402 pin 1)becomes 0 V.The output pins A+ ,A-, B+, B- of the drive IC isPWM waveform and drives the Stepping Motor.
The output signal of Hall(HU+, HU-, HV+, HV,HW+, HW-) comes from a Hall sensor of spindlemotor and they were inputted to pin 1, 2, 3, 4, 5, 6of drive IC(BD7907FS) via CN402. When spindlemotor rotate, HU+, HW+, HV+ signals aregenerated in a regular order with 1200 phase delayeach other.(Refer Fig 2)
If waveforms of HU+, HU-, HV+, HV-, HW+, HW-different from Fig 2, check the pin 7(HB signal) ofdrive IC. The HB signal must be about 5V.
Wave of U,V,W assigned to pin 9,11,18 of DriveIC is a PWM waveform and they drive Spindlemotor.When spindle motor rotate, U/W/V signals aregenerated in a regular order with 1200 phase delayeach other. (Refer Fig 3)
If waveforms different from Fig 3, check pin27(VC), pin 51(VCC), pin22(CTL1), pin23 (CTL2),R514, R512, R510, R511.
When spindle kick, refer to Fig 4.
Fig.1
Fig.2
Fig.3
Fig.4
56
Check Tray operation.
Check /EJECT KEY (pin 11 of IC101).
Check the output signal of tray(pin 49, 50 of IC501).
Check the LED.
Check operating signal of tray(pin 26 of IC501).
• Check the control singal of Drive IC(pin 22, 23 of IC501).
• Check the power of DRIVE IC andVC.
Check operating signal of LED (pin96, 98 of IC401).
Check SCLK, SDATA, XLAT (pin122, 123, 124 of IC401).
Check operation S/W of tray(/OPEN SW:pin 94 of IC401/LOAD SW : pin 95 of IC401).
M
Tray Motor
MT1516 RF Amp
General port use
IC 401
123
124
122SCLK
SDATA
XLA T
MT1508
DSPDecoderEncoder
I / F
Micro Processor
IC 101
SW103
DETECTOR-TRAY
63
62
65
FR
ON
T
BD7907FS6Ch Servo DRIVE
IC 501
22
101
DRV-MUTE2 DRV-MUTE1
CTL2CTL1
271.4 V
VC
2426LDIN
49
50
SW102
EJECT-SW
11
2
1
94
95
/OPEN_SW
/LOAD_SW
TRAY -
TRAY +
PWMOUT
/EJECT_KEY
LED102
LED101
96
98
Q802
Q801
LED1
LED2
23
102MT1518
57
Check identification of Drive.
Check the connection of ATAPIcable.
Check the communication betweenPC and MT1518 (IC101).
Check SDRAM. (IC102)
Check Flash ROM (IC103).
2. Connection of Power and ATAPI cable
MT1508
DSPDecoderEncoder
ATIP DemodulatorWrite Strategy
Write S/H SignalI / F
Micro Processor
HOST
8MBSDRAM
I/Fcable
Address
Data
IC 101IC 103
IC 102
AT49F002N512KB
Flash ROM
33.8688MHz
74 75
Address
Data
Pin no. Pin name Pin no. Pin name39 DASP GND 4037 CS1 CS3 3835 DA0 DA2 3633 DA1 PDIAG 3431 INTRQ IO16 3229 DMACK GND 3027 IORDY CSEL 2825 IOR GND 2623 IOW GND 2421 DMARQ GND 2219 GND KEY 2017 HD0 HD15 1815 HD1 HD14 1613 HD2 HD13 1411 HD3 HD12 129 HD4 HD11 107 HD5 HD10 85 HD6 HD9 63 HD7 HD8 41 /HRST GND 2
CN101(ATAPI)
SDRAM
MT1518AT49F040
58
Check the identification of CD-ROM Disc (insert Disc).
Check the operation of Focus.
Check the operation of Tracking.
Check the Jump action.
• Check the drive signal of FCS-/+(pin 1, 2 of CN201).
• Check drive input signal of Focus(pin 53 of IC501 : FCIN).
• Check the input signal of FE(pin 42 of IC101 : FEI).
• Check the input signal of SBAD(pin 38 of IC101).
• Check the input signal of CSI (pin41 of IC401).
• Check the input signal of RFZC (pin60 of IC101 : HRFZC).
• Check the drive signal of TRK+/-(pin 3, 4 of CN201).
• Check the signal of Tracking (pin 52 of IC501 : TKIN).
• Check the signal of SLED(pin 28, 29 of IC501 : SLIN1, 2).
• Check control signal of Drive IC(pin 22, 23 of IC501: CTL1,2).
• Check power and VC of DRIVE IC.
Check signal of A~H (pin 39, 38, 37,36, 30, 31, 32, 33 of IC401).
Check the input signal of TE(pin 40 of IC101 : TEI).
In case of Focus Up/Down
MT1516 RF Amp
General port use
IC 401
123
124
122SCLK
SDATA
XLA T
MT1518
DSPDecoderEncoder
I / FMicro Processor
IC 101
63
62
65
BD7907FS6Ch Servo
DRIVE
IC 501
DRV-MUTE2
DRV-MUTE1CTL2
CTL1
271.4 V
VC
45TEO
40
43CSI
41
49SBAD
38
NJM3404
7
IC 505
1
52
53
6
2
23
22
OpticalPick-upKRS-340B
45 46
1 2
47 48
3 4
FC
S-
FC
S+
TR
K+
TR
K-
22
23
101
102
FCIN
TKIN
FOO
TRO
FOSO
TRSO
A ~ D
E ~ H
CN 201
TEI
CSI
SBAD
42FEO
42 FEI
FMO
29SLIN2
28SLIN1
27
26
FMO2
126RFZC
60 HRFZC
59
4. Operation of Focus Up/Down
FESBADFCS+
5. Waveform of Track Following
6. Waveform of Track Jump
TE
EQRF
CE
SLIN1
7. Waveform of Spindle Servo On
SPIN
FG
U
Zoom in wave
Focus Search Focus Servo On
Zoom in wave
Zoom in wave
Waveform of Focus Search refer to Fig 5.In Focus Search, FE signal and SBAD signal areused to Focus Servo On.Therefore, in case of Focusing Fail, check the FEsignal and SBAD signal.
Waveform of Track Following(Sequential Read)refer to Fig 6.By Sled Servo, SLIN1, SLIN2 (pin 28, 29 of DriveIC) drive the Sled Motor(Stepping Motor) forlocating the lens on the center axis of Pick-up.
Waveform of Track Jump refer to Fig 7.Center level of TE,CE is 1.4V.SLIN1, SLIN2 signal (pin 28, 29 of Drive IC)assume the form of Pulse. And they drive the SledMotor(Stepping Motor).RFZC(RF Ripple Zero Cross) signal is Pulse formand it lags behind TE signal 900.
To maintain constant rpm(CAV) or l inearvelocity(CLV), the drives control spindle motor.The Fig 8 shows the waveforms when spindleservo is on.
TERFZC
CESLIN1
Fig.5
Fig.6
Fig.7
Fig.8
60
Check RF and Spindle(Insert CD-ROM Disc).
Check the identification of CD-R Disc(Insert Blank CD-R).
Check the identification of CD-RWDisc (Insert Blank CD-R).
Check EQRF input signal(pin 45 of IC101)
Check the signal of A~H (pin 39, 38,37, 36, 30, 31, 32, 33, of IC401)
Check the operation signal of Spindle(pin 24 of IC501).
Check SCLK, SDATA, XLAT (pin 122, 123, 124 of IC401).
Check FG input(pin 20 of IC101).
Check the input signal of ATFG(pin 69 of IC101).
• Check the control signal of Drive IC(pin 22, 23, of IC501).
• Check power/VC of DRIVE IC.
BD7907FS6Ch Servo
DRIVE
MT1518
DSPDecoderEncoder
I / F
ATIP Demodulator
Micro Processor
IC 101
IC 501
271.4 V
VC
2021FG FG
2524SPIN DMO18
11
9
OpticalPick-upKRS-340B
STEP Motor
SpindleMotor
65
4
23
CTL2
22
CTL1
3
21
U
V
W
HU+ , HU-
7HB
MT1516RF AmpWobble
General port use
IC 401
102101
123
124
122
63
62
65SCLK
SDATA
XLA T
HV+ , HV-
HW+ , HW-
,
,
,
A ~ D
E ~ H
DRV-MUTE2 DRV-MUTE1
116 69ATFG
21EQRF
45
61
Check point of Writing
Check the compatibility betweenDrive and Tool.
Check Disc state (Fingerprint,Scratch, Dust...).
Check whether or not additionalwriting is allowed.
(Given in the Disc Info of writing tool)
Check whether or not Disc iswriteable (CD-R/CD-RW).
MT1516
ALPC
EEPROM access
MT1508
DecoderEncoder
Micro Processor
IC 101
110 EEP-CS IC 401
107 EEP-SDATA
123
124
122
63
62
65SCLK
SDATA
XLA T
108 EEP-CLK
AT93C862KB
EEPROM
IC 2031
4DO
CS
3DI
2SLK
(ALPC initial value before ‘Laser Power Setting’)
MT1518
Check Laser 1(Check EEPROM)
Activate ‘Addition Func.’ window inTest Tool(GGOOM6).
Execute ‘S/N’ (Identify SerialNumber).
Execute ‘ALPC Parameters’(Identify ALPC Parameters).
Check the communication lineof EEPROM.
Execute ‘C. Laser Powersetting’ in Test Tool(GGOOM6).
Check whether or not ‘ALPCParameters is initial value.
NG
NG
OK
62
Check Laser 2 (No disc).
Execute ‘E.ALPC Test for AS’ inTest Tool (GGOOM6) (select‘VRDC Loop’, and ‘Trigger’).
E
E
Check Read Laser
Initial value of FPDO : 2.8V +/- 10%.
OFF LEVEL.
VRDC LEVEL FPD.
Execute ‘D. Laser Inspection’ inTest Tool (GGOOM6).
Check the input of ENBL(pin 33 of CN201 : ‘H’).
Check the input of VRDC(pin 25 of CN201 : 0.4~0.8V).
Check the input of FPDO (pin 54,65 of IC401 : FPDO~0.1V).
• Check the input of RLDON(pin 128 of IC401 : ‘H’).
• Check SCLK, SDATA, XLAT(pin 122, 123, 124 of IC401).
Check Reference voltage.
NG
F
NG
G
VWDC1 LEVEL FPD.
VWDC2 FPD.
MT1516
ALPC
MT1518
DecoderEncoder
Write StrategyWrite S/H Signal
Micro Processor
IC 101CN 201
5 ENBL
IC 401
OpticalPick-upKRS-340B
LDDrive
33
0.4~0.8V
19FPDO 54
65
FPDO
FPDOLP
ENBL
FPDO-0.1V
123
124
122
63
62
65SCLK
SDATA
XLAT6325 VRDCOVRDC
128 57RLDON
H
H
63
Execute ‘E.ALPC Test for AS’ inTest Tool(GGOOM6) (Select
‘CD-R Rec Mode’, and ‘Trigger’)
FInspection of CD-R Recording Laser
Execute ‘E. ALPC Test for AS’ inTest Tool (GGOOM6) (Select
‘CD-RW Rec Mode’, and‘Trigger’)
GInspection of CD-RW writing Laser
Chect input of ENBL(pin 33 of CN201 : ‘H’).
• Check input of VWDC1(pin 26 of CN201 : 0.4~1.0V).
• Check input of VWDC2 (pin 27 of CN201 : 0.1~0.5V).
• Check input of WLDON(pin 27 of IC401 : ‘H‘)
• Check SCLK, SDATA, XLAT(pin 122, 123, 124 of IC401)
MT1516
ALPC
MT1518
DecoderEncoder
Write Strategy Write S/H Signal
Micro Processor
IC 101
CN 201
5 ENBL IC 401OpticalPick-upKRS-340B
LDDrive
33
1330
0.4~1.0V
WXRWXR
19FPDO 54
65
FPDO
FPDOLP
ENBL
123
124
122
63
62
65SCLK
SDATA
XLAT
6226 VWDC1OVWDC1
6127 VWDC2OVWDC20.1~0.5V
1531 ODONODON
127 58WLDON
WXR
ODON
FPDO
CD-R Recording Pulse
CD-RW Recording PulseWXR
ODON
FPDO
H
H
• Check input of WXR(pin 30 of CN201 : Pulse)
• Check input of ODON(pin 31 of CN201 : Pulse)
Check input of FPDO(pin 54, 65 of IC401 : Pulse).
Initial value of FPDO :2.8V/-10%)
64
Check Audio signal(Insert Audio Disc).
Identify playback of Audio Disc(Play Mode).
Check Output signal of AUIO L/R(pin 51, 54 of CN100).
Check Output signal of AUDIOL/R (pin 165, 167 of IC101).
Check Output signal of /AUD-MUTE (pin 103 of IC401).
Check SCLK, SDATA, XLAT (pin 122, 123, 124 of IC401).
Check Output signal of AUDIOL/R (pin 1, 7 of IC801).
Check Input signal of AUDIO L/R(pin 3, 5 of IC801).
Check Input signal of /AUD-MUTE (pin 3 of IC801).
Output of Headphone
MT1516 RF Amp
General port use
MT1508DSP
DecoderEncoder
I / FMicro Processor
IC 101
BH3544F
AUDIO AMP
IC 801 103
IC 401
LO165
RO167
AUDIO Line Out
51 54
CN 100
JK101
H-JACK
SB
3
5
3
AudioMute
Circuit
1
7
123
124
122
63
62
65SCLK
SDATA
XLAT
L-CH R-CH
ROUT
LOUT
ROUT
LOUT
/AUD-MUTE
ROUT
LOUT
MUTE
FRONT
MT1518
65
A. Start1. Install GCE-8481B -> PC Power ON -> Execute Windows.2. Execute GGOOM6.exe on Windows (GGOOM6.exe & GGOOM6.cfg should be on the same Directory).3. If you use GCE-8481B, “GGOOM6(Ver x.xx)” will be displayed on the Window Frame.4. Select I/F Setup on the menu bar.5. Select ATAPI I/F and then Click OK.6. Select Target Select on the menu bar.7. Select Number of Host(#0 or #1) appropriately, then “GCE-8481B” displays on Target Device. 8. Select “GCE-8481B” on Target Device, and then Click OK.
B. Check ALPC Parameters1. Select VIEW on the menu bar. 2. Click Addition Func. on VIEW window -> New frame will be displayed.3. Click ALPC Para tab.
[ALPC Parameters]1) CD-R READ Reference DAC : 60 ~1852) CD-RW READ Reference DAC : 60 ~1853) VWDC1 : 200 ~ 2964) VWDC1 Offset : 30 ~ 175 5) VWDC2 : 499 ~7876) VWDC2 Offset : -55 ~ 75
4. Close Calibration window.
• How to use Test Tool (GGOOM6)
[I/F Setup Menu] [Target Select window]
[ALPC Parameters Menu][Additional Function Menu]
C. Laser Power Setup (VWDC / VWDC 1, 2 re-setup)1. Remove disc on the tray.
2. Select ALPC/OPC on the menu bar, and then select Laser Power Setup menu.
3. Setup LD Power meter (Frequency :780nm, Measure Range : 0.01mW unit).
4. Click VRDC button on the Laser Power Setup window. Laser beam will be emitted from LD.
5. Measure LD Power with LD Power meter. Type the result in the blank(Read Power box).
[Ex] 2.11mW ->211
6. Click VWDC1 button and follow above step 5. But VWDC1 result should be filled in the Write Power box.
[Ex] 19.32mW ->1932
7. Click Setup button, and result will be displayed with OK or NG.
8. Close Laser Power Setup window.
66
[Laser Power Setup window]
[Laser Power Setup Frame] [Laser Power Setup Result]
67
[Laser Inspection]
[Laser Power Test Frame] [Laser Power Test Result]
D. Laser Inspection (VRDC/VWDC1, 2 FPD & Level check)1. Remove disc on the Tray.2. Select ALPC/OPC on the menu bar and select Laser Inspection menu, then Laser Power Test window
will appear.3. Click Trigger button, then the result will be displayed with OK or NG separately.4. Close Laser Power Test window.
68
[ALPC Test For AS]
[ALPC Test Mode]
E. ALPC Test for AS1. Remove disc on the Tray.2. Select ALPC/OPC on the menu bar and select ALPC Test for AS menu, then window will appear.3. Select specific mode of ALPC Test mode and click Trigger button, then LD will be on.4. Implement test like measuring LD Power.5. Click Stop button, then LD Off .
* Caution : Laser beam is emitted continuously on the VRDC Loop and CW Power Test.Pulse_Type Laser output like real writing is emitted on the CD-R Rec Mode and CD-RW Rec Mode.
71
BD
7907FS
6Ch
Servo
DR
IVE
MT
1516R
F A
mp
Wo
bb
leA
LP
CG
eneral po
rt use
EE
PR
OM
access
MT
1518
DS
PD
ecod
erE
nco
der
AT
IP D
emo
dulato
rW
rite Strateg
yW
rite S/H
Sig
nal
I / F
Micro
Pro
cessor
Au
dio
Mu
teC
ircuit
HOST
33.868MH
zO
pticalP
ick-upK
RS
-340B
SD
RA
M2M
B
I/Fcab
le
Data
Address
ST
EP
Motor
FC
ST
RK
Spindle
Motor
Writing
Pulse
Servo S
/H,
Write S
/H S
ignal
Data, C
lock, XLA
TR
eset
Lin
e Ou
t
L,R
AT
93C86
2KB
EE
PR
OM
EQ
RF
,R
RF
,F
EI,T
EI,C
SI
DM
O
FO
OT
RO
SL
O
Address/
Data
PW
M o
ut
F P
DA
BC
DE
FG
HIC
401
IC 101
IC 501
IC 103
IC 102
Au
dio
L,R
3.3 V
Reset
5V
12V
IC 203
AT
49F002N
512KB
Flash
RO
M
LD
Drive
VW
DC
VR
DC
2.5 V
FG
M
Tray M
oto
r
Drive M
ute
LE
D C
on
trol
Mech
anism
S/W
Detect
Functional Block Diagram
AT
49F040
MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTIONIC401 (MT1516) : CD-R/RW Analog Signal Processor
Block Diagram
36
A P C
RFZC1M
CLK
D IG.R E G .
M P X 1
M P X 2
VCON
RR
FX
AD
BC
O
BC
O
AD
O
FPDOX
TELP
MPPO
SPPO
DRCLP
RFRP
MP
X1
TZC
MP
X2
MPX1
ASH
BSH
DSH
ESH
CSH
FSH
GSH
HSH
MP
X2
MP
X2B
VW
DC
2O
VW
DC
1O
VR
DC
O
W R E F 1V W D C 1
V W D C 1 N
F P D O L P
F V R E FF P D O
R R E FV R D C
V R D C N
RF
PD
SH
WF
PD
SH
RLD
ON
WLD
ON
FPDOX
R R F
RR
FX
EQ
RF
GAINUP
SE
RV
SH
WB
LSH
AD
BC
O
AD
OB
CO
FE
O
MP
PO
SB
AD
O
SP
PO
S /H&
M AT R I XR O P C
F ED R C O 2
C ET ES B A DTEIN
R F Z C
S H P CR F Z C 1 V CS H B C
DEFECT
DataSlicer
RE
CD
IN
TEFE
CE
SBADOLP
INA
INB
INC
IND
HAVC
INA
INB
INC
IND
HAVC
INA
INB
INC
IND
HAVC
E Q R F
VC
ON
GAINUP
EQRF
RF
SU
M
MP
XO
UT
1
VR
EF
MP
X
AV D D 1AV S S 1AV D D 2AV S S 2AV D D 3AV S S 3AV D D 4AV S S 4AV D D 5AV S S 5AV D D 6AV S S 6AV D D 7AV S S 7AV D D 8AV S S 8AV D D 9AV S S 9
S DATAX L AT
S C L K DRCSO
DRCMO
SLP
FN
SLP
FP
XD
EF
MD
EF
M
RR
FX
LP
H11
T
I NH
ING
INF
INE
D R C O
INA
HAV
C
IND
INB
INC
T R O P E NT R AYO U T #
TRAYIN#L E D 1L E D 2
LIMIT#F R
E N D MM U T E
S BD E V S E L
E E P _ S DATAE E P _ S C L K
E E P _ C SE N B L
GIO1~GIO7
GeneralI /O
S U B G N D
T R C L O S E
ATIP
10-BitA D C
S E RVO&
Detect ion
SBAD
A S P R E Q
OS
TC
CR
FAG
CC
EQ
BIA
SE
QR
F
RO
PC
CR
OP
CO
AU X 2AU X 3
AU X 1W
RF
SU
M
RR
F
WR
F
RFZC1
TZC
Vol tageRef & DAC
VD
AC
1V
DA
C0
VR
EF
VF
VR
EF
V14
VH
AVC
V28
P /BDetect
x1
MP
XO
UT
2MPX2B
X R S T
DV
SS
2D
VD
D2
DV
SS
1D
VD
D1
S B A D L P
RE
CD
IN/R
RF
SU
M
RR
FX
LPR
RF
/WR
F
ATFMX
FPDO
ROPCO
RFAGCC
FVREF
VRDCB
VWDC1B
WREF1
VRDCO
RREF
WRFSH
AUX1AUX2
AUX3
VWDC1OVWDC2O
VD
AC
0
ATF
G
ATF
M
AG
C3C
AG
C2C
AG
C1C
WB
LCLK
37
• Pin Assignment
Pin Numbers
Symbol Type Description
RF Signals & S/H Control Pulses
36 INA Analog Input Input of Main Beam Signal (A) 37 INB Analog Input Input of Main Beam Signal (B) 38 INC Analog Input Input of Main Beam Signal (C) 39 IND Analog Input Input of Main Beam Signal (D) 30 INE Analog Input Input of Side Beam Signal (E) 31 INF Analog Input Input of Side Beam Signal (F) 32 ING Analog Input Input of Side Beam Signal (G) 33 INH Analog Input Input of Side Beam Signal (H) 34 HAVC Analog Input Reference Voltage Input of Main and Side Beams (2.0V)
120 SERVSH Digital Input (TTL),
SMT S/H Control Pulse of Main and Side Beam Signals
118 WBLSH Digital Input (TTL),
SMT S/H Control Pulse of Wobble Signal
Focus/Tracking Error & Servo Control Signals
40 DRCO Analog Output Output of Differential Radial Contrast (DRC) Signal 41 DRCO2 Analog Input Re-Input of Differential Radial Contrast (DRC) Signal 42 FE Analog Output Output of Focusing Error Signal 45 TE Analog Output Output of Tracking Error Signal 43 CE Analog Output Output of Center Error Signal 49 SBAD Analog Output Output of SBAD Signal 44 TEIN Analog Input Input of Out-of-Track Detection Circuit 50 SBADLP Analog Input Input of SBAD Signal after LPF for DEFECT Detection 46 SHPC Analog Output External Capacitor Connection for Peak Hold of RFRP Signal 47 RFZC1VC Analog Output Reference Voltage for RFRP Peak/Bottom Hold 48 SHBC Analog Output External Capacitor Connection for Bottom Hold of RFRP Signal
126 RFZC Digital Output
(TTL), 4 mA Driving Output of RF Zero Crossing Binary Signal
EQRF (RF Equalizer Filter and Data Slicer) Circuit
19 RFSUM Analog Input Input of RF Summing Signal from PUH to EQRF Block 11 EQBIAS Analog Output External Bias Connection for Circuits in EQRF Block
13 OSTCC Analog Output External Capacitor Connection for Offset Cancellation Circuit of Equalizer Output
16 RFAGCC Analog Output External Capacitor Connection for RF AGC in EQRF Block 21 RFOUT Analog Output Output of RF EFM Signal after Equalizer Filter
4 DEFM Digital Output
(TTL), 6 mA Driving Binary Output of EFM Signal after Slicing (Positive)
3 XDEFM Digital Output
(TTL), 6 mA Driving Binary Output of EFM Signal after Slicing (Negative)
8 SLPFP Analog Input Input ( ) of Auto Slicing Level 9 SLPFN Analog Input Input of Auto Slicing Level
RRF & ROPC (Running OPC) Related Signals
22 RECDIN/ RRFSUM
Analog Input (1). Input of RF Signal for Recorded Area Detection (2). Input of Read RF Summing Signal from PUH to RRF Block
70 RRFXLP Analog Output Low Pass Output of RRF Signal
38
Pin Numbers
Symbol Type Description
24 RRF/WRF Analog Output (1). Output of Read RF (RRF) Signal (2). Output of Write RF (WRF) Signal
26 WRFSUM Analog Input Input of Write RF (WRF) Summing Signal to ROPC Block 27 ROPCO Analog Output Output of Amplified B-Level of Write RF Signal 28 ROPCC Analog Input Vin(-) of Amplifier for Sampled B-Level of WRF Signal
125 H11T Digital Input (TTL),
SMT S/H Control Pulse of WRF Signal
ATIP (Absolute Time In Pre-groove) 81 AGC1C Analog Output External Capacitor Connection for AGC1 in ATIP Block 82 AGC2C Analog Output External Capacitor Connection for AGC2 in ATIP Block 83 AGC3C Analog Output External Capacitor Connection for AGC3 in ATIP Block 85 ATFM Analog Output Output of Analog Wobble Signal
116 ATFG Digital Output
(TTL), 4mA Driving Digital Output of Wobble Signal after Slicing
114 WBLCLK Digital Input (TTL),
SMT External Clock Input for Wobble BPF (SCF)
APC (Auto Power Control for Laser)
54 FPDO Analog Input Input of Laser Monitor Voltage 65 FPDOLP Analog Input Input of Laser Monitor Voltage after Low Pass Filtering 52 FVREF Analog Input Reference Voltage of APC Loops
128 RLDON Digital Input (TTL) Laser Diode Control for Read Mode 127 WLDON Digital Input (TTL) Laser Diode Control for Write Mode
112 RFPDSH Digital Input (TTL),
SMT S/H Control Pulse for Read APC Mode
111 WFPDSH Digital Input (TTL),
SMT S/H Control Pulse for Write APC Mode
55 RREF Analog I/O (1). Input of Power Setting Voltage for Read APC; (2). Output of Read APC Reference Voltage Generated by Built -in DAC
59 VRDCN Analog Input Vin(-) of Midcourse Amplifier for Read APC Loop 58 VRDC Analog Output Midcourse Output of Laser Diode Controlling in Read Mode 63 VRDCO Analog Output Output Voltage of Laser Diode Controlling in Read APC
53 WREF1 Analog I/O (1). Input of Power Setting Voltage for Write APC 1; (2). Output of Write APC Reference Voltage Generated by Built-in DAC
57 VWDC1N Analog Input Vin(-) of Midcourse Amplifier for Write APC 1 56 VWDC1 Analog Output Midcourse Output of Laser Diode Controlling in Write APC 62 VWDC1O Analog Output Output Voltage of Laser Diode Controlling in Write APC 61 VWDC2O Analog Output Output Voltage 2 of Laser Diode Controlling in Write APC
Reference Voltages & DACs 75 VHAVC Analog Output Output of Voltage Reference (2.0V) 78 VREF Analog Output Output of Voltage Reference (2.0V) 77 V14 Analog Output Output of Voltage Reference (1.4V) 76 V28 Analog Output Output of Voltage Reference (2.8V) 74 VFVREF Analog Output Output of Voltage Reference (2.5V~3.0V) 69 VDAC0 Analog I/O Output of General Purposed 8-Bit DAC (0V ~ 2.0V) 51 VDAC1 Analog Output Output of General Purposed 10-Bit DAC (0V ~ 4V)
MPXOUT (Multiplexer Circuit for Various Signals) and Testing Interface 68 AUX1 Analog Input Auxiliary Input 1 for Signal Monitoring 67 AUX2 Analog Input Auxiliary Input 2 for Signal Monitoring 66 AUX3 Analog Input Auxiliary Input 3 for Signal Monitoring
39
Pin Numbers
Symbol Type Description
71 MPXOUT1 Analog Output Multiplexer Output 1 for Signal Monitoring 72 MPXOUT2 Analog Output Multiplexer Output 2 for Signal Monitoring
Serial Interface & Other Digital Control Signals
1 ASPREQ Digital Output
(TTL), 4 mA Driving ASP request signal output to MT1508 to send control signals via serial interface.
122 SCLK Digital Input (TTL),
SMT Clock Input for Register Setting
123 SDATA Digital I/O (TTL),
4 mA Driving Data Input/Output for Register Setting
124 XLAT Digital Input (TTL),
SMT Latch Input for Register Setting
2 XRST Digital Input (TTL),
SMT Digital Input for Register Resetting
109 MCLK Digital Input (TTL),
SMT Digital Input of Main Clock
95 TRAYIN# Digital Input (TTL), 50K Pull-Up, SMT
Tr n Input, A Logical Low Indicates the Tray is IN. Feedback Flag from Tray Connector.
94 TRAYOUT# Digital Input (TTL), 50K Pull-Up, SMT
Tr Input. A Logical Low Indicates the Tray is OUT. Feedback Flag from Tray Connector.
99 LIMIT# Digital Input (TTL), 50K Pull-Up, SMT
Sledge Inner Limit Input, Active Low.
106 DEVSEL Digital Input (TTL), 50K Pull-Up, SMT
Device Select. Cleared to ZERO Indicates the Driver is Master Device. Set to ONE Indicates the Driver is Slave Device.
100 FR Digital Input (TTL), SMT Spindle Motor Reverse Detection Input.
93 TROPEN Digital Output (TTL), 4 mA Driving Tray Open Output. Initial Output.
92 TRCLOSE Digital Output (TTL), 4 mA Driving Tray
96 LED1 Digital Output (TTL), 4 mA Driving LED Control Output. Initial Output.
98 LED2 Digital Output (TTL), 4 mA Driving LED Control Output. Initial Output.
101 ENDM Digital Output
(TTL), 4 mA Driving Enable/Disable Disk Motor. A Logical High Enables Disk Motor. Initial Output.
102 MUTE Digital Output (TTL), 4 mA Driving Servo Control Power Driver Enable Output. Initial Output.
103 SB Digital Output (TTL), 4 mA Driving Spindle Motor Short Break Control Output. Initial Output.
110 EEP_CS Digital Output (TTL), 4 mA Driving EEPROM Chip Select Output.
108 EEP_SCLK Digital Output (TTL), 4 mA Driving EEPROM Transmit Clock Output.
107 EEP_SDATA Digital I/O (TTL), 50K Pull-Down, 4mA Driving
EEPROM Transmit Data Input/Output.
5 ENBL Digital Output
(TTL), 4 mA Driving
Laser Diode Enable Signal Output
40
88 GIO1
Digital I/O (TTL), 50K Pull-Up, 4 mA Driving
(1). General I/O 1 for Mass Production Use (Initial Input Mode) (2). Output of Internal Digital Signal ( VWDC1 )
Pin Numbers
Symbol Type Description
89 GIO2 Digital I/O (TTL),
50K Pull-Up, 4 mA Driving
(1). General I/O 2 for Mass Production Use (Initial Input Mode) (2). Output of Defect Detection Signal ( DEFEC )
90 GIO3 Digital I/O (TTL), 50K Pull-Down, 4 mA Driving
(1). General I/O 3 for Mass Production Use (Initial Input Mode) (2). Output of the State of Seeking ON Control Setting
91 GIO4 Digital I/O (TTL), 50K Pull-Down, 4 mA Driving
(1). General I/O 4 for Mass Production Use (Initial Input Mode) (2). Output of Internal Digital Signal ( )
104 GIO5 Digital I/O (TTL),
50K Pull-Up, 4 mA Driving
(1). General I/O 5 for Mass Production Use (Initial Input Mode) (2). Output of Out-of-Track Detection Signal
105 GIO6 Digital I/O (TTL),
50K Pull-Up, 4 mA Driving
(1). General I/O 6 for Mass Production Use (Initial Input Mode) (2). Output of Out-of-Track Detection Signal ( XTOR )
119 GIO7 Digital I/O (TTL),
50K Pull-Up, 4 mA Driving
(1). General I/O 7 for Mass Production Use (Initial Input Mode) (2). Output of Recorded Area Detection Signal ( RECD1
Power Supplies 86 , 87 SUBGND Analog Ground Ground Pin for Substrate Bias of Internal Digital Circuitry
29 AVDD1 Analog Power Power Pin for Internal Analog Circuitry (5V) 35 AVSS1 Analog Ground Ground Pin for Internal Analog Circuitry 60 AVDD2 Analog Power Power Pin for Internal Analog Circuitry (5V) 64 AVSS2 Analog Ground Ground Pin for Internal Analog Circuitry 80 AVDD3 Analog Power Power Pin for Internal Analog Circuitry (5V) 84 AVSS3 Analog Ground Ground Pin for Internal Analog Circuitry 20 AVDD4 Analog Power Power Pin for Internal Analog Circuitry (5V) 18 AVSS4 Analog Ground Ground Pin for Internal Analog Circuitry 23 AVDD5 Analog Power Power Pin for Internal Analog Circuitry (5V) 25 AVSS5 Analog Ground Ground Pin for Internal Analog Circuitry 79 AVDD6 Analog Power Power Pin for Internal Analog Circuitry (5V) 73 AVSS6 Analog Ground Ground Pin for Internal Analog Circuitry 10 AVDD7 Analog Power Power Pin for Internal Analog Circuitry (5V)
6 , 7 AVSS7 Analog Ground Ground Pin for Internal Analog Circuitry 14 AVDD8 Analog Power Power Pin for Internal Analog Circuitry (5V) 12 AVSS8 Analog Ground Ground Pin for Internal Analog Circuitry 15 AVDD9 Analog Power Power Pin for Internal Analog Circuitry (5V) 17 AVSS9 Analog Ground Ground Pin for Internal Analog Circuitry
121 DVDD1 Digital Power Power Pin for Internal Digital Circuitry (5V) 117 DVSS1 Digital Ground Ground Pin for Internal Digital Circuitry 113 DVDD2 Digital Power Power Pin for Digital I/O Pads Buffer Circuitry (5V) 115 DVSS2 Digital Ground Ground Pin for Digital I/O Pads Buffer Circuitry
IC101(MT1518) : CD-R/RW Encoder/Decoder/Write Strategy / DSP /Interface /Micro Processor
Block Diagram
41
r
AD
GO
LOD
AC
VR
EF
RO
FOOTROFMO
PWMOUT
DM
AR
QIO
RDY
INTR
QIO
CS
16#
UP
3_7/
UR
D#
UA
LE
UP
3_6/
UW
R#
RA[11:0]RAS#CAS#CASH#/RWEH#RWE#ROE#CLKCKEDQMBA(1:0)
PRST#
PDMVDDPWM2VREF
PWMVREFPDMVSS
DA
CV
DD
DA
CV
SS
SRVADCVDDFEITEI
TEZILPTEI
HRFZC
RD[15:0]
UP
0[7:
0]/U
AD
[7:0
]
HR
ST
#D
IOW
#D
IOR
#D
MA
CK
#H
A[2
:0]
CS
1FX
#C
S3F
X#
HD
[15:
0]P
DIA
G#
DA
SP
#
TEST
8032Micro-controller
Key/LEDInterface
3KSRAM
EJECT#/STOP#PLAY#/PAUSE#
Host Interface
ATAPIPacketFIFO
HostDataFIFO
AudioDigital Out
CDROMHigh-speed
Audio Playback
ResetLogic
CDROMSync
DetectionDescrambler
CIRCError Corrector
RFZC/TEZCCircuit
PDM &PWM DAC
VaripitchCLV ClockGenerator
EFMDemodulator
SubcodeDemodulator
Servo DSP
UA
16/U
P1_
0
UP
SE
N#
UP
2_7~
UP
2_0
UA
[7:0
]
UP
3_5~
UP
3_4
UR
ST
UP
3_1~
UP
3_0
CLV/CAVController
Audio/EffectInterface
Audio DAC
PWM DAC
BufferMemory
Controller
ServoADC
C3Encoder
Sync.ProtectionData
PLL
DataSlicer
DPLLVDDIREF
LPFIN
DPLLVSSLPFIP
LPFON
LPIONLPFOP
LPIOP
DMO
FG
VPVDDVCOCINVPVSS
ENDM
C3Decoder
CIRC EncoderEFM modulatoin
Subcode generator
SystemClock
Generator
ASPControl
Interface
Write StrategyInterface
Logic
Servostatus
detectioncircuit
SC
OP
RFI
NR
FIP
RF
DT
SLV
NR
FD
TS
LVP
SC
ON
EFMPLL(efmclk
synthesizer)
SD
ATA
SD
EN
SLC
KX
RS
T#
WS
R_O
DO
N
WS
R_W
XR
WS
R_C
FR
EQ
FLA
G_O
UT
1F
LAG
_OU
T2
RLD
ON
SE
RV
SH
WB
LSH
WF
PD
SH
RF
PD
SH
WLD
ON
H11
T
Laser PowerControlLogic
OPC/ROPCComputation
Unit
Time toDigital
Converter
FLA
G_O
UT
1
FM Demodulator& Bi-Phase data
Demodulator
ATIP Sync Protection &CRC check &
Target MSF Search
WobbleSpindleControl
Wobble SignalInterface Logic
ATF
G
WB
LCLK
EF
MV
CO
IN
EF
MP
LLV
SS
EF
MP
LLV
DD
EF
MLP
FG
ND
XTALIIPLLVDDIPLLVSS
XTALO
systemclock
DMU
UP
3_2/
UN
IT0#
UP
3_3/
UIN
T1#
UA
17/U
P1_
1U
A18
/UP
1_2
FMO2
SRVADCVSS
CSISBAD
42
Pin Numbers Symbol Type Description
Data PLL Interface (9)
29 DPLLVDD Analog Power(3.3V) Power supply for data PLL and related analog circuitry. 30 LPIOP Analog Output Data PLL VCO DAC positive output. 31 LPION Analog Output Data PLL VCO DAC negative output. 32 LPFOP Analog Output The positive output of loop filter amplifier. 33 LPFIN Analog Input The negative input terminal of loop filter amplifier. 34 LPFIP Analog Input The positive input terminal of loop filter amplifier. 35 LPFON Analog Output The negative output of loop filter amplifier. 36 IREF Analog Input Current reference input. It generates reference current for data
PLL. Connect an external 15K resistor between this pin and PLLVSS.
37 DPLLVSS Ground Ground pin for data PLL and related analog circuitry.
Signal Amplifier Interface (13)
38 SBAD Analog Input Sub-beam add input (E+F+G+H). 39 TEZILP Analog Input Tracking error zero crossing low pass input. 40 TEI Analog Input Tracki ng error input. 41 CSI Analog Input Central servo input. 42 FEI Analog Input Focus error input. 43 SRVADCVSS Ground Ground pin for servo ADC circuitry. 44 RFIN Analog Input RF negative signal input. 45 RFIP Analog Input RF positive signal input. 46 SRVADCVDD Analog Power(3.3V) Power supply for servo ADC circuitry. 47 RFDTSLVN Analog Input Negative input for analog slicer. 48 SCOP Analog Output Positive low pass filter output for analog slicer. 49 SCON Analog Output Negative low pass filter output for analog slicer. 50 RFDTSLVP Analog Input Positive input for analog slicer.
Turbo 8032 Interface (37)
171 UP3_7 / URD#
3.3V LVTTL I/O, Slew rate, SMT,
4mA driving, 75K pull-up
Programmable bi-directional I/O. Alternate function : RD#. Data write signal.
172 UP3_6 / UWR#
3.3V LVTTL I/O, Slew rate, SMT,
4mA driving, 75K pull-up
Programmable bi-directional I/O. Alternate function : WR#. Data write signal.
173 UP3_3 / UINT1#
3.3V LVTTL I/O, Slew rate,
4mA driving, 75K pull-up
Programmable bi-directional I/O. Alternate function : INT1#. External interrupt 1.
174 UP3_2 / UINT0#
3.3V LVTTL I/O, Slew rate,
4mA driving, 75K pull-up
Programmable bi-directional I/O. Alternate function : INT0#. External interrupt 0.
• Pin Description
43
175 UP3_1 / UTXD
3.3V LVTTL I/O, Slew rate,
4mA driving, 75K pull-up
Programmable bi-directional I/O. Alternate function : TXD. Serial transmit data.
176 UP3_0 / URXD
3.3V LVTTL I/O, Slew rate,
4mA driving, 75K pull-up
Programmable bi-directional I/O. Alternate function : RXD. Serial receive data.
177 UALE 3.3V LVTTL I/O, Slew rate, SMT,
4mA driving, 75K pull-up
Address latch enable output during internal µP mode, active high. And as address latch enable input during ICE mode.
178 UPSEN# 3.3V LVTTL I/O, Slew rate, SMT,
4mA driving, 75K pull-up
Programmable store enable output during internal µP mode, active low. UPSEN# enables the external ROM output port. And as input during ICE mode.
189,188,186, 185,184,182,
181,179
UA[7:0] 3.3V LVTTL output, Slew rate,
2mA, 4mA, 6mA 8mA PDR, 75K pull-up
Lower address bus output for external device. Alternate function : Internal monitored signal output.
190,192,193, 194,195,197,
198,199
UP2_[7:0] / UA[15:8]
3.3V LVTTL I/O, Slew rate,
2mA, 4mA, 6mA 8mA PDR, 75K pull-up
Programmable bi-directional I/O. Alternate function : A[15:8]. Upper address bus input/output.
191 FLASH_WE# 3.3V LVTTL output, 4mA driving
Flash memory write enable signal output, low active.
200 UP1_1 /UA17
3.3V LVTTL I/O, Slew rate,
2mA, 4mA, 6mA 8mA PDR, 75K pull-up
Programmable bi-directional I/O. Alternate function : A17. Address bit 17 output.
201 UP1_0 / UA16
3.3V LVTTL I/O, Slew rate,
2mA, 4mA, 6mA 8mA PDR, 75K pull-up
Programmable bi-directional I/O. Alternate function : A16. Address bit 16 output.
202 FLASH_CS# 3.3V LVTTL I/O, 4mA driving, 75K pull-up
Flash memory chip select signal output, low active.
203,204,3, 4,5,6,8,9
UP0_[7:0] / UAD[7:0]
3.3V LVTTL I/O, Slew rate,
2mA, 4mA, 6mA 8mA PDR
Programmable bi-directional I/O. Alternate function : AD[7:0]. Lower address/data bus output for external device.
205 UP1_2 /UA18
3.3V LVTTL I/O, Slew rate,
4mA driving, 75K pull-up
Programmable bi-directional I/O. Alternate function : UA18. Address bit 18 output.
Motor and Actuator Driver Interface (11)
20 FG 3.3V LVTTL Input, SMT, 75K pull-up
Motor Hall sensor input.
44
22 FOO Analog Output Focus servo output. PDM output of focus servo compensator. 23 TRO Analog Output Tracking servo output. PDM output of tracking servo
compensator. 24 PWMOUT Analog Output General purpose PWM output. 25 DMO Analog Output Disk motor control output. PWM output. 26 FMO Analog Output Feed motor control. PWM output. 27 FMO2 Analog Output Feed motor 2 control. PWM output. 51 PDMVDD Analog Power(3.3V) Power supply for PDM circuitry. 52 2VREF Analog input 2.90 V reference voltage input. 53 VREF Analog input 1.45 V reference voltage input. 54 PDMVSS Ground Ground for PDM circuitry.
Mega Interface (2)
11 EJECT# 3.3V LVTTL I/O, 75K pull-up, 4mA driving
Eject/stop key input, active low.
12 PLAY# 3.3V LVTTL I/O, 75K pull-up, 4mA driving
Play/pause key input, active low.
NC (3)
155 NC 156 NC 157 NC
IPLL VCO Interface (2)
104 IPLLVDD Analog power(3.3V) Power supply for IPLL circuitry. 105 IPLLVSS Ground Ground pin for IPLL circuitry.
EFMPLL VCO Interface (4)
207 EFMPLLVDD Analog power(3.3V) Power supply for EFMPLL circuitry. 208 EFMVCOCIN Analog input EFMPLL VCO input. For external loop filter connection. 1 EFMLPFGND Analog input EFMPLL LPF ground input. 2 EFMPLLVSS Ground Ground pin for EFMPLL circuitry.
Audio Output Interface (1)
163 ADGO 3.3V LVTTL I/O, Slew rate,
75K pull-up, 4mA, 8mA driving
Digital Audio Output. The signal is the Digital Audio Output which supplies the IEC-958 digital audio data. Alternate function : HRST_ extension selection input during power-on stage (PRST falling edge). A logical low input indicates raw HRST_ is used. A logical high input indicates extended HRST_ is used.
Internal Audio DAC Interface (5)
164 AUDACVSS Ground Ground pin for internal audio DAC circuitry. 165 LO Analog Output Left channel of audio. 166 DACVREF Analog Output Reference voltage for external audio filter circuit. 167 RO Analog Output Right channel of audio. 168 AUDACVDD Analog Power(3.3V) Power supply for internal audio DAC circuitry.
45
Write Strategy Interface (5)
13 WXR 3.3V LVTTL output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
Laser diode write power control output. (Write/Read mode SW signal)
15 ODON 3.3V LVTTL output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
Laser diode over drive control output. (Over drive control SW signal)
16 OUT1/OSCEN 3.3V LVTTL output, Slew rate,
8mA driving
Internal flag output. Include : “WSR_OSCEN” signal
18 OUT2/CMOD 3.3V LVTTL output, Slew rate,
8mA driving
Internal flag output. Include : “WSR_CMOD” signal
19 CFREQ 3.3V LVTTL output, Slew rate,
8mA driving
Frequency selection signal output.
Write strategy & ASP transmission Interface (16)
55 XRST# 3.3V LVTTL output, 4mA driving
RF reset output. Active low.
56 ASPREQ 3.3V LVTTL Input, SMT, 75K pull-down
ASP request signal input from MT1516 to get RECD1, XTOR, DEFECT automatically.
57 RLDON 3.3V LVTTL I/O, 75K pull-down,
4mA driving
Read laser diode on control signal. Alternate function : ICE mode selection input during power-on stage (PRST falling edge). A logical low input indicates internal µP is used. A logical high input indicates external µP is connected.
58 WLDON 3.3V LVTTL output, 4mA driving
Write laser diode on control signal.
60 HRFZC 3.3V LVTTL Input, SMT, 75K pull-up
High frequency RF ripple zero crossing input.
61 H11T 3.3V LVTTL output, Slew rate,
8mA driving
EFM 11T indicator for ROPC sampling.
62 XLAT 3.3V LVTTL output, 4mA driving
Latch signal output for RF register setting.
63 XDATA 3.3V LVTTL I/O, Slew rate,
75K pull-down, 4mA driving
Data signal output for RF register setting.
65 XCLK 3.3V LVTTL output, Slew rate,
8mA driving
Carrier clock signal output for RF register setting.
66 SERVSH 3.3V LVTTL output, 2mA, 4mA, 6mA,
8mA, 10mA, 12mA, 14mA, 16mA PDR
Sample pulse for servo signal (main beam/ side beam)
46
68 WBLSH 3.3V LVTTL output, 2mA, 4mA, 6mA,
8mA, 10mA, 12mA, 14mA, 16mA PDR
Sample pulse for wobble signal.
69 ATFG 3.3V LVTTL Input, SMT
Digital wobble signal (22.05 ± 1 K Hz) input
70 WBLCLK 3.3V LVTTL output, Slew rate,
4mA driving
Wobble processing clock (432.18K Hz) output for MT1516.
71 RFPDSH 3.3V LVTTL output, 2mA, 4mA, 6mA,
8mA, 10mA, 12mA, 14mA, 16mA PDR
Sample pulse control signal for RF read APC.
72 WFPDSH 3.3V LVTTL output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
Sample pulse control signal for RF write APC.
206 WRSTOP 3.3V LVTTL Input, SMT, 75K pull-down
Write procedure stop control input.
Miscellaneous Interface (4)
169 TEST_MODE 3.3V LVTTL input, 75K pull-down
Test mode, active high
170 PRST 3.3V LVTTL Input, SMT
Power on reset input, high active.
74 XTALO Output X`tal output. 75 XTALI Input X`tal input. The working frequency is 33.8688 MHz.
Host Interface (31)
122 HRST# 3.3V LVTTL Input, SMT, 75K pull-up
Host reset input. The active-low input is referred to as hardware reset and is used to reset this chip.
142,140,138, 135,132,130, 127,124,123, 125,128,131, 133,136,139,
141
HD15 ~ HD0 3.3V LVTTL I/O, Slew rate, SMT,
4mA, 6mA, 8mA, 12mA PDR,
40K(15K) PPU, 40K (15K)PPD
Host Data bus. This is the 8-bit or 16-bit bi-directional data bus to the host. The lower 8 bits, HD0–HD7, are used for 8-bit data transfers. Normally, data transfers are 16-bit wide. Note : All pins except HD7 (no any pull) may be selectively pull-up or pull-down with 40K resistant.(HD6~HD0 is 15K)
144 DMARQ 3.3V LVTTL output, 12mA driving
DMA request. This signal is used for DMA data transfers between host and device and it shall be asserted by the MT1518 when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR# and DIOW#.
145 DIOW# 3.3V LVTTL Input, SMT, 40K pull-up
Device I/O write. Stop ultra DMA burst. For Device I/O Write, this signal is the strobe signal asserted by the host to write device register or the data port. For Stop Ultra DMA, this signal shall be negated by the host before data is transferred in an Ultra DMA burst and is asserted by host during an Ultra DMA burst to signal the termination of Ultra DMA burst.
47
68 WBLSH 3.3V LVTTL output, 2mA, 4mA, 6mA,
8mA, 10mA, 12mA, 14mA, 16mA PDR
Sample pulse for wobble signal.
69 ATFG 3.3V LVTTL Input, SMT
Digital wobble signal (22.05 ± 1 K Hz) input
70 WBLCLK 3.3V LVTTL output, Slew rate,
4mA driving
Wobble processing clock (432.18K Hz) output for MT1516.
71 RFPDSH 3.3V LVTTL output, 2mA, 4mA, 6mA,
8mA, 10mA, 12mA, 14mA, 16mA PDR
Sample pulse control signal for RF read APC.
72 WFPDSH 3.3V LVTTL output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
Sample pulse control signal for RF write APC.
206 WRSTOP 3.3V LVTTL Input, SMT, 75K pull-down
Write procedure stop control input.
Miscellaneous Interface (4)
169 TEST_MODE 3.3V LVTTL input, 75K pull-down
Test mode, active high
170 PRST 3.3V LVTTL Input, SMT
Power on reset input, high active.
74 XTALO Output X`tal output. 75 XTALI Input X`tal input. The working frequency is 33.8688 MHz.
Host Interface (31)
122 HRST# 3.3V LVTTL Input, SMT, 75K pull-up
Host reset input. The active-low input is referred to as hardware reset and is used to reset this chip.
142,140,138, 135,132,130, 127,124,123, 125,128,131, 133,136,139,
141
HD15 ~ HD0 3.3V LVTTL I/O, Slew rate, SMT,
4mA, 6mA, 8mA, 12mA PDR,
40K(15K) PPU, 40K (15K)PPD
Host Data bus. This is the 8-bit or 16-bit bi-directional data bus to the host. The lower 8 bits, HD0–HD7, are used for 8-bit data transfers. Normally, data transfers are 16-bit wide. Note : All pins except HD7 (no any pull) may be selectively pull-up or pull-down with 40K resistant.(HD6~HD0 is 15K)
144 DMARQ 3.3V LVTTL output, 12mA driving
DMA request. This signal is used for DMA data transfers between host and device and it shall be asserted by the MT1518 when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR# and DIOW#.
145 DIOW# 3.3V LVTTL Input, SMT, 40K pull-up
Device I/O write. Stop ultra DMA burst. For Device I/O Write, this signal is the strobe signal asserted by the host to write device register or the data port. For Stop Ultra DMA, this signal shall be negated by the host before data is transferred in an Ultra DMA burst and is asserted by host during an Ultra DMA burst to signal the termination of Ultra DMA burst.
48
84 BA0 3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR,
75K PPD
SDRAM bank address 0 signal. For SDRAM application only.
85 ROE# 3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
RAM Output Enable, low active. For SDRAM application, this pin is “Chip Select” signal output connected to “CS#” pin of SDRAM. When two 2-bank SDRAM are used, this pin musts connect to “CS#” pin of first SDRAM.
87 RAS# 3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
RAM Row Address Strobe. This active-low output is the Row Address Strobe signal to the RAM. For SDRAM application, this pin is “row address strobe” signal output connected to SDRAM.
88 CAS# 3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
Column Address Strobe Low / Column Address Strobe. When two column address strobe pins are used, this pin is the Column Address Strobe Low signal for accessing the lower bytes of a two-CAS# 16-bit RAM. When an 8-bit DRAM is used, this pin shall be connected to CAS# of the DRAM. For SDRAM application, this pin is “column address strobe” signal output connected to SDRAM.
89 RWE# 3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
RAM Write Enable/RAM Write Enable Low. RAM write enable signal, low active. When two write enable pins are used, it is the Write Enable Low signal for writing the lower bytes of a two-WE_ 16-bit RAM. For SDRAM application, this pin is dedicated for “Write Enable” usage.
90 DQML 3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR,
75K PPD
SDRAM low-byte data output mask control signal, high active. For SDRAM application only.
116 CASH#/
RWEH#
3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
Column Address Strobe High / RAM Write Enable High. When a 16-bit DRAM is used, this active-low pin functions as Column address Strobe High for accessing the upper bytes of a two-CAS# RAM, or as Write Enable High for writing the upper bytes of a two-WE# RAM. For SDRAM application, this pin is changed to DQMH and is used to as SDRAM high-byte data mask control signal, high active.
117 CLK 3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR,
75K PPD
SDRAM clock output. For SDRAM application only.
49
118 CKE 3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR,
75K PPD
SDRAM clock enable signal output. For SDRAM application only.
106,107,108, 109,110,112, 113,115,92, 93,94,95,96,
97,98,99
RD15 ~ RD0 3.3V LVTTL I/O, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR, 75K PPU, 75K PPD
RAM Data bus. These pins are the bi-directional upper Buffer RAM data bus to the external buffer memory.
119,81,120, 121,103,102.
101,100,77,78, 79,80
RA11~ RA0 3.3V LVTTL Output, Slew rate,
2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR
RAM address bus.
Power Supply (27)
91,143,196 (3) DVDD33 Power (3.3V) Power supply for input pad buffer circuitry. 17,76,134,180
(4) DVDD25 Power (2.5V) Power supply for internal digital circuitry and general pad buffer
circuitry. 14,73,137,183
(4) DVSS Ground Ground pin for internal digital circuitry and input pad buffer
circuitry. 7,67,86,111, 129,150 (6)
DVDD33 Power (3.3V) Power supply for output pad buffer circuitry.
10,64,83,114, 126,147,187 (7)
DVSS Ground Ground pin for output pad buffer circuitry.
28 AVDD25 Power (2.5V) Power supply for dedicated digital circuitry in fully block. 21 AVSS Ground Ground pin for dedicated digital circuitry in fully block. 59 AVDD33 Power (3.3V) Power supply for dedicated digital circuitry in fully block.
50
IC501 (BD7907FS): Spindle Motor and 5ch Actuator Driver
Block Diagram
LEV
EL
SH
IFT
LEV
EL
SH
IFT
HA
LLB
IAS
FG
RE
VE
RC
ED
ET
EC
T
TS
D
PR
ELO
GIC
Current
LIMIT
PR
ELO
GIC
LEV
EL
SH
IFT
47K
47K
94K94K
47K
47K
47K
47K
47K
94K
FF
FF
FF
OS
C
OS
C
3-phaseM
AT
RIX
Current
CO
MPPolarity
CO
MP
PW
MO
UT
FG
LIMIT
LIMIT
15K15K
ST
BY
/B
RA
KE
CO
NT
RO
L
541 DVCCHU+
2HU-
3HV+
4HV-
5HW+
6HW-
7HB
8PGND1
9U
10SPVM1
11V
12GND
13GND
14GND
15GND
16GND
17PGND2
18W
19SPVM2
20SPRNF
21FG
22CTL1
23CTL2
24SPIN
25DGND
26LDIN
27VC
53 FCIN
52 TKIN
51 VCC
50 LDO+
49 LDO-
48 TKO+
47 TKO-
46 FCO+
45 FCO-
44 AVM
43 GND
42 GND
41 GND
40 GND
39 GND
38 AGND
37 SLO1+
36 SLO1-
35 SLO2+
34 SLO2-
33 SLGND
32 SLRNF2
31 SLRNF1
30 SLVDD
29 SLIN2
28 SLIN1
51
• Pin Description
Terminal Symbol Description1 HU+ Hall amp.U positive input
2 HU- Hall amp.U negative input
3 HV+ Hall amp.V positive input
4 HV- Hall amp.V negative input
5 HW+ Hall amp.W positive input
6 HW- Hall amp.W negative input
7 HB Hall bias
8 PGND1 Spindle driver power ground 1
9 U Spindle driver output U
10 SPVM1 Spindle driver power supply 1
11 V Spindle drive output V
12 GND GND
13 GND GND
14 GND GND
15 GND GND
16 GND GND
17 PGND2 Spindle driver power ground 2
18 W Spindle driver output W
19 SPVM2 Spindle driver power supply 2
20 SPRNF Spindle driver current sense
21 FG Frequency generator output
22 CTL1 Driver logic control input 1
23 CTL2 Driver logic control input 2
24 SPIN Spindle driver input
25 DGND PWM block pre-ground
26 LDIN Loading driver input
27 VC Reference voltage input
Terminal Symbol Description54 DVCC PWM block control power supply
53 FCIN Focus driver input
52 TKIN Tracking driver input
51 VCC BTL pre and Loading power supply
50 LDO+ Loading driver positive output
49 LDO- Loading driver negative output
48 TKO+ Tracking driver positive output
47 TKO- Tracking driver negative output
46 FCO+ Focus driver positive output
45 FCO- Focus driver negative output
44 AVM Actuator driver block power supply
43 GND GND
42 GND GND
41 GND GND
40 GND GND
39 GND GND
38 AGND Ground
37 SLO1+ Sled driver 1 positive output
36 SLO1- Sled driver 1 negative output
35 SLO2+ Sled driver 2 positive output
34 SLO2- Sled driver 2 negative output
33 SLGND Sled driver power ground
32 SLRNF2 Sled driver 2 current sense
31 SLRNF1 Sled driver 1 current sense
30 SLVDD Sled driver Power MOS pre-supply
29 SLIN2 Sled driver 2 input
28 SLIN1 Sled driver 1 input
* Positive/negative of the output terminals are determined in reference to those of the input terminals.
• Functional description
CTL1(22pin) CTL2(23pin) Spindle Sled Focus Tracking Loading
L L X X X X X
H L X X X X O
_ H O O O O X
CTL1(22pin) CTL2(23pin) SPIN > VC SPIN < VC
L H Forward-rotation mode Reverse-rotation braking mode
H H Forward-rotation mode Short-circuit braking mode
O : ON, X : OFF
¥L
¥M
¥N
¥O
¥LStanby mode ¥M Drivers muting ¥N Reverse-rotation mode (spindle) ¥O Short-circuit braking mode (spindle)
1. CABINET and CIRCUIT BOARDDISASSEMBLY
1-1. Bottom ChassisA. Release 4 screws (A) and remove the Bottom Chassis
in the direction of arrow (1). (See Fig.1-1)
1-2. Front Bezel Assy A. Insert and press a rod in the Emergency Eject
Hole and then the CD Tray will open in the directionof arrow (2).
B. Remove the Tray Door in the direction of arrow (3) by pushing the stoppers forward.
C. Release 3 stoppers and remove the Front Bezel Assy.
1-3. Cabinet and Main Circuit BoardA. Remove the Cabinet in the direction of arrow (4).
(See Fig. 1-3)B. Release 2 hooks (a) and remove the CD Tray
drawing forward.C. Remove the Main Circuit Board in the direction of
arrow (5).D. At this time, be careful not to damage the 4
connectors, are positioned at right side, of the MainCircuit Board.
2. MECHANISM ASSY DISASSEMBLY2-1. Pick-up UnitA. Release screws (B).B. Separate the Pick-up Unit in the direction of arrow (6).
(4)
(5)
MainCircuit Board
Cabinet
Hooks (a)
(A)
(A) (A)
(A)
(1)
Bottom Chassis
(2)
(3)
Tray Door
CD Tray
Front Bezel Assy
Emergency Eject Hole
Stoppers
Fig. 1-1
Fig. 1-2
DISASSEMBLY
8
Fig. 1-3
Mechanism Assy
Pick-up Unit(6)
(B)(B)
Fig. 2-1
ATIP Absolute Time In Pre-groove.With an additional modulation of the “Wobble”,the “Groove” contains atime code information
Wobble The pre-groove in the Disc is not a perfect spiral but is wobbled with ; - a typical amplitude of 30ns- a spatial period of 54 -64µm
(Pre-) groove The guidance track in which clocking and time code information is stored by means of an FMmodulated wobble
CW Continuous Wave. The laser light output is at a constant level
DOW Direct Over-Write. The action in which new information is recorded over previously recordedinformation in CD-RW disc.
Overwrite The action in which new information is recorded over previously recorded information
Land Land is characterized in the following way: When radial signals are concerned,land is defined as the area between the grooveWhen HF signal are concerned,land is defined as the area between the marks(pits) in tangentialdirection
Hybrid Disc A Multisession disc of which the first Session is mastered. On a hybrid disc, recorded and masteredinformation may co-exist
Mastered Information Information,stored as pits on the disc during the manufacturing process of the disc (when making the“master”)
OPC Optimum Power Control. Procedure is determined optimum recording power according to CD-R/RWMedia in recording start step.
ROPC Running OPC. The purpose is to continuously adjust the writing power to the optimum power that isrequired When the optimum power may change because of changed conditions of disc and change inoperating temperature,
Jitter The 1ø value of the time variation between leading and trailing edges of a specific (Mark) pit or landas measured by Time Interval Analysis
Deviation The difference between a fixed value of Pit length and Land length
TOC Table Of Contents : in the Lead-in Area the subcode Q-channel contains information about the Trackon the disc
Packet Writing A method of writing data on a CD in small increments. Two kinds of packets can be written : Fixed-length and Variable-length
Write Strategy The shape of the HF write signal used to modulate the power of the laser. The Write Strategy mustbe used for recordings necessary for disc measurements
Information Area Wobble, ATIP, Disc Identification, Write Power, Speed Range OPC Parameters, etc are recorded inthe Information area of CD-RW Disc
Finalization The action in which (partially) unrecorded or logically erased tracks are finished and the Lead-inand/or Lead-out areas are recorded or overwritten with the appropriate TOC subcode
Logical Erase A method to remove information from a disc area by overwriting it with an EFM signal containingmode 0 subco A logically erased area is equivalent to an unrecorded
Physical Erase The action in which previously recorded information is erased by overwriting with a CW laser output.After a Physical Erase action ,the erased area on the CD-RW disc is in the unrecorded state again.
Session An area on the disc consisting of a Lead-in area ,a Program area,a Lead-out area.
Multi session A session that contains or can contain more than one session composed Lead-in and Lead-out
GLOSSARY
16
The differences of CD-R/CD-RW discs and General CD-ROM1. Recording Layer
Recordable CD has a wobbled pre-groove on the surface of disc for laser beam to follow track.
2. Disc Specification
Read-only Disc
CD-R and CD-RW Disc
3~11T
1.6um
0.4~0.5 um
(Pit)Groove
Land
Track pitch(p)
Radial Direction
Iw
A
O
a
a
GrooveLand
Radial Error Signal
The Groove wobble
Average center
Actual center
17
CD-ROM (READ-ONLY DISC) a=30nm
ITEM CD-ROM CD-R CD-RW
Standard Yellow Book Orange Book II Orange Book III
Record Not available Write once Re-Writable
Tracking Signal I11/Itop > 0.6 > 0.6 0.55 > M11> 0.70(HF Modulation)
Read Laser Power(mW) < 0.5 mW < 0.7 mW < 1.0 mW
Jitter < 35 nsec < 35 nsec < 35 nsec
Reflectivity (Rtop) 70 % 65 % 15 % ~ 25 %Remark)
Write Laser Power(mW) 14-65 mW 6-45 mW
18
3. Disc Materials
1) CD-ROM disc
Laser Beam Groove
Substrate(Polycarbonate)
Organic Dye LayerReflective LayerProtective Layer
Label Printing
2) CD-R disc
Pigment Reflective Layer Color
Phtalocyanine Gold/Silver Yellow/White
Cyanine Gold/Silver Dark Green/Bright Green
Azo Gold/Silver Dark Blue
• It is composed of Silver _ colored aluminum plate and Reflective layer.• Groove (Pit) of aluminum plate make a track.• Laser wavelength : 780 nm, Laser Power (Read): 0.5mW• Signal is detected by the
difference of reflective beam intensity between “pit” and “Land” on the disc.
• It is so-called WORM (Write Once Read Many) CD.• It is composed of polycarbonate layer, Organic dye layer, Reflective layer, and Protective
layer.Gold/Silver Reflective layer is used to enhance the reflectivity• According to the kinds of Organic dye layer, it is divided by Green CD, Gold CD, Blue CD.• Laser Wavelength : 780 nm, Laser Power (read) : 0.7 mW• Recording Power : 8x(14~20mW), 12x(15~30mW), 16x(25~35mW), 48x(50~65mW)• When some part of dye layer is exposed to laser heat, it’s color changs black.Therefore, writing and
reading is enabled by the difference of reflectivity between changed part and unchanged part.• Polycarbonate layer has Pre_Groove which make a Track.
Laser BeamPit
Substrate(Polycarbonate)
Reflective Layer
Protective Layer
Label Printing
19
3) CD-RW Disc
4. Reading process of Optical Disc
Laser Beam Groove
Substrate(Polycarbonate)
Recording LayerDielectric Layer(TL)
Dielectric Layer(UL)
Protective Layer
Label Printing
• It is composed of polycarbonate layer, alloy(silver, arsenic) layer, aluminum reflectivity layer, protective layer.• An crystalized alloy layer is transformed into noncrystalized by the laser heat. Therefore, writing and reading
is enabled by the difference of reflectivity.• It is possible to overwrite about 1000 times.• Laser Wavelength : 780 nm, Laser Power (Read) : 1.0mW• Recording Power : Erase (4~18mW), Write (6~45mW)• When disc rewriting, new data is overwritten previously recorded data.• Polycarbonate layer has a Pre-Groove which make a track.
LensH
D
BeamSpot
FocusingLens
Laser Spotat ConstantRead Intensity
ReflectedLightSignal
Laser SpotPosition(Time)
Previously Recorded Marks
Groove Land Mirror
I3 Itop
I11 IG IL I0
Numerical aperture: NA=nsinθ, n: Refractive index
Focus depth : H = λ/NAlaser spot diameter : D = λ/NA2
θ
20
5. Writing Process of CD-R Disc
a b c d e f g
a
b
c
d
e
f
g
IncidentLaserPower
(Read) (Read)
(Write)
Laser SpotPosition(Time)
a b c d e f gLaser SpotPosition(Time)
LaserSpot
RecordedMark
ReflectedLightSignal
ReflectedLightSignal
Below "ORP"– Mark Too Short
At Optimum Record Power ("ORP")
Above "ORP" – Mark Too Long
Time
6. Writing process of CD-RW Disc
Write Power
Erase Power
Read Power
Groove
Crystal Amorphous
Amorphous
Recorded state(lower reflectivity)
Melting/quenching
Heating/gradual cooling
Crystal phase
Erased state(higher reflectivity)
7. Organization of the PCA, PMA and Lead-in Area
1) Layout of CD-ROM disc
21
Center hole Clamping and Label Area Information Area
Lead-in Area
Lead-in Area
Diameter 15 mm
Diameter 46 mm
Diameter 120 mm
Program Area
Read Only Disc
Lead-out Area
Program Area Lead-out Area
Center hole Clamping and Label Area Information Area
PCA PMA
Test Area Count Area
Diameter 15 mm
Diameter 45 mm
Diameter 120 mm
Unrecorded Disc
Tsl-00:35:65 Tsl-00:15:05 Tsl-00:13:25 Tsl 99:59:7400:00:00
in out
Test Area : for performing OPC procedures.
Count Area : to find the usable area immediately in T.A
Tsl : start time of the Lead-in Area, as encoded in ATIP
PMA : Program Memory Area
Disc Center
Disc Center
2) Layout of CD-R/RW disc
22
8. Function of PCA and PMA area
1) PCA (Power Calibration Area)
• PCA area is used to determine the correct Laser Power for a disc.– Method 1 : PCA area is divided by a track.– Method 2 : The previous Calibration value is referred to.– Method 3 : ROPC is used to determine Laser Power value automatically in data writing.
• CD-R Disc can write maximum 99 Tracks but CD-RW Disc can write unlimited tracks because it has a rewritable function.
2) PMA (Program Memory Area)
• It has a track information (track No, track Start/End time) of every track before writing completed.– PMA area has the last written point and the next writable point of a disc.– In case of CD to CD copy, some writer may not write PMA area.
* When Disc is Finalized,PMA information is transferred to the Lead_In area so that general Driver can read it.
* Because PCA and PMA area exist before Lead-In area, General CD Player or CD-ROM Drive can’t read these areas.
9. OPC and ROPC
1) OPC (Optimum Power Control)• This is the first step of writing process, because CD writer has its own laser power value and media have different writing characteristics,– This is determined by the Writing characteristic, speed, temperature, and humidity.– Laser wavelength is determined by the environmental temperature (775~795nm) and Optical Laser Power is
determined by the test and retry.
• Asymmetry and optimum writing Power– EFM signal Asymmetry is determined by the writing power.
Therefore, Optical Power which has the same value to the preset power value can be estimated by measuring HF signal Asymmetry on the PCA area.
• Measurement of Asymmetry* Parameter setting (Beta) : Using AC coupled HF signal before equalization
Beta = (A1+A2)/(A1-A2)
Time P << Po TimeP = Po
HF
Sig
nal A1
0
A2
TimeP >> Po
2) ROPC (Running Optimum Power Control)
• Variable primary factor of Optimum Power– Change of Power sensitivity on the Disc. (limited to 0.05 *Po)– Wavelength shift of the laser diode due to the operating temperature change.– Change of the Spot aberration due to the Disc skew,
Substrate thickness, Defocus.– Change of Disc or Optics conditions due to the long term OPC
==> It is necessary to adjust continuously to obtain the Optimum Power.
• Principle of Running OPC– To meet the factors mentioned above,
a horizontal direction movement of a curve is uesd.– Beta = f(B-level) = constant on the Recorded Disc– Procedure of ROPC
a. Reference B-level is determined during OPC Procedure.b. During Recording, B-level value is controlled to have a close
Reference B-level value.c. Normalization of B-level is used to eliminate the effect of reflectivity fluctuation.
==> The reflected B-level value is normalized by the disc reflectivity itself.
23
CD-R/RW Media
Write StrategyDetermination
PCA Test Area
Program Area
PMA Area
Lead-In Area
Lead-out Area
OP
C
PCA Count Area
RO
PC
Incident recording pulse
Reflected recording pulse
Sampled timing B
11T
Sample B-level (Write Power)
Leve
l B
Sampled at timing B
Pwo decided by OPC
Recording Power
Level B with Pwo
normalized to recording power
Sample Disc Reflectivity (Read power)
10. Writing Process of DISC
24
11. Recording capacity of CD-R/RW (74min Recording media) • (2048 Byte / Sector ) x ( 75 Sector / Second ) x ( 60 Second / Minute) x 74 Minute
= 681,984,000 Bytes = 682 Mbytes
• But the actual recording capacity is about 650 Mbytes. (according to the ISO 9660 standard,approximately 30 Mbytes are used to make directory structure and volume names.)
12. Super Link
Super(SUPpressed Error Recording) link method is a new technology to link the interrupted recording bybuffer under run. When drive’s buffer will be under, the drive will stop recording and store the stop position.When drive’s buffer receive data from HOST again, the drive will seek to the stop position of last recordingand continue writing. In the read procedure, the drive can not find any error in the linking area, the data oraudio will be regenerated perfectly.
13. Optimum record speed
To prevent record fail or readability problem of recorded disc, the drive should decide optimum recordingspeed during the recording for the media.
1) All media do not support 48x recording by media quality. Even though a CD-R can be recorded by 48x,there is a possibility to occur fail during recording, especially in high speed writing.
2) So during the recording, Drive checks the Atip and Servo errors, and Drive thinks the current recordingstatus is unstable, then decreases the recording speed for getting stable record.
3) Drive changes the write pulse and power for low speed CLV recording and continuously checks Atip andServo errors during recording.
WritingSpeed
32X
24X
16X
48 74 Time[min]
Normal Case
Speed Down Case
40X
48X22 to 48X CAV(9540 RPM)
14. Full/Partial CAV & Zone CLV Recording Comparison
25
Full/Partial CAV Zone CLV
Advantage
Disadvantage
1. Reduce Recording time. ( no loss time for speed change )2. Easy to Spindle RPM control
1. Increase a stability of Recording.( 4 CLV zone : 16, 24, 32, 40x )
2. High Recording quality compare to P-CAV.
1. It is difficult to control servo stability of CAV recording.2. It has a difficulty in getting the high Recording quality relative to Zone CLV.
1. Recording time is longer than partial CAV.2. It needs to control the spindle in speed change area.
Data transfer rate
RPM
* Full/Partial CAV
16X
40X CLV
Time
CLV Speed change
Time
0
24X 32X
* Zone CLV
40X PCLV
Time
Spindle Mode Change
Time
0
9020
22x
954048x CAV
40x PCAV
20x
48X CAV
INTERNAL STRUCTURE OF THE PICK-UP1. KRS-340B Circuit Diagram
26
1
2
3
4
5
6
7
123
45
123456789
101112 13
1415161718192021222324
14
13
12
11
10
9
8
109876
R3
VR1
VR2
R2
C6
C4
C7
LD
C5
R4
R1
L1
R5R6
C8
R7
C11 C10 C9
Vcc
2 Axis Actuator OP output terminal
IC1CXA2660N
IC2
C1
C2C3
GNDG
D
C
E
RRF
WRF
GND
H
A
B
F
Vc
VLIM
GNDGNDGNDVccVc
BinOUT
PDINVOUT
VCCVREF
VCCGNDIOUTIINRIOUTIIN2GNDIIN3
GNDRFREQ
RAMPGND
ENABLEGND
OSCENWEN3VCCWEN2GNDGND
7
8
910
1112131415161718
1920212223242526272829303132
654321 FCS +
FCS -TRK +TRK -LIMGDCE
RRFWRF
PDGNDPDVC
FBAH
PDVCCFPDO
FPDVCCFPDGNDFPDVC
LDVCCLDVCCVRDC
VWDC1VWDC2LDGNDLDGND
WE1WE2
OSCEN
3334
ENBL MODAMP
IC3EL6215CU
2. Signal detection of the P/U
1) Focus Error Signal ==> (A+C)-(B+D)This signal is generated in RF IC (IC401 : MT1516) and controls the pick-up’s up and down to focus onDisc.
2) Tracking Error Signal (DPP Method) ==> {(A+D)-(B+C)}- k x {(F+H)-(E+G)}This signal is generated in RF IC (IC401 : MT1516) and controls the pick-up’s left and right shift to find totrack on Disc.
3) RF Signal ==> (A+B+C+D)This signal is converted to DATA signal in DSP IC (IC101 : MT1518).
27
Pick-Up module
Photo Diode Tracking
Focusing
Infrared Iaser
k[(F+H) - (E+G)]
(A+D) - (B+C)
(A+D) - (B+C) - k[(F+H) - (E+G)]
Offset
TE
Tp
Sub2
Main
Tp/2 Sub1
Track Center
F,E
D,CA,B
H,G
DESCRIPTION OF CIRCUIT1. ALPC (Automatic Laser Power Control) Circuit1-1. Block Diagram
28
MT1518
Write Strategy
Write S/H Signal
Micro Processor
IC 101
CN 201
IC 401 ( MT1516 )
OpticalPick-upKRS-340B
LDDrive
19 54
65
FPDO
FPDOLP
6226
VWDC1OVWDC1
6127
VWDC2OVWDC2 127 58
WLDON
128 57
RLDON
6325
VRDCOVRDC 112 71
RFPDSHS/H &VRDCG &Level Shift
111S/H &
VWDC1G &Level Shift
VWDC1DAC
& Gain
WFPDSH
72
WDAC2&
Amplifier
WDAC1& x1/x2
RDAC
VRDCDAC
& Gain
22 52
FVREF
+
-
-
+
1-2. ALPC(Automatic Laser Power Control) Circuit Operation
ALPC function in CD-R/RW analog front-end is for constant power level control purpose.Based on the accurate power sensor(FMD) in PU, APC feedback loop maintains constant power level againstlaser diode¡fls temperature variation.
There are two power control loops in MT1516, which are used with different combination for differentapplications. Generally, the first APC loop is used for read-power control. The 2nd APC loop is used forwrite(erase) power control for CD-R(CD-RW) disc.
Owing to the small signal level in read-power control mode, the first APC loop amplifies (x5/x10/x15/20x) theFMD signal(FPDO) to enhance the accuracy of read power control. The built-in 8-bit DAC(RDAC) is used to setthe read power level. Moreover, the 2nd APC loop is used for high power control. The built-in 10-bitDAC(WDAC1) is used to set the wanted power level. And the register VWDC1G is employed to adjust the gainof FMD signal.
The following potentiometers(VRDCDAC, VWDC1DAC, and WDAC2) and amplifiers(VRDCDAG, VWDC1DAGand WDAC2G) are used to set the wanted levels of the output pins VRDCO, VWDC1O, and VWDC2O.Moreover, the input signal FPDO after low-pass filtering & amplification(x1 or x2) will send the MPXOUT2 formonitoring.
29
2. Focus Circuit
2-1. Block Diagram
DiscMotor unit
OpticalPick-up
KRS-340B
A,B,C,DE,F,G,H
-{(A+C)-(B+D)}
HAVC LS to V14
FEO
FEI
ADC Focusing Compensator
DAC
FRO
FRO
1.4V
R149
IC501
BD7907
C562R560
IC505 R566
FCS+
FCS-
FCS+FCS-
IC401MT1516
IC101MT1518
MUTE2
MUTE1
CTL1
CTL2
MUTE2
MUTE1
C188VC1.4V
FCIN
-((E+F+G+H))
LPF G
HAVCLS to
0.8V
SBAD
SBAD
49
LPF G
101
102
42
42
38
22
53
27
22
23
46
45
2-2. Focus Servo
The aim of Focus Servo is to maintain the distance between object lens of P/U and disc surface, so that thedetected RF signal(A, B, C, D, E, F, G, H) can be maximized.
Focus Error Signal(FE) generates from focus error detection block in RF IC(MT1516) using AstigmatismMethod. Focus Gain and path can be changed at the RF IC(MT1516) according to the disc, and the resulting outputFE(MT1516 42pin) is input to DSP IC(MT1518 42pin).The SBAD Signal(MT1516 49pin) is from the sum of Side Beam(E, F, G, H), represents Beam Strength andinput to DSP IC(MT1518 38pin). The Focus Search operation is using FE, SBAD Signal, therefore check FE, SBAD signals when Focusing isfailed.
The role of DSP IC(MT1518) is Focus Digital Controller. The operation path is as follows; FE Signal is input to DSP IC(MT1518 42pin), and after A/D Conversion, Digital Equalizer Block and D/AConversion in MT1518, the output signal FRO(MT1518 22pin) is input to Drive IC(BD7907 53pin).The drive output signal FCS+/FCS- generated according FCIN(BD7907 53pin), and drives focus actuator in theP/U unit.
3. Tracking & Sled Circuit3-1-1. Block Diagram (Tracking Following)
DiscMotor unit
OpticalPick-up
KRS-340B
A,B,C,DE,F,G,H
TEO
TEI
ADC TrackingCompensatorDAC
TRO
TRK+TRK-
IC401MT1516
IC101MT1518
MUTE2
MUTE1MPPO
(A+D)-(B+C)
G
HAVCLS to V14
101
102
45
4023
LPF
LPF
SPPO
K*{(F+H)-(E+G)}
SledCompensatorPWM
FMO
26
FMO2
27A+
A-
B+
B-
SLED MOTORUnit
TRO
1.4V
R148
IC501
BD7907
C561R561
IC505 R567
TRK+
TRK-
CTL1
CTL2
MUTE2
MUTE1
C187
VC1.4V
TRKIN52
27
22
23
46
45
FMO28
FMO229
R148
R148
C154 C156
SLIN1
SLIN2
A+
A-
46
45
B+
B-
46
45
SLO1+
SL01-
SLO2+
SLO2-
30
3-1-2. Block Diagram (Seek)
31
DiscMotor unit
OpticalPick-up
KRS-340B
A,B,C,DE,F,G,H
TEO
TRK+TRK-
IC401MT1516
MUTE2
MUTE1MPPO
(A+D)-(B+C)
G
HAVCLS to V14
101
102
45LPF
LPF
SPPO
K*{(F+H)-(E+G)}
A+
A-
B+
B-
SLED MOTORUnit
(A+D)-(B+C)
K*{(F+H)-(E+G)}
40
41 G
HAVCLS to V14
LPF 126
46
47
48
RFRPSLV
C48
0
G
HAVCLS to V14
43LPF
MPPO
Vref
-
+
-
+
+
-
TEO
RFZC
RFZC
DRCO
DRCO2
R456
C489
CSI
FMO
DAC
TrackingCompensator
IC101MT1518
23
SledCompensator
ADC
26
27
27
MUX
ShortSeek
Algorithm
LoogSeek
Algorithm
PWM 27
102
26
TRO
FMO2
Track Counterand Timer
R141
C142
RFZC
TEO
CSI
TEI
TEZILP
HRFZCI
CSI
32
3-2-1. Tracking Servo
The aim of tracking servo is to make laser beam trace the data track on disc.
Tracking Error(TE) Signal is generated from tracking error detected block in MT1516 using DPP(DifferentialPush-Pull) Method.DPP Method uses not only main beam(A, B, C, D) but also side beam(E, F, G, H) for correcting DC offset generated in Push-Pull Method.
The remaining procedure of TE signal processing in MT1518 is similar to Focus Servo.The role of DSP IC(MT1518) is Tracking Digital Controller.TE Signal is input to DSP IC(MT1518 40pin), and after A/D Conversion, Digital Equalizer Block and D/AConversion in MT1518, the output signal TRO(MT1518 22pin) is input to Drive IC(BD7907 23pin).
The drive output signal TRK+/TRK- generated according TKIN(BD7907 52pin), and drives tracking actuatorin the P/U unit.
3-2-2. Sled Servo
The working distance of tracking actuator is too short to cover whole disc radius.Sled Servo make P/U move by little and little so that the laser beam keep tracing the data track on disccontinuously when tracking actuator reaches the working limit.
TE Signal is input to DSP IC(MT1518 40pin), and after A/D Conversion, Digital Tracking Equalizer Block,Digital Sled Compensator Block and PWM Conversion in MT1518, the output signal FMO, FMO2(MT151826,27pin) is input to Drive IC(BD7907 28,29pin) after Low-Pass filtering.The PWM output signal A+, A-, B+, B- generated according to SLIN1, SLIN2(BD7907 28,29pin), anddrives the sled motor.
4. Spindle Circuit4-1-1. Block Diagram (EFMCLV Servo)
4-1-2. EFM CLV Servo : 4x, 8x
When drive read PRESS CD at the speed of 4x, 8x, the spindle motor is controlled using EFM CLV SpindleServo.
The equalized RFOUT Signal(MT1516 21pin) is generated using RFSUM signal from P/U, and input to DSP IC(MT1518 45pin) as RFIP.The spindle controller in MT1518 uses RFOUT signal as linear velocity feedback, therefore the EFM CLV servodoesn¡flt work well if RFOUT signal is abnormal. The spindle controller PWM output signal DMO (MT1518 25pin) input to SPIN in Drive IC(BD7907 24pin) afterLow-Pass Filtering. The PWM output signal U, V, W signal(BD7907 9, 11, 18) drives Spindle Motor using Hall Sensor Output signal(HU+, HU-, HV+, HV-, HW+, HW-) and SPIN.
33
DiscMotor unit
OpticalPick-up
KRS-340B
RFSUM
-{(A+C)-(B+D)}
Offset Adj.
RFOUT
IC401MT1516
MUTE2
MUTE1
EQRF G
101
102
2119 G
OSTCC13
C430
RFIPDataSlicer
DataPLL
IC101MT1518
44
MUX
PWM
DMO
25
Motor KickREG
CLV FD+
CLV PD
PCK4M
VCK4M
PCK4M 45
RFIN
C141
C410
C153
1.4V
R146
SPIN
IC501
BD7907
U
V
MUTE2
MUTE1
VC1.4V
24
22
23
9
11
HU+
2 HU-
21
C506
HV+
HV-
3
4
HW+
HW-
5
6
1
27
SPIN
FG
CTL2
CTL1
C507
C508
SPIN
FG
W 18
4-2-1. Block Diagram (FGCAV Servo)
34
DiscMotor unit
OpticalPick-up
KRS-340B
XTALOControl Clock
Generator
IC101MT1518
75
MUX
PWM
DMO
25
Motor KickREG
CAV FD+
CAV PD
PCK4M
VCK4M
VCK4M 74
C153
1.4V
R146
SPIN
IC501
BD7907
U
V
MUTE2
MUTE1
VC1.4V
24
22
23
9
11
HU+
2 HU-
21
C506
HV+
HV-
3
4
HW+
HW-
5
6
1
27
SPIN
FG
CTL2
CTL1
C507
C508
SPIN
FG
W 18
XTALI
20
R543
3.3V
X10133.8688MHz
4-2-2. FG CAV Servo
1) CD 15x CAV : Eccentric CD-R/RW, Video CD, CD-DA2) CD 32x CAV : (CD-RW)3) CD 40x CAV : CD-R, CD-RW4) CD 48x CAV : CD-ROM
When drive read PRESS CD, Closed Session CD-R/RW, the spindle motor is controlled using FG CAV SpindleServo. FG signal(BD7907 21pin) input to FGIN in DSP IC(MT1518 20pin).The spindle controller in DSP IC uses FGIN as spindle rotation frequency feedback, therefore the FG CAVSpindle Servo doesn't work well if FG generation is abnormal.
The spindle controller PWM output signal DMO(MT1518 25pin) input to SPIN in Drive IC(BD7907 24pin) after Low-Pass Filtering. The PWM output signal U, V, W signal(BD7907 9,11,18) drives Spindle Motor using Hall Sensor Output signal(HU+, HU-, HV+, HV-, HW+, HW-) and SPIN, and FG pulse output is generated as 18 pulses/rotation.
4-3-1. Block Diagram (Wobble CLV Servo)
35
DiscMotor unit Optical
Pick-upKRS-340B
IC401MT1516
85
HPFS/H
-
+
WBLSH
C485
36
39
37
38
HPF AGC2
LPFBPF AGC3
LPF
HPF116
118
34 75
WBLSH
VHAVCHAVC
81 82
AGC1
5V
83
VREF
AGC1C AGC2C AGC3C
ATFM
INA
INB
INC
IND
D
A
C
B
+
-
C486 C487
ADO
BCO
IC101MT1518
MUX
PWM
DMO
25
Motor KickREG
FD+
PD
69C153
1.4V
R146
SPIN
MUX
ReferenceClock Gen.
FD+
PD
CLK33M
ATFG
EFMCLK4
ATFG_SYNC
EFM_BLOCK_CLK
ATIP_BLOCK_CLK
TrackingClock Gen.
ATFG
4-3-2. Wobble CLV Servo : 4x, 10x, 12x, 16x, 24x, 32x, 40x, 48x. (Blank Area in CD-R/CD-RW)
When drive read/write blank CD-R/RW or read open-session CD-R/CD-RW, the spindle motor is controlledusing Wobble CLV Spindle Servo.
The ATFG signal(MT1516 116pin) input to DSP IC(MT1516 69pin). The DSP Controller in MT1518 uses ATFGas linear velocity feed back, therefore the Wobble CLV Spindle Servo doesn¡flt work well when ATFG signal isabnormal.The two types are in the Wobble CLV Spindle Servo. The one is pre-sync mode, the other is sync mode. When Wobble CLV Spindle Servo drives the spindle motor, the pre-sync mode type of Wobble CLV spindlecontroller controls the spindle motor.After being stabilized, the pre-sync mode is switched to the sync-mode type of Wobble CLV spindle controller.
The spindle controller PWM output signal DMO(MT1518 25pin) input to SPIN in Drive IC(BD7907 24pin) afterLow-Pass Filtering. The PWM output signal U,V, W signal(BD7907 9,11,18) drives Spindle Motor using Hall Sensor Output signal(HU+, HU-, HV+, HV-, HW+, HW-) and SPIN.