introduction to analog design in submicron cmos...

Manila, December 2002

Introduction to Analog Design in Submicron

CMOS TechnologiesGiovanni Anelli

CERN - European Organization for Nuclear ResearchExperimental Physics Division

Microelectronics GroupCH-1211 Geneva 23 – Switzerland

[email protected]

Microprocessor Laboratory Asian Course on Advanced VLSI DesignTechniques using a Hardware Description Language

Manila, The Philippines

25 November – 13 December 2002

Giovanni Anelli, CERN 2Manila, December 2002

The MOST important thing…


A second tip…

D��

� f1

WLCK

g1

kTn4f

v2ox

a

m

2in

2

2

2

)x(

e21

)x(p ��

�

��

fRkT4

i2n ��

2t

DS

n2I

.C.I�

�

qkT

t ��

� 21.C.I41

41

.C.I61

21

.)C.I(F

��

2

2BGD,n

2TOT,n

DUT,n)f(G

)f(V)f(V)f(E

��

L W

A

L W

A 2C

2ox�� P

EE'

2/

L W

tConst ox

Vth

4 N��

d)ld

(FnL 2 ��

Adn

Al

R w ��

sRC1

)s(V)s(V

)s(Hin

out ��

2220

40

2

n nh8qmZ

E�

��

2TGSDS )VV(

n2I �

�

DSTGSGS

DSm I

n2)VV(

nVI

g

��

��

�

)e1(eLW

II t

DS

t

GS

nV

nV

0DDS�

��

SAT_DS

E

SAT_DSds0 I

LVI

1g1

r

��

��

gs

mmax C

g21

f�

�

)VV(1 TGS

0

��

��

��

�2/T

2/T

2av dt)t(x

T1

limP


Outline

• Semiconductor physics� Silicon and silicon dioxide properties� Band diagram concept� Intrinsic and doped semiconductors� Carrier mobility in silicon

• CMOS technology: an analog designer perspective� The MOS transistor� DC characteristics� Important formulas� Small signal equivalent circuit� Some cross sections of real integrated circuits


Outline




Insulators and (semi)conductors

S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 1


Physical Properties of Si and SiO2

Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, p. 11.

at room temperature (300 K)


Silicon crystalline structure

S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 5.Linus Pauling, General Chemistry, Dover, 1988, p. 128.

Diamond lattice

structure

Covalent bonding

Orbitalsfilling

3p2

3s2

2p6

2s2

1s2

a = 0.513 nm for Silicon

Nucleus


From energy levels to bands

E1

E2

E3

En

E0 (reference)

2220

40

2

n nh8qmZ

E�

��

Z: atomic number

m0: free electron mass

q: electron charge

�0: permittivity free space

h: Planck’s constant

n: positive integers(level number)

… putting more atoms together

(and remembering Pauli’s exclusion

principle)

x

Allowed energy band

Forbidden energy gap

Allowed energy levels


Energy-band diagrams

Conduction Band

Valence Band

Conduction Band

Energy Gap

Valence Band

Conduction Band

Energy Gap

Valence Band

Conduction Band

Insulator Semiconductor Conductor Conductor

Empty allowed energy band

Full allowed energy band


Formation of Energy Bands

S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 10.

Curves obtained with quantum mechanical

calculations made for diamond lattice

crystals.

Increasing T increases the lattice

spacing and therefore gives a lower energy gap


Fermi levels

S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, pp. 17, 18.

The Fermi level is the energy at which the probability of occupation of that level by an electron is exactly 0.5

F(Ef) = 0.5

n = p = ni

ni = intrinsic carrier density

ni = 1.45*1010 cm-3


Intrinsic and doped silicon

Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, pp. 10, 13, 14.E. S. Yang, Microelectronic Devices, McGraw-Hill International Editions, 1988, pp. 9, 15.

Fictitious particle


Donors and acceptors


Intrinsic Semiconductor: small amount of impurities compared to the thermally generated electrons and holes

Donor level: the allowed energy level provided by a donor is neutral when occupied by an electron and positively charged when empty

Acceptor level: the allowed energy level provided by an acceptor is neutral when empty (= occupied by a hole) and negatively chargedwhen occupied by an electron (= empty)


Carrier density vs Temperature

S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 27

N-type semiconductor

Electrons are the majority carriers

Intrinsic carrier density (= hole density)

kT

E

vc2i

g

eNNn�

�


Fermi levels vs Doping and T



Mobility vs T and ND

S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 33.

ND: doping concentration

EEmq

v ne

md ��

��

vd = drift velocity

�m = mean free time between collisions

me = conductivity effective mass

E = electric field


Mobility vs doping


IL

111�

��

��

� = total mobility

�L = mobility due to lattice scattering

�I = mobility due to impurity scattering


Carrier velocity vs Electric Field

R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd Edition, John Wiley and Sons, 1986, p. 36.


Resistivity vs doping


)pn(q1

pn ��

ρ = resistivity

n, p = carrier concentration

�n, �p = carrier mobility


Outline




The MOS transistor

Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999, p. 35

x

y

z

GATE

SOURCE

DRAIN

SUBSTRATEGSmDS vgi �

Transconductance


CMOS technology

n+ n+p+ p+ p+ n+

n-well

SG

D SG

Dsub well

p-substrate

NMOS PMOS

PolysiliconOxideElectronsHoles

NMOS layout

n+ sourceG

n+ drain


Linear and Saturation regions

n+ n+

SG

D

n+ n+

SG

D

LINEAR REGION (Low VDS):Electrons (in light blue) are attracted to the SiO2 – Si Interface. A conductive channel is created between source and drain. We have a Voltage Controlled Resistor (VCR).

SATURATION REGION (High VDS):When the drain voltage is high enough the electrons near the drain are insufficiently attracted by the gate, and the channel is pinched off. We have a Voltage Controlled Current Source (VCCS).


Drain current vs Drain voltage

0.0E+00

5.0E-06

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

0.0 0.5 1.0 1.5 2.0 2.5

VDS [ V ]

I DS [

A ]

Saturation region (VCCS)

Linear region (VCR)

Output conductance

@ three different VGS

Locus of IDS_SAT vs VDS_SAT


Equations: strong inversion

LW

Cox ��x.1g

ggn

m

mbm ��

�

DSDS

TGSDS V)2

nVVV(I ��

LINEAR REGION:

SAT_DSTGS

DS Vn

VVV �

��

2TGSDS )VV(

n2I �

�

DSTGSGS

DSm I

n2)VV(

nVI

g

��

��

�

SATURATION REGION:

SAT_DSTGS

DS Vn

VVV �

��

Transconductance:

ox

SiOox t

C 2�

�BS

DSmb V

Ig

��

�


0.E+00

2.E-04

4.E-04

6.E-04

8.E-04

1.E-03

1.E-03

1.E-03

2.E-03

-0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4

VGS [ V ]

I DS [

A ]

Drain current vs Gate voltage

Su

bth

resh

old

re

gio

n

Lin

ear

reg

ion

(g

reen

) an

d

satu

rati

on

reg

ion

(re

d)

High field (vertical and longitudinal)

effects


Log(IDS) vs VGS

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4

VGS [ V ]

I DS [

A ]

LEAKAGE CURRENT

THRESHOLD VOLTAGE

STRONG INVERSION

WEAK INVERSION

SUBTHRESHOLD SLOPE


Band diagrams of a MOS structure

Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999, p. 576

Diagrams assuming VFB = 0

(a) Flat-band condition

(b) Accumulation

(c) Onset of weak inversion

(d) Onset of moderate inversion

(e) Onset of strong inversion

Energy

Space

kTEE

i

iF

enn�

�

kTEE

i

Fi

enp�

�


Equations: weak inversion

)e1(eLW

II t

DS

t

GS

nV

nV

0DDS�

��

t

DS

GS

DSm n

IVI

g�

��

�

K300mV25q

kTt @ ��

tDS n4V ��

Almost like a bipolar transistor!

t

GS

nV

0DDS eLW

II ��

If then the drain current does not depend on VDS any longer (saturation)


Transcond. vs Gate voltage

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

8.E-05

9.E-05

1.E-04

-0.35 0.05 0.45 0.85 1.25 1.65 2.05 2.45

VGS [ V ]

gm

[ S

]Measurement

made in the linear region


Output conductance

0.0E+00

5.0E-06

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

0.0 0.5 1.0 1.5 2.0 2.5

VDS [ V ]

I DS [

A ]

�V�I

VDSVD VD’

IDS

ID

ID’

L-LL

VI

VI

G Dout �

�

��

��

�n+ n+

SG

D

�LL

Dashed lines:ideal behavior


Equations: output conductance

)V1()VV(n2

I DS2

TGSDS ��

�

SAT_DSDS

DSdsout I

VI

gg ��

��SAT_DS

E

SAT_DSds0 I

LVI

1g1

r

��

��

2SAT_DS

2TGSSAT_DS nV

2)VV(

n2I

��

�

nVV

V TGSSAT_DS

�� since

)N,V(fLLL

LV1

DopingDSDS

where ��

��


Equations: addendum

Sm

m’m Rg1

gg

��

� SiSisbT VV ��Bulk effect

)VV(nL2

1Cg

21

f TGS2gs

mmax �

��

��

� in s.i.Maximum frequency

Source parasitic resistance

Vertical electric field effect )VV(1 TGS

0

��

��

K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, Chapter 1

ox

aSi

C

Nq2 ��


Equations: velocity saturation

Lv

21

Cg

21

f sat

gs

m.S.Vmax_ �

��

�

scm

10v)VV(vWCI 7satTGSsatox.S.V_DS with ��

satox.S.V_m vWCg �

For low values of the longitudinal electric field, the velocity of the carriers increases proportionally to the electric field (and theproportionality constant is the mobility). For high values of the electric field (3 V/�m for electrons and 10 V/�m for holes) the velocity of the carriers saturates.


gm / ID vs log(ID / W)

0

5

10

15

20

25

30

1E-11 1E-09 1E-07 1E-05 1E-03

ID / W

gm

/ I D

W.I.

M.I.

S.I. &

V.S.

Weak Inversion (W.I.)

t

DSm n

Ig

��

tD

m

n1

Ig

��

Strong Inversion (S.I.)

DSm In

2g

�DSD

m

I1

n2

Ig

�

Velocity Saturation (V.S.)

satoxm vWCg �DS

satox

DS

m

IvWC

Ig

�


0.1

1

10

100

1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03

ID / W

gm

/ I D

Log(gm / ID) vs log(ID / W)

Slope = - 0.5Strong inversion

Slope = - 1Velocity saturation


Small-signal equivalent circuit

gsmvg 0r

G

S

D

GSmDS vgi �

2TGSQDSQ )VV(

n2I �

�

K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, p. 24.

This equation fixes the bias point

This equation defines the small signal behavior


Small-signal equivalent circuit

gsmvg bsmbvg 0r

sbC

gsC

dbCgbC

gdC

G

S

D

B


The real thing!

SOI technology from IBMhttp://www-3.ibm.com/chips/gallery/


The real thing!

Metallization exampleshttp://www-3.ibm.com/chips/gallery/


Why is CMOS so widespread?

• The IC market is driven by digital circuits (memories, microprocessors, …)

• Bipolar logic and NMOS - only logic had a too high power consumption per gate

• Progress in the manufacturing technology made CMOS technologies a reality

• Modern CMOS technologies offer excellent performance (especially for digital): high speed, low power consumption, VLSI, low cost, high yield

CMOS technologies occupies an increasing portion of the IC market

… and this is why we will only talk about CMOS.


The next five lectures

• Lecture 2: Noise and Matching in CMOS (Analog) Circuits• Lecture 3: Scaling Impact on Analog Circuit Performance• Lecture 4: (Low Voltage) Analog Design (1)• Lecture 5: (Low Voltage) Analog Design (2)• Lecture 6: Introduction to Switched Capacitor Circuits

introduction to analog design in submicron cmos...

Documents