Lab Seminar

A Multi-channel architecture for high-performance NAND flash-based storage system

Jeong-Uk Kang et.al. (KAIST)Journal of System Architecture 2007,Vol 53

Speaker : Jaewoo Lee

Flash Memory : Basic

• NOR : code storage• Random access capability

• High read performance

• Low write and erase performance

• Expensive

• Execute-in-place (XIP)

• NAND : data storage• Higher write and erase performance

• Low cost

Flash Memory : New Technology

• Multi-Level Cell (MLC) technology• Multiply the capacity of flash memory

• Decrease the operation speed high performance is challenging area

• Large Block ( compared to small block )• # of page in each block : 32 64

• Each page consist of Main area : 512 byte 2048 byte Spare area : 16 byte 64 byte

• Sequential programming restriction is added

• Multi-Channel Architecture• Each channel can operate independently

Objective

• High Performance NAND flash-based storage system• In Multi-Channel Hardware Architecture• three optimization : exploit I/O Parallelism

Striping Interleaving Pipelining

• Result Striping, Interleaving, Pipelining improve

performance up to 164%, 62%, 197% Combining all the optimization results 3.6

times improvement

Multi-channel Architecture

• Prototype System based on Multi-Channel Architecture

Multi-channel Architecture

• Channel Manager

Timing of Read and Write Op

• Read Op

• Write Op

Software Architecture

• Optimization which exploit I/O parallelism • a: striping, b: Interleaving, c: pipelining

Software Architecture : Striping

Software Architecture : Interleaving

Software Architecture : Pipelining

Back

Software Architecture : All together

Result : Impact of Optimization

• Striping

• Interleaving

Result : Impact of Optimization

• Pipeling

Result : All Together

• Throughput

• Average Service TimeS2:I2

Request Size4K

Result : Overall Performance

• Throughput delivered to User-level Applications• Read : 80% of raw , due to programmed I/O

• Write : Sync – Async -

Link

Conclusion

• This paper present• High-performance NAND flash-based storage• Exploit I/O parallelism from multiple channel• Applied three optimization

Striping Pipelining Interleaving

• We find out• Size of sub-request >= page size of NAND for striping• Request size is not related to the throughput of read

and write op for interleaving

• Result • 3.6 times improvement to conventional single

channel architecture