layout design - carnegie mellon universityece322/lectures/lecture5/lecture5.03.pdflayout design...
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![Page 1: Layout Design - Carnegie Mellon Universityece322/LECTURES/Lecture5/Lecture5.03.pdfLayout Design Lecture 4 18-322 Fall 2003 Textbook: Design Methodology Insert A [Portions adapted from](https://reader035.vdocuments.net/reader035/viewer/2022071503/6123296423e4c863914543f1/html5/thumbnails/1.jpg)
Layout Design
Lecture 418-322 Fall 2003
Textbook: Design Methodology Insert A
[Portions adapted from J. P. Uyemura “Introduction to VLSI Circuits and Systems”, Wiley 2001.]
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Roadmap
Today: Basic CMOS Layout: “design in the small”Thursday: Layout Verification & “design in the large”Next week:
Transistor sizingWires
Homework 1: Due ThursdayHomework 2: Out ThursdayLab 2: This week
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Today’s Overview
Physical structure of ICsDesign rulesBasic gates layout
Stick diagrams Basic rulesExamples
Cadence (Virtuoso)
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Review: MOSFETs
Gate (G)No connection
G = 0Open switchSource Drain
Sourcelayer
Drainlayer
Gate layerConduction layer
G = 1Closed switch
G is responsible for the absence or presence of the conduction region between the drain and the source regions
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Review: Controlling Current Flow (nFET)
0V
p
n+ n+
No electronsL
insulatordrain diffsource diff
VG
n+ n+ W
L
Top viewSide view
+
p
n+ n+
electrons n+ n+
electron channel
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Review: Manufacturing
2D top-down view
How design engineers seethe chip.
3D “cross-section” view
How process engineers seethe chip.
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Design Rules
Interface between designer and process engineerClean separation between the process during wafer fabrication and the designeffort ⌧ Permissible geometries -> DESIGN RULES
• Width rule, space rule, overlap rule, etc.
Ways to do design rules“Scalable Design Rules”Absolute measures
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Scalable Design Rules
CMOS scalesImplement something now, shrink it laterExpress all design rules in terms of a unit dimensionChange the actual dimension of the unit, and the whole design shrinksMead and Conway
Unit dimension: Minimum line width (2λ)In 1978, λ = 1.5 µm (a.k.a. 3 micron technology)In 2003, λ = 0.065 µm (a.k.a. 0.13 micron technology)
Important Intellectual idea, not used in industry (but we will)
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Transistor Layout
1
2
5
3
Tran
sist
or
Well boundary
L
W
The choice of geometry determines transistor parameters!
All distances are expressed in λ
poly
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Transistor Layout
4λ
L
W2λ
2λ
5λ
λ
λ
Source Drain2λSource to
gate shortcirc
Non-catastrophicmisalignment
2λ
AS = AD = 5λWλ = 0.5µm -> A = 12.5µm2
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Absolute Design Rules
It is hard to scale every aspect of design linearlyThe elegance of scalable CMOS isn’t worth the costSpecify all dimensions in real units (µm or nm)
Currently (0.13 micron), there are THOUSANDS of design rules
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CMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
RedBlue
MagentaBlack
BlackBlack
Select (p+,n+) Green
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Inverters
Vin Vout
VDD
GND
Layout of a NOT gate
Vin Vout
GND
VDD
Vin Vout
VDD
GND
Alternate layout of a NOT gate
Transistor sizing determines inverter fundamental properties!
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Series/Parallel Connections
A B
n+ n+ n+
A B
n+ n+ n+
A B
n+ n+ n+
p
Devices can share patterned regions; this may reduce the layout area or complexity!
A BX
Y
A B
XX X
X
Y X
poly Redn+/p+ Greenmetal Bluecontact Black
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NAND2
V DD
GND
AB NOT(AB)
GND
A
B
V DD
NOT(AB)
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Question: How About AND2?
V DD
GND
AB NOT(AB) A and B
VDD
GND
GND
A
B
V DD
NOT(AB)
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NOR2
B
A
V DD
GND
NOT(A+B)
The output here is connected to one p-trans drain and two n-trans drains.
V DD
GND
A
BNOT(A+B)
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NOR2 (alternate layout)
B
A
V DD
GND
NOT(A+B)
The output here is connected to one p-trans drain and one n-trans drain.
V DD
GND
A
BNOT(A+B)
This is better! Less drain area connected to the output . This results in a faster gate.
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Complex Logic Gates: OAI Gates
ABCD
FA
B C D
1
2
A
B C D
1
2
#1 #2
F= NOT(A(B+C+D))
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OAI Gates: Sharing S/D (option 1)
A B C D
A
B C D
1
2
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OAI Gates: Sharing S/D
A B C D
VD D
GND
A
B C D
1
2
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OAI Gates: Sharing S/D
A B C D
F
VD D
GND
A
B C D
1
2
The output here has four output drain capacitances.
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Capacitance: Friend or Foe???
Foe: Slows down the output:
Friend: Stabilizes the Power Supply
Big CapacitanceMore charge toto change voltageSLOWER!
Big CapacitanceMore charge toto change voltageMore stable supplyvoltage!
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OAI Gates: Sharing S/D (option 2)
A B C D
A
B C D
1
2
#2
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OAI Gates: Sharing S/D
A B C D
F
VDD
GND
A
B C D
1
2
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OAI Gates: Sharing S/D
A B C D
F
V DD
GND
Wrong
A B C D
F
V DD
GND
Right
The output here has two output drain capacitances.
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Gate Design Procedure
Run VDD and GND in metal at top and bottomRun vertical poly for each gate inputOrder gates to allow maximum source-drain abuttingPlace max number of n-diffusions close to GNDPlace max number of p-diffusions close to VDDMake remaining connections with metal
Minimize metal usage
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Question: How About TGs?
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Overview
Physical structure of ICsDesign rulesBasic gates layout
Stick diagrams Basic rulesExamples
Cadence (Virtuoso)
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Stick Diagrams
•Introduced by Mead & Conway in the ‘80s
•Every line of a conduction material layer is represented by a line of a distinct color
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nFET and pFET Representations
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Basic Rules (1)
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Basic Rules (2)
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Basic Rules (3)
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Logic Gates Design
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Examples
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Complex Functions
OUT = ABC + D
OUT
VDD
C
CB
D
A
B
A
D
X X XX
X
X
X X
ABC D
VDD
GND
OUT
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Summary
Discussed Design rulesBasic gates layout Stick diagrams
Need more practice on Stick diagramsLayout (mostly in the lab)
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Preview: The 18-322 Flow
Boolean function Transistor Schematic
Schematic Simulation
ComponentDesign
Extracted Simulation
Layout (w/ DRC)1st part
of the Thursday’s
LectureLVS Check
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Preview: Modern ASIC Design
Designer Productivity is a big problemIn 1978, people could draw transistors, now there are 100s of millions per chip…New abstractions necessary:
Masks LayoutDesign
Design R
ules
Cell Libraries
Std CellDesign
18-322