lecture - 國立臺灣大學yangc/lecture1.pdf · course outline qfundamentals of computer...

Lecture 1

Course IntroductionComputer Architecture OverviewTechnology Trend in ComputerArchitecture Quantitative Principle of Computer Design

Course Introduction

Instructor : 楊佳玲

[email protected]: CSIE 411Office Hours: Tuesday and Thursday 10:30-11:30 orby appointmentCourse Web Page– Lectures, homeworks, project topics

TA: to be announcedTextbook: Computer Architecture A Quantitative Approach2nd Edition, John L. Hennessy and David A. Patterson

Computer Architecture Is

the attributes of a [computing] system as seenby the programmer, i.e., the conceptualstructure and functional behavior, as distinctfrom the organization of the data flows andcontrols the logic design, and the physicalimplementation.

Amdahl, Blaaw, and Brooks, 1964SOFTWARESOFTWARE

Course Focus

Why?– Understanding the design techniques, machine

structures, technology factors

Analysis and Evaluation– evaluating the performance of alternative choices in

system design using simulators

Interesting research topics

Grading

30% Homeworks– every two weeks

30% Project– team work

30% Exams– midterm and final (close book)

10% class participation

Computer Architecture Topics

Instruction Set Architecture

Pipelining, Hazard Resolution,Superscalar, Reordering, Prediction, Speculation

Addressing,Protection,Exception Handling

L1 Cache

L2 Cache

DRAM

Disks, WORM, Tape

Coherence,Bandwidth,Latency

Emerging TechnologiesInterleavingBus protocols

RAID

VLSI

Input/Output and Storage

MemoryHierarchy

Pipelining and Instruction Level Parallelism


M

Interconnection NetworkS

PMPMPMP ??

Topologies,Routng,Bandwith,Latency,Reliability

Network Interfaces

Shared Memory,Message Passing,Data Parallel

Processor-Memory-Switch

•Multiprocessors•Networks and Interconnections


Portable Systems

Computers vs. Intelligent CommunicatorsHigh Performance vs. Low PowerLCD TechnologiesReal-time Input/Output (e.g., Pen Input)Portable Storage Devices (PCMCIA)

Course OutlineFundamentals of Computer Architecture (ch1)– Cost and performance measurement

Instruction Set Design and Basic Pipelining (ch2&3)– DLX architecture

Exploiting Instruction Level Parallelism(ch4)– Multiple issue processor and compiler support

Memory Hierarchy Design (ch5)– Cache and virtual memory

I/O system design (ch6)Multiprocessors (ch8)– Parallel architecture types and memory consistence models

Advanced topics: power management, SMT, CMP

Computer Engineering Methodology

TechnologyTrends


Evaluate ExistingEvaluate ExistingSystems for Systems for BottlenecksBottlenecks

TechnologyTrends

Benchmarks



Simulate NewSimulate NewDesigns andDesigns and

OrganizationsOrganizations

TechnologyTrends

Benchmarks

Workloads



Simulate NewSimulate NewDesigns andDesigns and

OrganizationsOrganizations

Implement NextImplement NextGeneration SystemGeneration System

TechnologyTrends

Benchmarks

Workloads

ImplementationComplexity

Application Area– Special Purpose (e.g., DSP) / General Purpose– Scientific (FP intensive) / Commercial (Integer)

Level of Software Compatibility– Object Code/Binary Compatible (cost HW vs. SW; IBM

S/360)– Programming Language; Why not?

Context for Designing NewArchitectures

Operating System Requirements for GeneralPurpose Applications

– Size of Address Space– Memory Management/Protection– Context Switch– Interrupts and Traps

Standards: Innovation vs. Competition– IEEE 754 Floating Point– I/O Bus– Networks– Operating Systems / Programming Languages ...

Context for Designing NewArchitectures

Technology Trends(Summary)

Capacity SpeedLogic 2x in 3 years 2x in 3 yearsDRAM 4x in 3 years 1.4x in 10 yearsDisk 2x in 3 years 1.4x in 10 years

How does technology trends affect architectural design?• Memory subsystem is the performance bottleneck because of the performance gap between logic and Dram speed • The increase in logic capacity allows computer designers to place a larger cache on chip

Processor Performance

S un-4/260MIP S M/120

MIP S M2000 IBMRS 6000/540

HP9000/750

DEC AXP3000

0

50

100

150

200

250

300

1987 1988 1989 1990 1991 1992 1993 1994 1995

Perfor

mance

IBM P o we r 2 /590

1.54X/yr

1.35X/yr

DEC 21064a

S un UltraS parc

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Year

1000

10000

100000

1000000

10000000

100000000

1970 1975 1980 1985 1990 1995 2000

i80386

i4004

i8080

Pentium

i80486

i80286

i8086

Technology Trends: MicroprocessorCapacity

SparcUltra: 5.2 millionPentium Pro: 5.5Power PC: 6.9Alpha 21164: 9.3Alpha 21264: 15Pentium III: 28Pentium 4: 42Alpha21364: 100Alpha21464: 250

Memory Capacity(Single Chip DRAM)

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size

Year

1000

10000

100000

1000000

10000000

100000000

1000000000

1970 1975 1980 1985 1990 1995 2000

year size cyc time1980 64 Kb 250 ns1983 256 Kb 220 ns1986 1 Mb 190 ns1989 4 Mb 165 ns1992 16 Mb 145 ns1995 64 Mb1998 128 Mb

Measurement and Evaluation

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Design

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Analysis

Architecture is an iterative process:• Searching the space of possible designs• At all levels of computer systems

Creativity

Good IdeasGood IdeasMediocre Ideas

Bad Ideas

Cost /PerformanceAnalysis

Measurement Tools

Benchmarks, Traces, MixesCost, delay, area, power estimationSimulation (many levels)

– ISA, RT, Gate, Circuit

Queuing TheoryRules of ThumbFundamental Laws

The Bottom Line:Performance (and Cost)

• Time to run the task (ExTime)– Execution time, response time, latency

• Tasks per day, hour, week, sec, ns ?(Performance)– Throughput, bandwidth

Plane

Boeing 747

BAD/SudConcodre

Speed

610 mph

1350 mph

DC to Paris

6.5 hours

3 hours

Passengers

470

132

Throughput(pmph)

286,700

178,200

Performance Terminology

"X is n times faster than Y" means

ExTime(Y) Performance(X)--------- = ---------------ExTime(X) Performance(Y)

" X is n% faster than Y " means:

ExTime(Y) Performance(X) n --------- = -------------- = 1 + ----- ExTime(X) Performance(Y) 100

n = 100(Performance(X) - Performance(Y)) Performance(Y)

Example

1510 = 1.5

1.0 = Performance (X)Performance (Y)

ExTime(Y)ExTime(X) =

n = 100 (1.5 - 1.0) 1.0

n = 50%

Example: Y takes 15 seconds to complete a task, X takes 10 seconds. What % faster is X?

Amdahl's LawSpeedup due to enhancement E: ExTime w/o E Performance w/ ESpeedup(E) = ------------- = ------------------- ExTime w/ E Performance w/o E

Suppose that enhancement E accelerates a fraction F ofthe task by a factor S, and the remainder of the task isunaffected, then:

ExTime(E) =Speedup(E) =

Amdahl’s Law

ExTimenew = ExTimeold x (1 - Fractionenhanced) + Fractionenhanced

Speedupoverall =ExTimeold

ExTimenew

Speedupenhanced

=1

(1 - Fractionenhanced) + Fractionenhanced

Speedupenhanced

Amdahl’s Law

Floating point instructions improved to run 2X;but only 10% of actual instructions are FP

Speedupoverall =

ExTimenew =

Amdahl’s Law

Floating point instructions improved to run 2X;but only 10% of actual instructions are FP

Speedupoverall = 10.95

= 1.053

ExTimenew = ExTimeold x (0.9 + .1/2) = 0.95 x ExTimeold

Corollary: Make The Common Case FastAll instructions require an instruction fetch,only a fraction require a data fetch/store.

– Optimize instruction access over data access

Programs exhibit localitySpatial Locality Temporal Locality

Access to small memories is faster– Provide a storage hierarchy such that the most

frequent accesses are to the smallest (closest)memories.

Reg's Cache Memory Disk / Tape

Metrics of Performance

Compiler

Programming Language

Application

DatapathControl

Transistors Wires Pins

ISA

Function Units

(millions) of Instructions per second: MIPS(millions) of (FP) operations per second: MFLOP/s

Cycles per second (clock rate)

Megabytes per second

Answers per monthOperations per second

Aspects of CPU PerformanceCPU time = Seconds = Instructions x Cycles x Seconds

Program Program Instruction Cycle

CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle

Instr. Cnt CPI Clock RateProgram

Compiler

Instr. Set

Organization

Technology

Aspects of CPU PerformanceCPU time = Seconds = Instructions x Cycles x Seconds

Program Program Instruction Cycle

CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle

Inst Count CPI Clock RateProgram X

Compiler X

Inst. Set. X X

Organization X X

Technology X

Marketing MetricsMIPS = Instruction Count / Time * 10^6 = Clock Rate / CPI * 10^6

• Machines with different instruction sets ?

• Programs with different instruction mixes ?

– Dynamic frequency of instructions

• Uncorrelated with performance

MFLOP/s = FP Operations / Time * 10^6

• Machine dependent

• Often not where time is spent

Cycles Per Instruction

CPU time = CycleTime * ∑ CPI * Ii = 1

n

i i

CPI = ∑ CPI * F where F = I i = 1

n

i i i i

Instruction Count

instruction Frequency

Invest Resources where time is Spent!

CPI = Instruction Count / (CPU Time * Clock Rate)= Instruction Count / Cycles

average Cycles per Instruction

Example: Calculating CPI

Typical Mix

Base Machine (Reg / Reg)Op Freq CPI(i) CPI(i)*Freq (% Time)ALU 50% 1 .5 (33%)Load 20% 2 .4 (27%)Store 10% 2 .2 (13%)Branch 20% 2 .4 (27%) 1.5

Base Machine (Reg / Reg)Op Freq CyclesALU 50% 1Load 20% 2Store 10% 2Branch 20% 2

Typical Mix

ExampleAdd register / memory operations:

– One source operand in memory– One source operand in register– Cycle count of 2

Branch cycle count to increase to 3.

What fraction of the loads must be eliminated for thisto pay off?

Example SolutionExec Time = Instr Cnt x CPI x Clock

Op Freq Cycles Freq CyclesALU .50 1 .5 .5 -X 1 .5 -XLoad .20 2 .4 .2 -X 2 .4 -2XStore .10 2 .2 .1 2 .2Branch .20 2 .3 .2 3 .6Reg/Mem X 2 2X

1.00 1.5 1 -X (1.7 -X)/(1 -X)

Instr CntOld x CPIOld x ClockOld = Instr CntNew x CPINew x ClockNew

1.00 x 1.5 = (1 -X) x (1.7 -X)/(1 -X) 1.5 = 1.7 -X 0.2 = X

ALL loads must be eliminated for this to be a win!

Programs to Evaluate ProcessorPerformance

(Toy) Benchmarks– 10-100 line program– e.g.: sieve, puzzle, quicksort

Synthetic Benchmarks– Attempt to match average frequencies of real workloads– e.g., Whetstone, dhrystone

Kernels– Time critical excerpts– e.g., Livermore loops

Real programs– e.g., gcc, spice

Benchmarking Games

Differing configurations used to run the sameworkload on two systemsCompiler wired to optimize the workloadTest specification written to be biased towards onemachineWorkload arbitrarily pickedVery small benchmarks usedBenchmarks manually translated to optimizeperformance

SPEC: System Performance EvaluationCooperative

First Round 1989– 10 programs yielding a single number

Second Round 1992SpecInt92 (6 integer programs) and SpecFP92(14 floating point programs)

– Compiler Flags unlimited.

Third Round 1995– Single flag setting for all programs; new set of

programs benchmarks.

Spec2000: two options 1) specific flags 2)whatever youwant

Common Benchmarking Mistakes

Only average behavior represented in testworkloadCaching effects ignoredInaccuracies due to sampling ignoredIgnoring monitoring overheadNot validating measurementsNot ensuring same initial conditionsNot measuring transient (cold start) performance

How to Summarize PerformanceArithmetic mean (weighted arithmetic mean)tracks execution time: SUM(Ti)/n orSUM(Wi*Ti)Harmonic mean (weighted harmonic mean) ofrates (e.g., MFLOPS) tracks execution time:n/SUM(1/Ri) or n/SUM(Wi/Ri)Normalized execution time is handy for scalingperformanceBut do not take the arithmetic mean ofnormalized execution time, use the geometric

Performance EvaluationGiven sales is a function of performance relative tothe competition, big investment in improvingproduct as reported by performance summaryGood products created when have:

– Good benchmarks– Good ways to summarize performance

If benchmarks/summary inadequate, then choosebetween improving product for real programs vs.improving product to get more sales;Sales almost always wins!Ex. time is the measure of computer performance!What about cost?

lecture - 國立臺灣大學yangc/lecture1.pdf · course outline qfundamentals of computer...

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