lecture10 ee620 phase detectors

7/29/2019 Lecture10 Ee620 Phase Detectors

http://slidepdf.com/reader/full/lecture10-ee620-phase-detectors 1/23

Sam Palermo

Analog & Mixed-Signal Center

Texas A&M University

ECEN620: Network Theory

Broadband Circuit DesignFall 2012

Lecture 10: Phase Detector Circuits



Announcements & Agenda

• Exam 1 is on Wed. Oct 3•One double-sided 8.5x11 notes page allowed

•Bring your calculator

• Phase Detector Circuits

• Mixer PD

• XOR PD• J-K Flip-Flop PD

• Phase-Frequency Detector (PFD)

2



References

• RF Microelectronics, B. Razavi, PrenticeHall, 1998.

• Design of Integrated Circuits for Optical

Communications, B. Razavi, McGraw-Hill,2003.

• Monolithic Phase-Locked Loops and Clock

Recovery Circuits, B. Razavi, Wiley, 1996.• M. Perrott, High Speed Communication

Circuits and Systems Course , MIT Open

Courseware 3



Phase Detector

• Detects phase difference between feedback clock and reference clock

• The loop filter will filter the phase detector output,thus to characterize phase detector gain, extract

average output voltage• The K PD factor can change depending on the

specific phase detector circuit

4filterimpedanceawithusedwhen

pump-chargewith thecombinedwhenA/rador(averaged)radareunits

filterless-dimensionawithusedwhenV/radareunits

1-

PD

PD

K

K



Analog Multiplier Phase Detector

• If ω1=ω2 and filtering out high-frequency term

5

tA 11cosω

( )φ ω ∆+tA22

cos

( )[ ] ( )[ ]φ ω ω α

φ ω ω α

∆−−+∆++ tAA

tAA

2121

2121 cos

2cos

2

α is mixer gain

( ) φ α

∆= cos2

21AAty

• Near ∆φ lock region of π /2: ( )

∆−≈ φ

π α

2221AA

ty

221AA

K PDα

−=

[Razavi]



Mixer Circuits

7

Active MixersPassive Mixer



XOR Phase Detector

8

• Sensitive to clock duty cycle

[Razavi]



XOR Phase Detector

9

[Perrott]

Width is same for bothleading and laggingphase difference!



Cycle Slipping

• If there is a frequency difference between the inputreference and PLL feedback signals the phase detector can jump between regions of different gain

• PLL is no longer acting as a linear system

10

[Perrott]

(negative feedback operation)(positive feedback operation)



Cycle Slipping

• If frequency difference is too large the PLL may not lock

11

[Perrott]

Cycle Slipping



XOR PD Properties

• The nominal lock point with an XOR PD isalso a 90° static phase shift

• Unlike the analog mixer, K PD is

independent of input amplitude andconstant over a π phase range

• The XOR PD is sensitive to input dutycycle, and will lock with a phase error if theinput duty cycles are not 50%

12



J-K Flip-Flop Phase Detector

13

π

1=PDK

J K A

B



J-K Flip-Flop Details

14

J K A

B

D

Q

Q

D

Q

Q

J

K

Vout



J-K Flip-Flop Phase Detector Harmonic Locking

15

• Harmonic signals can display the same DC output,leading to potential locking to harmonics

A

B



J-K Flip-Flop PD Properties

• The nominal lock point with an J-K Flip-Flop PD is a 180° static phase shift

• The J-K Flip-Flop PD is not sensitive to

input duty cycle

• The J-K Flip-Flop displays a constant KPDover a 2π range

• There is the potential to lock to harmonicsof the reference clock

16



Phase Frequency Detector (PFD)

• Phase Frequency Detector allowsfor wide frequency locking range,potentially entire VCO tuning range

• 3-stage operation with UP andDOWN outputs

• Edge-triggered results in duty cycleinsensitivity

17



PFD Transfer Characteristic

• Constant slope and polarity asymmetry about zerophase allows for wide frequency range operation

18

UP=1 & DN=-1

[Perrott]



PFD Deadzone

• If phase error is small, then short output pulses are produced by PFD

• Cannot effectively propagate these pulses to switch charge pump

• Results in phase detector “dead zone” which causes low loop gain andincreased jitter

• Solution is to add delay in PFD reset path to force a minimum UP and

DOWN pulse length

19

[Fischette]



PFD Operation

20[Fischette]

Min. Pulse Width



PFD Properties

• The nominal lock point with a PFD is 0° • The PFD is not sensitive to input duty cycle

• The PFD outputs “UP” and “DN” are not

complementary and stay high until reset by theother, allowing for efficient frequency detection

• Near lock, the propagation of narrow pulses to

switch the charge pump can cause a phasedetector “dead zone”

• To prevent this, extra delay is generally inserted in thePFD reset path

21



Detailed Optimized PFD Schematic

• Because the flip-flop data input is always “1”, the logic can be optimized for higher

speed operation 22



Next Time

• Charge Pump Circuits

23

lecture10 ee620 phase detectors

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