legend and folklore: a bestiary of electronics · · 2015-07-28legend and folklore: a bestiary of...

Legend and Folklore:

A bestiary of electronics

Mark Rodwell, University of California, Santa Barbara

Short course, Device Research Conference, June , 05:

"Device Fundamentals You Were Never Taught: Interpreting Your Device Data"

"Must-Haves”

for a Useful Electron Device


Short course, Device Research Conference, June , 05:


Legend and Folklore:

A bestiary of electronics

With apologies to my co-authors.

C.-Y. Huang, J. Rode, S. Lee, V. Chobpattanna, P. Choudhary, A.C. Gossard, S. Stemmer ECE and Materials Departments, University of California, Santa Barbara P. Long, E. Wilson, M. Povolotskyi, G. Klimeck Network for Computational Nanotechnology, Purdue University

M. Urteaga, J. Hacker, M. Seo*, Z. Griffith, M. Fields, B. Brar

Teledyne Scientific and Imaging *Now Sunkyunkwan University.

Legend and Folklore: a bestiary of electronics

Let us now go hunting ...

Terra incognita: beyond the transistor

"Moore's law, transistor scaling, is over."

"We need new paradigms beyond charge as a state variable"

"We need more than Moore"

(Why do paradigms always shift?)

Moore or Dennard ?

Moore: predicted doubling of performance every ~18 months

Dennard: Proposed FET scaling laws (these now broken)

Robert and Gordon: What's your problem ?

FETs will stop working when we make them much smaller.

~ l/n

Oxide tunneling Source-drain tunneling

Lithography is getting hard. minimum focus spot size deep UV absorbtion

Power density is becoming excessive

CwireVDD2 interconnect energy

Static leakage > Ionexp(-qVDD /kT)

How electronics works today (same as in 1912)

tubes bipolar transistors field-effect transistors electrostatic barrier

Switching using charge-control

Communicating using... ...wires.

Time for new state variables ?

Gravitonics ?

Quarkonics ? gluonics?

Mechanics ? millions of heavy nuclei ...

Magnetics ? F ~ v1v2/c2→ weak!

Neutrinoonics ?

our tool-kit:

Our forebears chose wisely

Charge-control devices (switches) seem best confine & release charge using electrostatic barrier. electrons are light electrostatic force is strong over moderate* range.

Communicating using wires seems best signal using E&M waves guide them using wires E&M waves are strong & long-range. wires can be very narrow

http://semimd.com/chipworks/2014/10/27/intels-14nm-parts-are-finally-here/ca

0given size, source~ range* 2

Two older computing technologies

Nerve Cells

Cellular chemistry

Both are charge-control dense slow long development (~109 years) large installed base

cascaded, inter-regulating chemical reactions = computing machine

"CwireV2 dissipation constrains VLSI;

optical interconnects will fix this."

Optical interconnects are better ?

Aren't they both E&M waves ? So: what's the difference ? Both store energy eE2/2 +mH2/2 , a.k.a. CV2/2+LI2/2

Wires can be either capacitors or transmission-lines echoes or not T-lines: static dissipation Capacitors: CV2/2 dissipation per transition

0/ vZlCwire

Optical interconnects are better ?

If you shine a laser at a mirror, ...does it stop

drawing current ?

Optical interconnects have static dissipation

draws current when "1" transmitted

No static dissipation....

inC

cC

hvVC

hvVC

ddin

ddc

/ needed photons#

/ ed transmittphotons#

...looks tough.

DDVDDV

Other issues

optical losses

rough edge

bend radius 20nm contact pitch ?

Where to use optics: longer interconnect buses where switching activity is high

optics benefit: lower loss in longer interconnects

Can man live at such speeds ?

"Can man live at such speeds ?"

"Stephenson's Rocket drawing". Licensed under Public Domain via Wikimedia Commons - https://commons.wikimedia.org/wiki/File:Stephenson%27s_Rocket_drawing.jpg#/media/File:Stephenson%27s_Rocket_drawing.jpg

Stephenson's Rocket, 1829

"Circuit theory doesn’t work in the

sub-mm-wave THz IR etc."

Circuit theory is just Maxwell's equations

Circuits: Maxwell's equations in 0-D limit T-lines: Maxwell's equations in 1-D limit, etc.

Example: short T-line approximating an inductor

Any system of PDEs→ mesh finely into ODEs→ equivalent circuit

http://www5.ocn.ne.jp/

Circuit theory: alive & well at 1.0 THz

22

620 GHz, 20 dB gain HBT amplifier M Seo, Teledyne, IMS 2013

Not shown: 670 GHz HBT amplifier: J. Hacker, Teledyne: IMS 2013

Xiaobing Mei, et al, IEEE EDL, April 2015 doi: 10.1109/LED.2015.2407193

First Demonstration of Amplification at 1 THz Using 25-nm InP High Electron Mobility Transistor Process

No question that 1 THz interconnects are challenging, but they work...

"Charge control doesn’t work in the

sub-mm-wave THz IR etc."

...we must use quantum transitions"

FET parameter change

gate length decrease 2:1

current density (mA/mm), gm (mS/mm) increase 2:1

transport effective mass constant

channel 2DEG electron density increase 2:1

gate-channel capacitance density increase 2:1

dielectric equivalent thickness decrease 2:1

channel thickness decrease 2:1

channel state density increase 2:1

contact resistivities decrease 4:1

To double transistor bandwidth...

GW widthgate

GL

HBT parameter change

emitter & collector junction widths decrease 4:1

current density (mA/mm2) increase 4:1

current density (mA/mm) constant

collector depletion thickness decrease 2:1

base thickness decrease 1.4:1


eW

ELlength emitter

24

Electron device scaling & frequency limits

topR

bottomR

PIN diode

To double bandwidth: reduce thicknesses 2:1 Improve contacts 4:1 reduce width 4:1, keep constant length increase current density 4:1

vJx ee /// from 22

width

lengthlog

length

power

thicknessarea /

length

width

4area

area/

thickness/area

thickness

2

limit-charge-space max,

T

I

R

R

C

sheetcontactbottom

contacttop

How fast might it be ? 5nm diameter Schottky

2mA/ 0.3 diameter, 5nm nm, 5.3 :Assume mdeplT

aF 43.0/ :eCapacitanc DAC e

cm/s105.3)2/( : velocityAverage 7 Fermivv

fs 5.7

k17/2/

:) transport1D e(degenerat ResistanceJunction

2

CR

qIkTqhR

j

j

as 65

148: contacts),( Resistance Series

CR

RN

S

S

fs 6.9)2//( :meTransit ti Fermidepltransit vT

20-30 THz diode cutoff frequencies ?

How fast might it be ? 5nm diameter diode

Rob Maurer, Cheng-Ying Huang, Unpublished

...plasma resonance sets an upper frequency limit "

Plasma resonance ? No worries !

*2kinetic

1

nmqA

TL

T

AC

entdisplaceme

m

scatteringL

Rf

2

1

2

1

frequency scattering

kinetic

bulk

mnmqA

TR

*2bulk

1

e

2

1

2/1

frequency relaxation dielectric

bulkntdisplaceme

RC

fdielectric

ntdisplacemekinetic

2/1

frequencyplasma

CLf plasma

THz 800 THz 7 THz 74319 cm/105.3

InGaAs-

n

319 cm/107

InGaAs-

pTHz 80 THz 12 THz 13

Plasma resonance ? No worries !

*2kinetic

1

nmqA

TL

T

AC

entdisplaceme

THz72

1 frequency scattering

kinetic

bulk L

Rfscattering

mnmqA

TR

*2bulk

1

Above 7 THz, kinetic inductance increases N+/P+ layer impedances. But: contact resistances >> (N+/P+) resistances. A non-dominant resistance is increasing with frequency.

Not a serious concern until ~30THz.

...optics is fast, electronics is slow"

Transistors today

NGST Xiaobing Mei et al, IEEE EDL, April 2015

InP HEMTs

Teledyne: M. Urteaga et al: 2011 DRC, June

InP HBTs

These made fast by scaling FET Bipolar

lithographic dimensions: 25nm 130nm

epitaxial dimensions ~7nm 20nm base, 100nm collector

contact resistivities ~2-4-mm2 (both)

current densities ~1mA/mm 100 mA/mm2

~2 mA/mm 20-30 mA/mm2

Feasible to make these transistors (somewhat) faster.

Optics is fast ? Really ?

Optics has high *carrier* frequencies: 1.3 mm→ 230 THz

But, the per-channel *modulation* bandwidths are low.* 20~30 GHz modulation bandwidths for lasers 20~40 GHz for electro-absorbtion modulators a few ~100 GHz traveling-wave EO modulators; these are big

Terabit optical fiber systems aggregate many channels. WDM, polarization, etc Need lots of channels→ cost

Why are optical devices slow ?

*sure, a mode-locked-laser might have a 0.5fs pulse width, but how rapidly can you impose a signal (information) on this pulse?

Optical devices are hard to scale

Optical mode size prevents scaling: minimum I-layer thickness minimum lateral junction width maximum (P-/N-) doping (free-carrier losses)

+V (DC)

N+

N-

I

P-

P+

metal

metal

opticalmode

-V (DC)

AC outputfield

high er

But their carrier frequencies are high

Transistor R/C/ limits don't apply to laser (etc) carrier frequency carrier optical field guided by dielectric waveguide AC field kept away from resistive bulk and contact regions. AC signal not coupled through electrical contacts such dielectric mode confinement hard at low frequencies

+V (DC)

N+

N-

I

P-

P+

metal

metal

opticalmode

-V (DC)

AC outputfield

high er

"Tubes are ancient history"

Tubes are ancient ? They still beat transistors !

We developed a 180mW , 220 GHz HBT power amplifier...

... as part of a driver for a 20W, 220 GHz traveling-wave tube...

T Reed et al, CSICS 2014

We develop solid-state mm-wave sources, seeking to drive or replace existing high-power tubes.

... for DARPA's 220 GHz radar

Myths about III-Vs

Heard often at IEDM (even said by some III-V MOS folk)

(never at DRC) :

"III-V contacts much poorer than Si" "...can't be doped above 1018/cm3."

"...need to unpin the Fermi level under the contacts."












GW widthgate

GL








eW

ELlength emitter

40

III-V contacts much poorer than Si ???

For N-type, Si seems to be just a bit better Si at ~0.3 -mm2 , InAs at ~0.5 -mm2

For P-type, Si significantly better P-SiGe:~0.15 -mm2 (ZHANG et al, EDL, June 2013)

P-InGaAs at ~0.5 -mm2

III-V's can't be N-doped above ~1018/cm3 ???

Very strange, very persistent myth.

Easy fix: read any of 100's of papers in the literature N-type InGaAs to ~8*1019/cm3, InAs to 1020/cm3, P-type InGaAs to ~2*1020/cm3

Myth seems to arise from low conduction-band state density InGaAs effective state density Ns~4*1017/cm3, Surely it is not possible to dope higher than that ? ;-)

Need to unpin the contact Fermi level ???

N-InGaAs seems to have a ~0.2 eV Schottky barrier ~0.6nm depletion depth ~one lattice constant

N-InAs, or course, has a *negative* ~0.2 eV Schottky barrier with no barrier, is contact resistivity zero ??? No→ Landauer !

tcoefficienon transmissi ion,concentratcarrier

1

||||

1

3

83/22

3/2

2

Tn

nTqc

Wavefunction reflects due to mass, energy change → |T|<1 (over)simplified theory, heavily-doped InAs : |T|2 ~0.3, Experimental: |T|2 ~0.1

TLM Resistance, at zero spacing, is the contacts ?

That's how we all learned to characterize contacts.

Ti/Pd/Au

5 nm Intrinsic InGaAs (Capping layer)

60 nm N+ InGaAs

(regrown contact layer)

Gap

Channel

0 5 10 15 20 250

100

200

300

400

500

600

700

800

Re

sis

tan

ce

(O

hm

-mm

)

Gap (mm)

Y = 24 + 25*X

c = 5.3 -mm

2

RN+SD

= 85 -mm

widthTLM

knesslayer thic-epi

ion,concentratcarrier

11

3

83/2

3/2

2Landauer

W

H

n

nHWqR

But the zero-gap resistance also contains a Landauer term:

Correction can be significant Contacts are better than we think UCSB's published N-InAs contact data is pessimistic

Lee et al, 2015 VLSI symposium

"III-V dielectrics are still very poor"

Are III-V dielectrics still very poor ?

Maybe not perfect. But perhaps better than one might think. Here are Susanne Stemmer's dielectrics in our FETs.

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710

-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

|Ga

te L

ea

ka

ge

| (A

/cm

2)

Cu

rre

nt

De

ns

ity

(m

A/m

m)

Gate Bias (V)

10-5

10-4

10-3

10-2

10-1

100

101

SSmin

~ 61 mV/dec.

(at VDS

= 0.1 V)

SSmin

~ 63 mV/dec.

(at VDS

= 0.5 V)

Dot : Reverse Sweep

Solid: Forward Sweep

Lg = 1 mm

61 mV/dec Subthreshold swing at VDS=0.1 V. Negligible hysteresis

Lee

et

al, 2

01

5 V

LSI s

ymp

osi

um

BJT Myths

"...bipolar transistors are current controlled, FETs are voltage-controlled"

Given some finite, nonzero input impedance, there's a 1-1 relationship between voltage & current...

"InP is poor for power devices: vsat is only ~1.5*107 cm/s"

Is the velocity low in InP ??

This is the bulk velocity-field curve http://www.ioffe.ru/SVA/NSM/Semicond/InP/Figs/837.gif

But, in InP collector, no G-L scattering until band energies allow it.

Typical velocities are ~3E7 cm/s.

"velocity overshoot"

Drops at higher voltages...

Rbb is not "base spreading resistance"

It's mostly from the contacts

..and a bit from the gap

..and quite a lot from the metal !

Are base-emitter heterojunctions important ?

InGaAs emitter & base no EB heterojunction large electron degeneracy don't need heterojunction !

History Woodall pointed it out. Ritter did the experiment. Verified !

Why do we keep the InP ? InP/InGaAs selective etch precision placement of base contact.

Are DHBTs slow when saturated ?

DHBTs don't store holes in the subcollector: base-collector junction blocks hole injection into collector much less saturation charge.

Classic bipolar transistor saturation: moderate minority carrier storage in base large minority carrier storage in subcollector subcollector stored charge dominates

Circuit implications: base-collector diodes are Schottky like Daneshgar 2014: use in fast sample-hold gates CMOS-like saturating-HBT logic Taur et al 2015: proposed as CMOS logic replacement

10-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.1 0 0.1 0.2

J(m

A/m

m2)

Vbe

-

Fermi-Dirac

Highly degenerate

(Vbe

->>kT/q

Boltzmann

(-Vbe

)>>kT/q

HBTs have exponential I-V characteristics ????

Boltzmann

2

32

3

)(8

*

beV

mq

)/exp( kTqVbe

Fermi-Dirac

Highly Degenerate

130nm InP HBT

drops gm→ hurts bandwidth

FET Myths

"Long-channel FETs are limited by mobility...

...short-channel FETs are limited by saturation drift velocity".

Mobility/saturation velocity model ???

ID

VDS

increasingVGS

gthgsgoxD LVVWcI 2/)(

current limitedmobility

2

,

mm

)(

current limitedvelocity

, thgssatgoxvD VVvWcI

1

Expression dGeneralize

,

2

,

mD

D

vD

D

I

I

I

I

Id

VgsVth

mobility-limited

velocity-limited

: voltageknee thenlarger tha voltagesdrainFor

!correct not is This

notes class ateundergraduMy

Short-channel: Ballistic top-of-barrier model

Natori, Lundstrom, Antoniadis

If zero scattering between source and barrier: velocity set by mv2= Eelectron-Ec,barrier. current= #states above barrier times velocity of each scattering in drain region: reduces f , doesn’t reduce current

Scattering near source: drops Ef near barrier reduces current

Are FET f's set by transit times ?

Everyone knows this.

But, the significance is not always noted.

End capacitances about 0.3 fF/mm total in HEMTs about 1.0 fF/mm total in CMOS VLSI.

Impact on f (assuming zero gate length): gm=2mS/mm, 0.3 fF/mm→f =1.1 THz (InP HEMT) gm=1mS/mm, 0.3 fF/mm→f =550 GHz (GaN HEMT) gm=2mS/mm, 1.0 fF/mm→f =320 GHz (CMOS) Yet, gm is also hard to increase (gate dielectric scaling)

Cend/gm time constant is major bandwidth limit.

...es)/capacitanc end(/2/1 mg gvLf

But the roadmap says VLSI will give 1 THz f...

They have fixed it now, but...

...one recent RF ITRS roadmap predicted: f increases as 1/(technology note)

Physics-free prediction 1) gate length no longer proportional to technology node 2) 1/2f=Lg/v+Cends/gm+... ...some terms no longer scale.

Embellishment, fantabulism,

and balderdash.

Power Transistor Gamesmanship

Quote bandwidth at a low voltage, breakdown at a high one.

For InP HBTs, f drops with increased Vce: Movement of depletion edge decrease in distance before G-L scattering..

For HEMTs, f drops with increased Vce: Lateral movement of gate-drain depletion edge

Gamesmanship with breakdown

Is this breakdown useful ?

How about this ?

In designing PAs, such games would kill the IC.

This is how we specify our HBTs internally...

VLSI specsmanship

It's nice to have high gm, low SS, but (Ion, Ioff, VDD) is better you can have low SS, but a bad leakage tail will increase Ioff.

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

DIBL = 76 mV/V

VT = -85 mV at 1 mA/mm

SSmin

~ 72 mV/dec. (at VDS

= 0.1 V)

SSmin


= 0.5 V)

Lg = 25 nm

VDS

= 0.1 to 0.7 V

0.2 V increment

Cu

rre

nt

De

ns

ity

(m

A/m

m)

Gate Bias (V)

leakage tail

VLSI specmanship

A few recent papers have even done this...

stated off-current using extrapolation

VLSI specmanship

Or quote SS, gm, DIBL etc on a long-channel device Nice to look at...but the VLSI IC will use short-channel FETs...

0.01 0.1 160

70

80

90

100

110

5.0 nm InAs

2.5 nm InAs

Open: VDS

= 0.1 V

Solid: VDS

= 0.5 V

Gate Length (mm)

SS

min (

mV

/de

c)

Transistor benchmarks for circuits

How much gain can we get from a transistor ?


MSG: maximum obtainable gain, with no added feedback, If we add sufficient stabilizing resistance to ensure that no change in the generator or load can cause oscillation

0

5

10

15

20

25

30

10 100 1000

gain

s, dB

Frequency, GHz

Common base MAG/MSG

Common emitter MAG/MSG

Mason's unilateral gain

U: gain if we unilateralize (add lossless reciprocal feedback) and then match.

Note that the common-base MSG is larger than U !


The common-base MSG is larger than U. What does this tell us ? Adding feedback, and then re-stabilizing can increase gain. Even if we ensure unconditional stability.

Is there any upper bound to the gain so obtained ? No !

Mason showed that U is (1) an invariant (with respect to lossless reciprocal embedding) (2) the only invariant calculable from the network parameters.

→ The only limit to such design tricks is component tolerance.

Will such techniques be widely used ? Radios need LNAs and PAs These have quite different design constraints There are few applications for RF "A's" (i.e., not LNA, not PA)

Common-base stages are less stable ????

MSG is the maximum obtainable gain If you don't add feedback and if you ensure that termination changes won't cause oscillation

...so, in what sense is the CB stage less stable ?

0

5

10

15

20

25

30

10 100 1000

gain

s, dB

Frequency, GHz

Common base MAG/MSG



We have a clean measure of noise performance

Vgen

Zs=Zo

noisematch

Zs

invariant.an such not is that Note

embedding. reciprocal losslessw.r.t invariant is that provesMason

1 as measure, noise the, Define

...111

cascade infinitean of figure noise theas Define

min

32

F

M

FMM

G

F

G

F

G

FFF

F

AAA

So, the best low-noise transistor is the one with the smallest M.

Does fmax determine PA gain ? No !

Load is different for gain and for power MAG/MAG/U....obtained with load giving optimum gain load for maximum power is RLopt =(Vmax-Vmin)/Imax, plus parallel L

0

5

10

15

20

25

30

10 100 1000

gain

s, dB

Frequency, GHz

Common base MAG/MSG



Power gain with the optimum load match Can calculate this from transistor model (or Sij) and RL,opt. Load-pull measures this gain.

Are super-high breakdown voltages useful ?

?PA 100GHz afor useful thisIs

V. 100 (2) mmA/ 1 (1)

r with transistohave weSuppose

max brVJ m

realized bet can' 100 :Note max RRL

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Are super-high breakdown voltages useful ?

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Must-Haves for Electronics

RF/microwave/mmwave devices must have...

For general RF amplification, the answer's unclear Unilateral gain & fmax seem reasonable metrics. Fortunately, we always want PAs or LNAs

For low-noise RF transistors, the real metric is noise measure.

For high-power RF transistor, the metrics are maximum output power, and associated gain, into realizable load between ~10 and 100 . this involves both the discussed current & voltage metrics load-pull measures this.

Logic : some desirables

not are OR and AND

NOR is as ,sufficient is alone NAND

functionsBoolean perform should Logic

analysis/power speed/sizein deviceson translatiinclude

"0" and "1" defining valuessame

variablephysical same theof form in theoutput andinput

Cascade should Gates

e.g. , problem if input is DC H-field and output is 50 GHz spin wave amplitude

e.g. , problem if input is DC current and output is DC B-field

tooneeded,probably isout -Fan

e.g. , problem if input is at 2 GHz, and output is at 25 GHz (parametric gain)

Logic Elements Should Communicate

cts.interconne include explicitlymust analysesDelay Energy / Power /

wires.longmany have chips useful :rule sRent'

? big -how- ctsinterconnelonger drive toneeded devicesbigger

/area)complexity(Boolean small very be should gates

distances. longer the thegates, bigger the The

distances.t significan...over

ion / reagent concentration in solution (biology) wires gears (adding machines) optical waveguides

Logic Should Be Robust

restored are levels :Digital

accumulate errors :Analog

t"don' ICs analog , scale ICs Digital" saysRabaey Jan

inVV 0outVV 1

1/ inout dVdV

ties.nonlineariimply toseems This

headache a isn propagatio reverseinput output

ldirectiona-uni (nearly) be should Elements Logic

e.g. , nondegenerate parametric gain ---bilateral

e.g. clockless tunnel diode logic---bilateral RTD

?ally -exponenti- accumulate deviations small do b)

?n distinctioeffect / causeut input/outp lose wedo a)

)time1()time( :reversible

reversiblendissipatio zero

Landauer -despite---me worrieslogicpower Zero

ff

gain.imply toseems This

Second Part

Battling to make

good electron devices


Short course, Device Research Conference, June 21, 2015:


With apologies to my co-authors.

C.-Y. Huang, J. Rode, S. Lee, V. Chobpattanna, P. Choudhary, A.C. Gossard, S. Stemmer ECE and Materials Departments, University of California, Santa Barbara P. Long, E. Wilson, M. Povolotskyi, G. Klimeck Network for Computational Nanotechnology, Purdue University

M. Urteaga, J. Hacker, M. Seo*, Z. Griffith, M. Fields, B. Brar

Teledyne Scientific and Imaging *Now Sunkyunkwan University.

RF, Fast Digital Performance

Figures of Merit

nm Transistors, Far-Infrared Integrated Circuits

IR today→ lasers & bolometers → generate & detect

It's all about the interfaces: contact and gate dielectrics...

Far-infrared ICs: classic device physics, classic circuit design

...wire resistance,...

...heat,...

...& charge density.

band structure and density of states !

92

Transistor figures of Merit / Cutoff Frequencies

H21=short-circuit current gain

gai

ns,

dB

MAG = maximum available power gain: impedance-matched

U= unilateral power gain: feedback nulled, impedance-matched

fmax power-gain cutoff frequency

f current-gain cutoff frequency

What Determines Gate Delay ?

cexLOGIC

LOGIC

Ccb

becbi

becb

C

LOGIC

IRq

kTV

V

IR

CCR

CCI

V

4

leastat bemust swing logic The

resistance base the through

charge stored

collector base Supplying

resistance base the through

charging ecapacitanc on Depleti

swing logic the through

charging ecapacitanc on Depleti

:by ermined Delay DetGate

bb

depletion,bb

depletion,

JVR

v

T

A

A

V

V

I

VC

T)V(VvεJ

CI

CCIV

f

ex

electron

C

CE

LOGIC

C

LOGICcb

cceceelectronKirk

cbC

becbCLOGIC

cb

highat low for low very bemust

22

/2

objective. design key HBTa is / High

total.of 80%-55% is

withcorrelated not well Delay

delay; totalof 25%-10y typicall)(

logic

emitter

collector

min,

2

depletion full,operating ,max,

depl,

HBT Design For Digital & Mixed-Signal Performance

from charge-control analysis:

)./5.05.0(

)/5.05.05.0(

)/5.05.0)(/(

)66)(/(

LCfcbijebb

LCfcbicbxex

LCfcbicbxjeC

fcbicbxjeCLgate

VICCR

VICCR

VICCCqIkT

CCCIVT

analog ICs have similar bandwidth constraints...

Electron Device Design

Transistor scaling laws: ( V,I,R,C,t ) vs. geometry

AR contact /

Bulk and Contact Resistances

Depletion Layers

T

AC e

v

T

2

2

max)(4

T

Vv

A

I applsat e

Thermal Resistance

Fringing Capacitances

e~/ LC finginge~/ LC finging

dominate rmscontact te

escapacitanc fringing FET )1

escapacitancct interconne IC )2

W

L

LK

PT

th

ln~transistor

LK

PT

th

ICIC

Available quantum states to carry current

→ capacitance, transconductance contact resistance 97

L

THz & nm Transistors: State Density Limits

2-D: FET 3-D: BJT

current

conductivity

capacitance

2/1

2/1

3

2 2n

qc

3/2

3/22

8

3n

qc

32

23

4

*

VmqJ

22

2/32/12/52/3

3

*2

VmqJ sheet

2

*2

2

mqCDOS

# of available quantum states / energy determines FET channel capacitance FET and bipolar transistor current access resistance of Ohmic contact

98

Refractory Contacts to In(Ga)As

Refractory: robust under high-current operation / Low penetration depth: ~ 1 nm / Performance sufficient for 32 nm /2.8 THz node.

10-10

10-9

10-8

10-7

10-6

10-5

1018

1019

1020

1021

N-InGaAs

B=0.6 eV

0.4 eV0.2 eV

0 eV

Electron Concentration, cm-3

Co

nta

ct

Re

sis

tivit

y,

cm

2

step-barrierLandauer

1018

1019

1020

1021

N-InAs


0.2 eV

B=0.3 eV

step-barrier

B=0 eV

0.1 eV

Landauer

1018

1019

1020

1021

P-InGaAs

Hole Concentration, cm-3

B=0.8 eV

0.6 eV0.4 eV0.2 eV


requirements for 3 THz HBTs, 7nm III-V CMOS

Baraskar et al, Journal of Applied Physics, 2013

Why no ~2THz HBTs today ? Problem: reproducing these base contacts in full HBT process flow

99


10-10

10-9

10-8

10-7

10-6

10-5

1018

1019

1020

1021

N-InGaAs

B=0.6 eV

0.4 eV0.2 eV

0 eV


Co

nta

ct

Re

sis

tivit

y,

cm

2


1018

1019

1020

1021

N-InAs


0.2 eV

B=0.3 eV

step-barrier

B=0 eV

0.1 eV

Landauer

1018

1019

1020

1021

P-InGaAs


B=0.8 eV

0.6 eV0.4 eV0.2 eV



100

Schottky Barrier is about one lattice constant

what is setting contact resistivity ?

what resistivity should we expect ?



10-10

10-9

10-8

10-7

10-6

10-5

1018

1019

1020

1021

N-InGaAs

B=0.6 eV

0.4 eV0.2 eV

0 eV


Co

nta

ct

Re

sis

tivit

y,

cm

2


1018

1019

1020

1021

N-InAs


0.2 eV

B=0.3 eV

step-barrier

B=0 eV

0.1 eV

Landauer

1018

1019

1020

1021

P-InGaAs


B=0.8 eV

0.6 eV0.4 eV0.2 eV



101

limit)ty reflectivi-quantum

anddensity (state

:yresistivitcontact barrier -Zero

.cm/107 at m 1.0

tcoefficienon transmissi

ionconcentratcarrier

11

3

8

3192

3/22

3/2

2

n

T

n

nTq

c

c

m


Bipolar Transistors

Bipolar Transistor Design eW

bcWcTbT

nbb DT 22

satcc vT 2

ELlength emitter

eex AR /contact

2

through-punchce,operatingce,max cesatc TVVAvI /)(,

contacts

contactsheet

612 AL

W

L

WR

e

bc

e

ebb

e

e

E W

L

L

PT ln1

cccb /TAC e

103

Bipolar Transistor Design: Scaling eW

bcWcTbT

nbb DT 22

satcc vT 2

ELlength emitter cccb /TAC e

eex AR /contact

2

through-punchce,operatingce,max cesatc TVVAvI /)(,

contacts

contactsheet

612 AL

W

L

WR

e

bc

e

ebb

e

e

E W

L

L

PT ln1

104

Scaling Laws, Scaling Roadmap







emitter & base contact resistivities decrease 4:1

Narrow junctions.

Thin layers

High current density

Ultra low resistivity contacts 105

Can we make a 2 THz SiGe Bipolar Transistor ?

InP SiGe

emitter 64 18 nm width

2 0.6 mm2 access

base 64 18 nm contact width,

2.5 0.7 mm2 contact

collector 53 15 nm thick

36 125 mA/mm2

2.75 1.3? V, breakdown

f 1000 1000 GHz

fmax 2000 2000 GHz

PAs 1000 1000 GHz

digital 480 480 GHz

(2:1 static divider metric)

Assumes collector junction 3:1 wider than emitter.

Assumes SiGe contacts no wider than junctions

Simple physics clearly drives scaling

transit times, Ccb/Ic

→ thinner layers, higher current density

high power density → narrow junctions

small junctions→ low resistance contacts

Key challenge: Breakdown

15 nm collector → very low breakdown

Also required:

low resistivity Ohmic contacts to Si

very high current densities: heat

106








channel density of states increase 2:1

source & drain contact resistivities decrease 4:1


GW widthgate

GL







emitter & base contact resistivities decrease 4:1

eW

ELlength emitter

nearly constant junction temperature → linewidths vary as (1 / bandwidth)2

fringing capacitance does not scale → linewidths scale as (1 / bandwidth )

Energy-limited vs. field-limited breakdown

band-band tunneling: base bandgap impact ionization: collector bandgap

108

THz InP HBTs: Performance @ 130 nm Node

Teledyne: M. Urteaga et al: 2011 DRC

109

Needed: Greatly Improved Ohmic Contacts Refractory Emitter Contacts

negligible penetration

110

Base Ohmic Contact Penetration

~5 nm Pt contact penetration (into 25 nm base)

Base Ohmic Contact Penetration

111

Blanket Base Metal Process

112

Parasitics along length of HBT emitter

Base pad & feed increases Ccb

Emitter undercut actual junction shorter than drawn. → excess Ccb , excess base metal resistance

Base metal resistance adds to Rbb

all these factors decrease fmax

113

Field-Effect Transistors

....for RF

114

HEMTs: Key Device for Low Noise Figure

115

1

)(2

)(21

2

min

G

G

G

f

fRRRg

f

fRRRgF

igsm

igsm

Hand-derived modified Fukui Expression, fits CAD simulation extremely well.

0

2

4

6

8

10

1010

1011

1012

ft=300GHzft=600GHzft=1200GHzft=2400GHz

Nois

e f

igu

re,

dB

frequency, Hz

2:1 to 4:1 increase in f → greatly improved noise @ 200-670 GHz.

Better range in sub-mm-wave systems; or use smaller power amps.

Critical: Also enables THz systems beyond 820 GHz

FET Design

g

DSWL

RRS/D

contact

gW width gate

gfgsgd WCC e ,

)/( gchgm LvCg

)/( evWLR ggDS

)density state /well(2// 2

wellwell qTT

WLC

oxox

gg

chg

ee

masstransport

1

capacitors threeabove the

between ratiodivision voltage2/1

v

116

FET Design: Scaling

g

DSWL

RRS/D

contact

gW width gate

gfgsgd WCC e ,

)/( gchgm LvCg

)/( evWLR ggDS


wellwell qTT

WLC

oxox

gg

chg

ee

masstransport

1



v

117

FET Design: Scaling

g

DSWL

RRS/D

contact

gW width gate

gfgsgd WCC e ,

)/( gchgm LvCg

)/( evWLR ggDS


wellwell qTT

WLC

oxox

gg

chg

ee

masstransport

1



v

118

2:1 2:1

constant 2:1 2:1

2:1 2:1

2:1 2:1 2:1

2:1

constant

constant

2:1 2:1

constant

2:1 2:1

4:1

constant

constant











Field-Effect Transistor Scaling Laws

fringing capacitance does not scale → linewidths scale as (1 / bandwidth )

119











Field-Effect Transistors No Longer Scale Properly

120

Gate dielectric can't be much further scaled. Not in CMOS VLSI, not in mm-wave HEMTs

gm/Wg (mS/mm) hard to increase→ Cfringe / gm prevents f scaling.

Shorter gate lengths degrade electrostatics→ reduced gm /Gds

Scaling roadmap for InP HEMTs

121

Field-Effect Transistors ....for logic

122

What goals for logic FETs ?

Low off-state current (nA to pA/mm) for low static dissipation → minimum subthreshold slope→ minimum Lg / Tox low gate tunneling, low band-band tunneling

Low delay CFET V/Id in gates where transistor capacitances dominate.

Parasitic capacitances are 0.5-1.0 fF/mm → low C , high Id

Low delay Cwire V/Id in gates where wiring capacitances dominate.

→ need high Id / Wg

and small !



current density (mA/mm) increase 2:1

transport mass constant

2DEG electron density increase 2:1






nm/VLSI MOSFET Scaling: Ideal and Feasible

GW widthgate

GL

FET parameter

gate length 8 nm

current density (mA/mm) 1 mA/mm @0.5V

transport mass

2DEG electron density 3*1012/cm2

gate-channel capacitance density

dielectric equivalent thickness 0.4 nm (0.8 nm fin)

channel thickness 2 nm (4 nm fin)

channel state density

contact resistivities 0.3 -mm2

nm/VLSI MOSFET Scaling: Goals

GW widthgate

GL

Minimum Dielectric Thickness & Gate Leakage

)2exp(

ion)approximat (WKBy Probabiliton Transmissi

*2

:tcoefficienn Attenuatio

barrier

barrier

TP

Em

-6

-5.5

-5

-4.5

-4

-3.5

-3

-2.5

-2

eV

fro

m v

acu

um

le

vel

Si

InGaAs HfO2

TiO2

Ec

Ev

er ~20 e

r ~40

Aspect ratio and subthreshold swing

grchd WC 0~ ee

/~ DACgs e

gsgrgrgs

gs

chDchsgs

gs

g CWWC

C

CCC

C

V /21

1

2

00 eeee

)/21)(/(

expexp 0

gsgr

gate

DCWqkT

V

kT

qI

ee

Contact Resistance Scaling

With the above #s, contacts degrade on-current by ~15% A 2.4 mm2 contact would reduce the current 2:1

Mobility in Thin Channels: Surface Roughness Scattering

0 1 2 3 4 5 6 70

200

400

600

800

1000

1200

x 1012

me

ff (

cm

2/s

-V)

Carrier Density (/cm2)

2.5 nm InAs

5.0 nm InAs

0.01 0.1 10.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8InAs channel thickness

2.5 nm

5.0 nm

VDS

= 0.5 V

Gate Length (mm)

Pe

ak

gm (

mS

/mm

)mobility in FET channels

Sakaki 2

62

Mobility well

wellq

T

Tm

Mobility is high if surfaces are smooth

Quantum well: smooth surfaces

FET: rough surfaces

2

62

Mobility well

wellq

T

Tm

Terms in gate-channel capacitance

inversiondepth /Tc e

oxc

)( thgs VV

2*2 2/ gmqcdos

)2/()()(charge channel 2* gmEEqVVcqn wellfwellfdoss

motion) onalunidirecti(

scale. both alsomust states ofdensity & thicknessInversion

qEE wellf /)(

Calculating Current in Ballistic Limit

fvv )3/4( velocity electron mean

2/3

2/3

,

2/1

V 1)/*()/(1

)/*(

m

mA 84

thgs

ooxodos

oVV

mmgcc

mmgJ

m

minima band of # theis where, )/*(2/* ,

22 gmmgcgmqc oodosdos

thgs

dosequiv

equivdos

cfdos VVcc

ccVVc

s :charge Channel

2/* through velocity Fermidetermines

toapplied voltage voltage FermiChannel

2

ffff

dos

vmqVEv

c

Natori

2010 DRC Rodwell,

InGaAs MOSFETs: superior Id to Si at large EOT. InGaAs MOSFETs: inferior Id to Si at small EOT.

2/3*

,

2/1*

1

2/3

1

)/()/(1 where,

V 1m

mA84

oequivodos

othgs

mmgcc

mmgK

VVKJ

m

Drive current versus mass, # valleys, and EOT

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

no

rma

lized

drive

cu

rre

nt

K1

m*/mo

g=2

EET=1.0 nm

0.6 nm

0.4 nm

g=1

InGaAs <--> InP Si

0.3 nm

EET=Equivalent Electrostatic Thickness

=Tox

eSiO2

/eox

+Tinversion

eSiO2

/esemiconductor

/EOTε

)/c/c(c oxequiv

2SiO

1

depth

11

Why III-V MOS ?

III-V vs. Si: Low m*→ higher velocity. Fewer states→ less scattering → higher current. Can then trade for lower voltage or smaller FETs.

Problems: Low m*→ less charge. Low m* → more S/D tunneling. Narrow bandgap→ more band-band tunneling, impact ionization.

135

InGaAs/InAs FETs are leaky!

136

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (

mS

/mm

)

Cu

rre

nt

De

ns

ity

(m

A/m

m)

Gate Bias (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0L

g = 25 nm

SS~ 72 mV/dec.

SS~ 77 mV/dec.

Ion= 500 mA/mm at Ioff

=100 nA/mm

and VD=0.5V

10 100

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

S. Lee, VLSI 2014

J. Lin, IEDM 2013

T. Kim, IEDM 2013

Intel, IEDM 2009

J. Gu, IEDM 2012

D. Kim, IEDM 2012

I on (

mA

/mm

)

Gate Length (nm)

VDS

= 0.5 V

Ioff

=100 nA/mm

HP = High Performance: Ioff =100 nA/mm

GP = General Purpose: Ioff =1 nA/mm

LP = Low Power: Ioff =30 pA/mm

ULP = Ultra Low Power: Ioff =10 pA/mm

III-V MOSFET

*Heavy elements look brighter Courtesy of S. Kraemer (UCSB) Lee et al., 2014 VSLI Symposium

III-V MOSFET

Courtesy of S. Kraemer (UCSB)

Huang et al., 2015 DRC

Reducing leakage: Ultra-thin channel

139

10 100

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

S. Lee, VLSI 2014

J. Lin, IEDM 2013

T. Kim, IEDM 2013

Intel, IEDM 2009

J. Gu, IEDM 2012

D. Kim, IEDM 2012

I on (

mA

/mm

)

Gate Length (nm)

VDS

= 0.5 V

Ioff

=100 nA/mm

S. Lee et al., VLSI 2014

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

DIBL = 76 mV/V

VT = -85 mV at 1 mA/mm

SSmin


= 0.1 V)

SSmin


= 0.5 V)

Lg = 25 nm

VDS

= 0.1 to 0.7 V

0.2 V increment

Cu

rre

nt

De

ns

ity

(m

A/m

m)

Gate Bias (V)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

0.2

0.4

0.6

0.8

1.0

1.2

Cu

rre

nt

De

ns

ity

(m

A/m

m)

Drain Bias (V)

Ron

= 303 Ohm-mm

at VGS

= 0.7 V

VGS

= -0.4 V to 0.7 V

0.1 V increment

0.01 0.1 160

70

80

90

100

110

120 [2]

[4]

[3]

[7]

[1]

[6]

[5]

Solid: VDS

= 0.5 V

Open: VDS

= 0.1 V

Gate Length (mm)

SS

min (

mV

/de

c.)

This work

[1] Lin IEDM 2013,[2] T.-W. Kim IEDM 2013,[3] Chang IEDM 2013,[4] Kim IEDM 2013 [5] Lee APL 2013 (UCSB), [6] D. H. Kim IEDM 2012,[7] Gu IEDM 2012,[8] Radosavljevic IEDM 2009

On-state comparison: 2.5 nm vs. 5.0 nm-thick InAs channel

0.01 0.1 10.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8InAs channel thickness

2.5 nm

5.0 nm

VDS

= 0.5 V

Gate Length (mm)

Pe

ak

gm (

mS

/mm

)

0 1 2 3 4 5 6 70

200

400

600

800

1000

1200

x 1012

me

ff (

cm

2/s

-V)

Carrier Density (/cm2)

2.5 nm InAs

5.0 nm InAs

-0.2 0.0 0.2 0.4 0.60.0

0.5

1.0

1.5

2.0

2.5

Cox

= 4.2 mF/cm2

EOT= 0.8 nm

W/L= 25mm/21 mm

Freq: 200kHz

2.5 nm InAs

5.0 nm InAs

Ga

te C

ap

ac

ita

nc

e (

mF

/cm

2)

Gate Bias (V)

0

1

2

3

4

5

6

7

x 1

01

2

Ca

rrie

r D

en

sit

y (

/cm

2)

0.4

0.2

-0.2

0.0

-0.4

-0.6

0.6

0.8

EF

E1En

erg

y (

eV

)

Position (nm)10 20 30

EF

E1

Position (nm)10 20 30

~1.25 nm ~2.5 nm

2.5 nm thick 5 nm thick

1D-Possion Schrodinger solver (coded by W. Frensley, UT Dallas)

140

Wrap-Up

What are the challenges

Small dimensions Thin semiconductor layers (2-3nm) Extremely low resistance contacts High current densities Very thin dielectrics Available semiconductor states (III-Vs) Resistances in interconnects and electrodes

Where lies the future of electronics ?

"End of the scaling roadmap" "More than Moore"

tubes bipolar transistors field-effect transistors electrostatic barrier

Time for a new approach ?

Gravitonics ?

Quarkonics ?

Mechanics ? 1000's of heavy Nuclei ...

Magnetics ? F ~ v1v2/c

2→ weak!

Charge-control: fundamentally best electrons are light electrostatic force: strong & long-range

The future of electronics: classic charge-control devices few-nm dimensions, 1012-scale integration multi-THz bandwidths

electromagnetic waves: strong, long-range → electromagnetic interconnects (wires !) are best: efficient, dense Neutrinonics ?

(backup slides follow)

legend and folklore: a bestiary of electronics · · 2015-07-28legend and folklore: a bestiary of...

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