logic modeling, testing,verification , cadence

8/13/2019 Logic Modeling, TESTING,VERIFICATION , CADENCE

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-- Satish Kumar Grandhi

Logic Modeling & Simulation


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Introduction Logic Modeling techniques

Objectives, Challenges

Logic Simulator Classification

Problems affecting Simulators


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omenc a ure

Reconvergent Fan out Different paths from the same signal

merging at some component

Level

Measure of the element distance

from the primary inputs

Level of primary inputs is fixed to be

0

Level of an element I whose inputs

come from element K1, K2, Ki

L(i) = 1 + max L (Kj)


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Levels of Modeling

Behavior HDL Languages

Logic Structural representation using

primitive modules

Gate Timing information, Gates used to

define all modules

Circuit Tech. Data, device parameters,.

Refers to primitive component used

in the model

Higher level model provides abstract

view of system ; but involves loss of

accuracy and detail

Lower level model requires large

computing resources; memory

capacity, processing time

Trade off : Complexity Vs Accuracy


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Binary Decision Diagrams

(BDD) Graph model of the function of a circuit

Simple graph traversal determines the value of the output

A . represents 0 ; otherwise 1

Combinational

Sequential

Any Difference ???


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Constructing a BDD


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Truth Tables and Cubes

F( n Variables) Table of 2n Entries

V -- > Table entry

Z -- > Function

V(2n1) = Z(1,1,1.1)

Cubeof a function represent a entryin the truth table

A cube of a function Z(x1, x2.) hasthe form (v1, v2,.| vZ)

00x|1 is a cube of the function Z andrepresents x1x2 implicant

00x|1 covers000|1 & 001|1

If V= 010 , then Z = ?? { useintersection operator }

1. Truth Table

2. Primitive Cubes

3. Intersection Operator


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Unknown Logic Value Response of a sequential circuit depends on its initial state, usually

unpredictable

Simulation algorithms use separate logic U to process unknown state

turning it into 3 valued system {0 , 1, U}

Loss of information with 3 valued system

??


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Issues with 3 Valued logic

Reconvergent fan-out results in pessimistic results

Use of complementary unknown values U & U might help ?? NO

Solution : Use several distinct unknown signals u1, u2, u3for every

variable such that Ui* Ui= 0 && Ui+ Ui

= 1 Highly Tedious


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Logic Simulation Methodology adopted to predict the behavior of a design prior to its

physical realization

Ascertains that the design performs its specified behavior

During the initial days (MSI era), prototypes were used for verification

Runs @ operating frequency

Costly and Time consuming Lacks accuracy as models of ICs

Simulation replaces the

prototype methodology Higher Accuracy andeasy analysis


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Objectives

Design Verification (Pre-Silicon)

To find design errors

Error space cannot be defined ; Hence, Fault coverage does not exist

Generally, errors are related to data transfers and transformations rather

than the data operations itself

Manufactured IC Verification (Post-Silicon)

To detect physical faults

Design errors are enumerable whose behavior is well defined

Can Compute Fault Coverage


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Challenges Generating input stimuli

Methodology to ascertain that results are correct

How Good are the applied input stimuli ?

In reality, Design Verification suffers from several limitations Lack of formal procedures to generate tests

Producing the stimuli is heuristic ; relying heavily on engineers intuition

System that passes the test is correct only wrt the applied test

Completeness of the tests cannot be promised

In spite of all these limitations, logic simulation is invaluable esp. for

VLSI designs where prototypes are impractical


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Simulator ClassificationTerminology Active signal Signals when changing their value @ arbitrary time

Activity Ratio of active signals to total number of signals { Generally, itsmax value is 5%origin for low power design concepts}

Event Represents the change in the value of the signal

Simulators classification

Compiler Driven Executes a compiled code model

Event Driven Executes based on active signals

Problems affecting Simulators

Treatment of unknown values

Delay Modeling

Hazard Detection

Oscillation Control


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Compiled Code Simulator Code turns into simulator ; seeking inputs and flushing outputs Translate the logic network into a series of machine instructions

Assume timing values are intact (No setup or hold violations) ;enables us to ignore delays

Code model is generated such that preceding level signals are

evaluated Parallel Pattern evaluation can be used for simultaneous evaluation ;

works only for combinational

Note : Evaluates all signals for every input vector


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Event Driven Simulator An event-driven simulator monitors the occurrences of events

Maintains an Activity list which determine which gates to evaluate

2

2

4

2

b=1

c =1 0

d = 0

e =1

f =0

Time, t

0 4 8

g


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Compiled Code Vs. Event

Driven

Event-drivenBased on Signal Activity

Implementing gate delays and

detecting hazards

Low switching activity circuits

More complicated memory

management

Compiled-codeCycle-based simulation

High switching activity circuits

Parallel simulation

Limited by compilation times


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Gate Level Event Driven

Simulator Events scheduled to occur @ the

same time are stored in thesame list

Time order is appropriately

maintained according to order.< tp


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Two Pass strategy First, it retrieves the entries from

the event list and determines

activated gates

Then, it evaluates the activated

gates and schedules their

computed values

Due to (a,0) @4, (Z,0) is scheduled @ 12

But, Z is already set to zero @ 10Issue


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Modified.

Guaranteed to schedule true

events only

Compares the new value Vj with

the last scheduled valueof j,

denoted by lsv(j)

Fewer schedule operations

More memory to maintain last

schedule events

Efficiency depends on number of

unnecessary events


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One Pass strategy Evaluates a gate as soon as it is

activated

Avoids constructing the activated

set

a & b Scheduled to change @

same time

If events are retrieved in the

sequence

(b,0), (a,1) Z is never

scheduled

(a,1), (b,0) Z will under go both

0-1 & 1-0 transition, resulting in

spike

Improvement : Cancel previously

Scheduled event if gate output is

scheduled repeatedly @ the same

Issue Results depending on processing of

concurrent events : UNACCEPTABLE


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Transport Vs Inertial Delay

Transport DelayThe time duration it takes for the effect

of gate input changes to appear at

gate outputs

Inertial Delay

The minimum input pulse durationnecessary for the output toswitch states


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Continued

Propagation or Transport delays : Da& Db Transition or Inertial delay : Dc


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Gate Delay Modeling In modeling the behavior of gate, function and timing are separately

dealt with

Activated element is evaluated first

Delays are computed later

In high speed circuits, wire delay is comparable to component delay

As they depend on wire length, predictable only after routing

Wire Delay


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Delay Models

Zero & unit delay models Transition dependent delay models

Delay differs for rise(Dr) & fall(Df) transition

Can result in impossible events

Ambiguous delay model

Delay value varies, say Dmin& DMAX Results in intervals during which the signal

value is not precisely defined

Inverter with Dr = 12 & Df=7

I/P pulse : 1 0 1 of pulse width 4

1stI/P tran schedules O/P @ 12

2ndI/P tran schedules O/P @ 11


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Issues with Arbitrary Delay

Model Computes the earliest & latest times @which signal changes can occur

In presence of Reconvergent Fan-out, arbitrary delay model may result

in pessimistic results

Incorrect, because transitions on A & B are dependent

Transition on B occurs after *6,10+ only once A is stable

No chance of STATIC HAZARD @ C


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Other Relevant Terminology

(delay) SETUP / HOLD Minimum time a signal has

to be present at the inputpin of a memory cellbefore/afterthe write signalarrives.

RECOVARY / REMOVAL

Minimum time you mustleave between anasynchronous clear/setsignal and before/after the

clock of the cell is triggered.

MINIMUM PULSE WIDTH

Minimum width a controlsignal must have in order

for the cell to detect it.


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Hazards Unwanted pulses or glitches ; must analyze dynamic behavior to

detect

Static or dynamic

A dynamic hazard refers to the transient pulse during a 0-to- 1 or 1-

to-0 transition

A static hazard refers to the transient pulse on a signal line whose

static value does not change

Reference : http://cset.sp.utoledo.edu/eet3350/lesson1.html

(look at this link for good treatment of hazards & Avoid them

Static0 Static1

Dynamic1 Dynamic0
http://cset.sp.utoledo.edu/eet3350/lesson1.htmlhttp://cset.sp.utoledo.edu/eet3350/lesson1.html


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Static Hazard


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Dynamic Hazard


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Detecting Static Hazards

Directly Extracted from Reference 2 Textbook

H d D i D l M d l


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Hazard Detection Delay Model

Role

I/P Sequence A = 010

Zero Delay Model:

B = 101 & C = 000 ; No Hazard

Models only static behavior; Ignores dynamic behavior

Unit Delay Model:

B = 1101 & C = 0010 ; Pulse in response to 0 --> 1 transition of A

Arbitrary Delay Model: A = 0u1u0 ; B = 1u0u1 ; C = 0u0u0 (from previous slide)

Hazard predicted for both rise & fall transitions of input

Overly Pessimistic bcos , in general, one of the paths to AND gate will havegreater delay which will cause a hazard

Arbitrary delay model cannot predict which path results in higher delay

H d D t ti i A


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Hazard Detection in Async.

Ckts

Directly Extracted from Reference 2 Textbook


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Example

Step 1 : Set R = S = u => Q = Qn= u

Step 2 : Set R = S = 1 => Q = Qn= u

Hence, under arbitrary delay model, the operation of the circuit is

unpredictable

Depending on actual delays, the circuit may oscillate

At time t,

R = S = 0

Q = Qn= 1

At time t+1,

R = S = 1


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Oscillation Control Issue: Simulation of a circuit that oscillates results in repeated

scheduling & processing of same sequence of events : results in

endless loop

Detecting Oscillations during simulation and taking appropriate

corrective action

Local oscillation control: Identifying conditions causing oscillations inlocal sub circuits like latches & Flops

Global oscillation control: Identifying signals which have unusually

high activity


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Assignment - 1 Will be uploaded on the course webpage on 3rdJan2011 You need to submit your answers on or before 5PM ; 10thJan2011

Solutions for all the problems will be uploaded @ 5PM ; 10thJan

2011

No copying ; 0 marks if find any two solutions following the same

pattern

No Late Submission ; 0 marks in this case also

logic modeling, testing,verification , cadence

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