Low-Power Pipelined ADC Design for Wireless LANs

J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla

Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Univ. de Valladolid, Spain.

V. Boccuzzi, M. Banu

Agere Systems, 555 Union Boulevard, Allentown, Pennsylvania, 18109, USA

DesignFunctional

Blocks Simulation ExperimentalResults

EVMmeasurements

measurements

measurementsNonlinearity

SNR & SNDR

Monte−Carlo

Spectre

Operational

Amplifiers

Flash−ADCs

DACs

Digital logic

Single Stage

Architecture

INDEX

Block Diagram of the ADC

Ana

log

Inpu

t

Stage Stage

Stage Stage Stage Stage

#1 #2 #9

Stage Stage

#1 #2 #8

#8

#9

Dig

ital O

utpu

t

MUX

Digital Delay & Correction Logic

Digital Delay & Correction Logic

Eve

n S

ampl

esO

dd s

ampl

es

Transfer function

Simplified Pipeline Stage

+

−

−Vref4

+Vref4

−Vref/4

+Vref/4

(Cs)

Vin

+Vref 0 −VrefDigitalOutput

Φ1

Φ1

Φ1Φ2

Φ2

Φ2Vres

1.5−bit Flash ADC 1.5−bit DAC

SHA

C1 (Cs)

C2

+Vref−Vref

+Vref

−Vref

−Vref

+Vref2

2

0

0

01 1100

Operational Amplifiers

µ s166 V/

CMFB

CT

SC

Vbpc

Vbnc

Vo+ Vo−

Vi+ Vi−

VDD

GND

Cc2

Cc1

VbnCMFB

OUTER

INNER

Cc1

Cc2

First stage is a telescopic cascode:

− 2 cascode nodes available for

Two Common−Mode−Feedback loops:− Good stability− Outer loop is a SC circuit due to

linearity requirements.

Phase−Margin

compensation:

− Large DC gain:

Main Specs:

− Gain−Bandwidth: 200 MHz− Slew rate:

give more Gain−Bandwidth or

· Low Parasitics

· Split Compensation Capacitors

· Short−channel devices are OK

1.5−Bit, Flash, sub−ADC

/bit 0

/bit 1

The

rmom

eter

out

put

Cs

Cs

Cs

Cs

− No charge pumping. Low Power

· Charge injection generate offsets

· Offsets are removed through digital correction

− Sensitive to charge injection from switches, but:

Vi+

Vi−

Vcm

Vcm

Vref/4−

Vref/4+

bit 0

bit 1

Φ1

Φ1

Φ1

Φ1

Φ2

Φ2

Φ2

Φ2

Φ2

Φ2

Φ2

Φ2

Comparator

CLK

Vi−Vi+

Out−

Out+

/CLKVbn

VDD

M2

M3 M4

M1

M5

M6

M7

M8

M9

M10

m11 Low−gain Preamplifier

− Isolates input from kick−back noise

− fast settling

Full−Swing Latch

− Fast regeneration. No metastability

− Rail−to−rail output

Clocked output

− Avoids non−CMOS levels

1.5−Bit sub−DAC

/φ2

a

b

c

Ι0

I1

/I0

/I1

Sb

Sc

Sa

Sa

Sc

Sb

Vcm

+Vref

−Vref

+Dac

−Dac

The

rmom

eter

inpu

t

Sw

itch

cont

rol

− High impedance output during phase 1. This saves 2 series−switches in the S&H circuit

− High linearity thanks to wire−crossing inversion

Analog Pipeline

Digital Delay and Correction Circuit

Σs

c

Σs

c

Σs

c

Σs

c

Σs

c

Σs

c

Σs

c1

stage

stage

stage

stage

stage

2

3

4

5

stage

stage

stage

6

7

8

p1

d1

d0

d1

d0

d1

d0

d1

d0

d1

d0

d1

d0

d1

d0

d1

d0

d1

d0

(no amps)

9

stage

p2p2 p1 p2 p1 p2 p1

p2

p1

p1

p2

p1

p2

p1

p2

p1

D1

D0

D2

D3

D4

D5

D6

D7

D8

D9

p2 p1

-0.4

-0.2

0

0.2

0.4

0 128 256 384 512 640 768 896 1024

INL

(LS

B)

ADC code

0

100

200

300

400

500

600

0 0.2 0.4 0.6 0.8 1

Cou

nts

�

Max. nonlinearity

INLDNL

Single INL run Monte−Carlo

System−level Simulation

Effects simulated:

− Finite opamp gain

− Digital correction logic.

− Capacitor mismatch

− Comparator offset

-80

-60

-40

-20

0

0 2 4 6 8 10 12 14 16 18 20

Am

pl. (

dB)

Freq. (MHz)

Transistor−level Simulation (Spectre)

− Distortion < −60 dB

− Power: 11.5 mW

· Analog: 9.75 mW

Effects not included:

− Mismatch

− Circuit noise

· Digital: 1.75 mW

− Simulated from extracted circuit

Chip photograph

Area: 1500 x 880 µm2, including pads.

Measurements

Measured Nonlinearity Graphs

-1

-0.5

0

0.5

1

0 128 256 384 512 640 768 896 1024

DN

L (L

SB

)

�

ADC code

-1

-0.5

0

0.5

1

0 128 256 384 512 640 768 896 1024

DN

L (L

SB

)

�

ADC code

-1

-0.5

0

0.5

1

0 128 256 384 512 640 768 896 1024

INL

(LS

B)

ADC code

-1

-0.5

0

0.5

1

0 128 256 384 512 640 768 896 1024

INL

(LS

B)

ADC code

- Code density measurement with sinusoidal input.

Frequency-domain measurements

-120

-100

-80

-60

-40

-20

0

9 9.5 10 10.5 11

Am

plitu

de (

dB)

Frequency (MHz)

30

35

40

45

50

55

60

-30 -25 -20 -15 -10 -5 0

SN

DR

(dB

)

�

Input amplitude (dB)

1 MHz, CT13.3 MHz, CT

13.3 MHz, sampled19.3 MHz, sampled, INL corr.

- Single and two-tone tests

- Continuous time and sampled sinusoids.

EVM measurements with real OFDM signals

-1

0

1

-1 0 1

IQ constellation

0

1

2

3

4

5

6

7

-25 -20 -15 -10 -5 0 5E

VM

(pe

rcen

t, rm

s)

Input amplitude (dB)

DUTE1439A

- 54-Mbit/s OFDM signal (IEEE 802.11a/g). 10 MHz carrier.

- Agilent’s EVM test equipment & software.

Performance summaryResolution 10 bits

Sampling Rate 40 MHzPower ADC: 11.7 mW

consumption Pin drivers: 1.3 mW(CL 4.5 pF)

Technology 2.5-V, 0.25-µm, CMOS (MOM cap.)Chip Area (w. pads) 1.5 0.88 mm2

(wo. pads) 1.2 0.58 mm2

Nonlinearity DNL: 0.77 LSB(max) INL: 1.15 LSBSNR 61.3 dB

SNDR 57.6 dBENOB 9.3 bit

Low-Power Pipelined ADC Design for Wireless LANs

J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla

Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Univ. de Valladolid, Spain.

V. Boccuzzi, M. Banu

Agere Systems, 555 Union Boulevard, Allentown, Pennsylvania, 18109, USA

Circuit

Outer CMFB

Circuit

GND

VDD

Inner CMFB

Operational Amplifiers

− Continuous−time

− Diff. pair + level shifter

− Small differential−input range

− Discrete−time

− Highly linear. Large input range

− Two circuits operate on alternate clock phases

Φ1

Φ1 Φ1

Φ2

Φ2Φ2

Φ2Φ1 Φ2 Φ2 Φ1 Φ1

Φ2 Φ1Vcm

Vo+

Vbn

Vo−

CMFB

CMFB

Vo+ Vo−

Performance summaryResolution 10 bits

Sampling Rate 40 MHzPower ADC: 11.7 mW

consumption Pin drivers: 1.3 mW(CL 4.5 pF)

Technology 2.5-V, 0.25-µm, CMOS (MOM cap.)Chip Area (w. pads) 1.5 0.88 mm2

(wo. pads) 1.2 0.58 mm2

Nonlinearity DNL: 0.77 LSBINL: 1.15 LSB

SNR (max) 61.3 dB @ 10.6 MHzSNDR (max) 57.6 dB @ 1 MHz

57.8 dB @ 19.3 MHz†

59.0 dB @ 19.3 MHz††

ENOB (max) 9.3 bit @ 1 MHz9.3 bit @ 19.3 MHz†

9.6 bit @ 19.3 MHz††

Notes:

† Sampled input.

†† Sampled input and static INL correction.

OFDM modulation

➯ Large number of subcarriers per channel.

➯ Orthogonality = No interference bw. subcarriers.

Ts

0Ai cos ωit ϕi A j cos ω jt ϕ j dt 0

➯ OFDM modulation and demodulation are done via Fast Fourier Transforms (FFT).

OFDM (standard IEEE 802.11a/g)

0−10 MHz +10 MHz

Symbol time (4 us)

FFT time (3.2 us)

64 sub−carriers, but

54 used subcarriers.

48 carriers for data.

im

re

64−QAM subcarrier

Subcarrier modulation: QAM

QAM constellations:

OFDM channel spectrum

64 (54 mb/s), 16 or 4 points.

288 bits

− No DC carrier (f=0 Hz)

− No carriers close to adjadcent channels