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LP38500-ADJ, LP38502-ADJSNVS539H –NOVEMBER 2007–REVISED SEPTEMBER 2015

LP3850x-ADJ, LP3850xA-ADJ 1.5-A Flexcap Low-Dropout Linear Regulatorfor 2.7-V to 5.5-V Inputs

1 Features 3 DescriptionTI's FlexCap low-dropout (LDO) linear regulators

1• Input Voltage: 2.7 V to 5.5 Vfeature unique compensation that allow use of any• Adjustable Output Voltage: 0.6 V to 5 V type of output capacitor with no limits on minimum or

• FlexCap: Stable with Ceramic, Tantalum, or maximum equivalent series resistance (ESR). TheAluminum Capacitors LP38500 and LP38502 series of LDOs operates from

a 2.7-V to 5.5-V input supply. These ultra-low-dropout• Stable with 10-µF Input and Output Capacitorslinear regulators respond very quickly to step• Low Ground-Pin Current changes in load, making them suitable for low-voltage

• 25-nA Quiescent Current in Shutdown Mode microprocessor applications. Developed on a CMOSprocess (utilizing a PMOS pass transistor) the• Ensured Output Current of 1.5 ALP38500-ADJ and LP38502-ADJ have low quiescent• Ensured VADJ Accuracy of ±1.5% at 25°C (A currents that changes little with load current.Grade)• GND Pin Current: Typically 2 mA at 1.5-A load• Ensured Accuracy of ±3.5% at 25°C (STD) current.

• Overtemperature and Overcurrent Protection • Disable Mode: Typically 25-nA quiescent current• ENABLE Pin (LP38502) when the EN pin is pulled low. (LP38502-ADJ)

• Simplified Compensation: Stable with any type of2 Applications output capacitor, regardless of ESR.

• Precision Output: A grade versions available with• ASIC Power Supplies In:1.5% VADJ tolerance (25°C) and 3% over line,– Printers, Graphics Cards, DVD Players load, and temperature.

– Set Top Boxes, Copiers, RoutersDevice Information(1)• DSP and FPGA Power Supplies

PART NUMBER PACKAGE BODY SIZE (NOM)• SMPS RegulatorDDPAK/TO-263 (5) 10.16 mm x 8.42 mm• Conversion from 3.3-V or 5-V Rail LP38500 TO-263 (5) 10.16 mm x 9.85 mmLP38502WSON (8) 3.00 mm x 2.50 mm

(1) For all available packages, see the orderable addendum atthe end of the datasheet.

Typical Circuit (LP38500)Typical Circuit (LP38502)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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LP38500-ADJ, LP38502-ADJSNVS539H –NOVEMBER 2007–REVISED SEPTEMBER 2015 www.ti.com

Table of Contents7.4 Device Functional Modes........................................ 121 Features .................................................................. 1

8 Application and Implementation ........................ 132 Applications ........................................................... 18.1 Application Information............................................ 133 Description ............................................................. 18.2 Typical Applications ............................................... 134 Revision History..................................................... 2

9 Power Supply Recommendations ...................... 165 Pin Configurations and Functions ....................... 39.1 Power Dissipation/Heatsinking................................ 166 Specifications......................................................... 4

10 Layout................................................................... 176.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 176.2 ESD Ratings.............................................................. 410.2 Layout Examples................................................... 176.3 Recommended Operating Conditions....................... 4

11 Device and Documentation Support ................. 206.4 Thermal Information .................................................. 411.1 Documentation Support ........................................ 206.5 Electrical Characteristics........................................... 511.2 Community Resources.......................................... 206.6 Typical Characteristics .............................................. 711.3 Trademarks ........................................................... 207 Detailed Description .............................................. 911.4 Electrostatic Discharge Caution............................ 207.1 Overview ................................................................... 911.5 Glossary ................................................................ 207.2 Functional Block Diagrams ....................................... 9

12 Mechanical, Packaging, and Orderable7.3 Feature Description................................................. 10Information ........................................................... 20

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (June 2015) to Revision H Page

• Changed thermal values for KTT (DDPAK/TO-263); add notes 2 and 3 to Thermal Information table ................................ 4

Changes from Revision F (April 2013) to Revision G Page

• Added Added Device Information and Pin Configuration and Functions sections, ESD Ratings and updated ThermalInformation tables, Feature Description, Device Functional Modes, Application and Implementation, Power SupplyRecommendations, Layout, Device and Documentation Support , and Mechanical, Packaging, and OrderableInformation sections................................................................................................................................................................ 1

• Deleted obsolete heatsinking information for DDPAK/TO-263 package ............................................................................. 16

Changes from Revision E (April 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 19

2 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

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LP38500-ADJ, LP38502-ADJwww.ti.com SNVS539H –NOVEMBER 2007–REVISED SEPTEMBER 2015

5 Pin Configurations and Functions

KTT Package (LP38500) KTT Package (LP38502)5-Pin DDPAK/TO-263 5-Pin DDPAK/TO-263

Top View Top View

NDQ Package (LP38500) NDQ Package (LP38502)5-Pin TO-263 5-Pin TO-263

Top View Top View

NGS Package (LP38500A) NGS Package (LP38502A)8-Pin WSON 8-Pin WSON

Top View Top View

Pin FunctionsPIN

TYPE DESCRIPTIONNAME KTT NDQ NGSADJ 5 5 8 O Sets output voltage

Enable (LP38502-ADJ only). Pull high to enable the output, low to disable the output.EN 1 1 2 I This pin has no internal bias and must be either tied to the input voltage, or actively

driven.GND 3 3 1 G Ground

Input supply (LP38500-ADJ only). Input supply pins share current and must beIN — — 2 I connected together on the PC board.Input supply. Input Supply pins share current and must be connected together on theIN 2 2 3, 4 I PC board.In the LP38500-ADJ, this pin has no internal connections. It can be left floating or usedN/C 1 1 — — for trace routing.Regulated output voltage. Output pins share current and must be connected together onOUT 4 4 5, 6, 7 O the PC board.The DAP is used to remove heat from the device by conducting it to a copper clad areaon the PCB which acts as a heatsink. The DAP is electrically connected to the backsideDAP √ √ √ — of the die. The DAP must be connected to ground potential, but can not be used as theonly ground connection.

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6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1) (2)

MIN MAX UNITInput pin voltage (survival) −0.3 6 VEnable pin voltage (survival) −0.3 6 VOutput pin voltage (survival) −0.3 6 VIOUT (survival) Internally limitedPower dissipation (3) Internally limitedStorage temperature, Tstg −65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Office/ Distributors for availability andspecifications.

(3) Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD),maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RθJA). See Application andImplementation.

6.2 ESD RatingsVALUE UNIT

VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. have higherperformance.

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted) (1)

MIN NOM MAX UNITInput supply voltage 2.7 5.5 VEnable input voltage 0 5.5 VOutput current (DC) 0 1.5 AVOUT 0.6 5 VJunction temperature (1) −40 125 °C

(1) Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD),maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RθJA). See Application andImplementation.

6.4 Thermal InformationLP38500 and LP38502

THERMAL METRIC (1) KTT(DDPAK/TO-263) NDQ (TO-263) NGS (WSON) UNIT5 PINS 5 PINS 8 PINS

RθJA(2) Junction-to-ambient thermal resistance 41.8 33.3 52.5 (3) °C/W

RθJC(top) Junction-to-case (top) thermal resistance 45.0 22.1 53.6 °C/WRθJB Junction-to-board thermal resistance 24.8 16.9 26.1 °C/WψJT Junction-to-top characterization parameter 13.1 5.8 0.6 °C/WψJB Junction-to-board characterization parameter 23.8 16.8 26.3 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 2.3 7.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7, High Effective ThermalConductivity Test Board for Leaded Surface Mount Packages.

(3) The PCB for the NGN (WSON) package RθJA includes thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.





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6.5 Electrical CharacteristicsUnless otherwise specified VIN = 3.3 V, IOUT = 10 mA, CIN = 10 μF, COUT = 10 μF, VEN = VIN, VOUT = 1.8 V. Minimum andmaximum limits apply over the junction temperature (TJ) range of –40°C to +125°C and are specified through test, design, orstatistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for referencepurposes only.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT2.7 V ≤ VIN ≤ 5.5 V10 mA ≤ IOUT ≤ 1.5 A 0.584 0.605 0.626TJ = 25°CVADJ Adjust pin voltage (1) V2.7 V ≤ VIN ≤ 5.5 V 0.575 0.63510 mA ≤ IOUT ≤ 1.5 A2.7 V ≤ VIN ≤ 5.5 V10 mA ≤ IOUT ≤ 1.5 A 0.596 0.605 0.614TJ = 25°CVADJ Adjust pin voltage (A grade) (1) V2.7 V ≤ VIN ≤ 5.5 V 0.587 0.62310 mA ≤ IOUT ≤ 1.5 A2.7 V ≤ VIN ≤ 5.5 V 50 nATJ = 25°CIADJ ADJUST pin bias current2.7 V ≤ VIN ≤ 5.5 V 750 nAIOUT = 1.5 A 220 275 mVTJ = 25°CVDO Dropout voltage (2)

IOUT = 1.5 A 375 mV2.7 V ≤ VIN ≤ 5.5 V 0.04 %/VΔVOUT / TJ = 25°COutput voltage line regulation (1) (3)

ΔVIN 2.7 V ≤ VIN ≤ 5.5 V 0.05 %/V10 mA < IOUT < 1.5 A 0.18 %/AΔVOUT / Output voltage load regulation (1)TJ = 25°C

ΔIOUT(4)

10 mA < IOUT < 1.5 A 0.33 %/A10 mA < IOUT < 1.5 A 2 3.5

Ground pin current in normal TJ = 25°CIGND mAoperation mode10 mA < IOUT < 1.5 A 4.5VEN < VIL(EN), TJ = 25°C 0.025 0.125

IDISABLED Ground pin current µAVEN < VIL(EN) 15

IOUT(PK)GN Peak output current VOUT ≥ VOUT(NOM) – 5% 3.6 AD

ISC VOUT = 0 V, TJ = 25°C 3.7 AShort-circuit current

VOUT = 0 V 2ENABLE INPUT (LP38502 Only)VIH(EN) Enable logic high VOUT = ON 1.4 VVIL(EN) Enable logic low VOUT = OFF 0.65 V

Time from VEN < VIL(EN) to VOUT =td(off) Turnoff delay OFF 25 µs

ILOAD = 1.5 ATime from VEN >VIH(EN) to VOUT = ONtd(on) Turnon delay 25 µsILOAD = 1.5A

IIH(EN) Enable pin high current VEN = VIN 1 nAIIL(EN) Enable pin low current VEN = 0 V 0.1

(1) The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are includedin the adjust voltage tolerance specification.

(2) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Forany output voltage less than 2.5V, the minimum VIN operating voltage is the limiting factor.

(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.(4) Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in the load current.





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Electrical Characteristics (continued)Unless otherwise specified VIN = 3.3 V, IOUT = 10 mA, CIN = 10 μF, COUT = 10 μF, VEN = VIN, VOUT = 1.8 V. Minimum andmaximum limits apply over the junction temperature (TJ) range of –40°C to +125°C and are specified through test, design, orstatistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for referencepurposes only.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITAC PARAMETERS

VIN = 3 V, IOUT = 1.5 A, ƒ = 120 Hz 58PSRR Ripple rejection dB

VIN = 3 V, IOUT = 1.5 A, ƒ = 1 kHz 56ρn(l/f) Output noise density ƒ = 120 Hz, COUT = 10 µF CER 1 µV/√Hz

BW = 100 Hz – 100 kHzen Output noise voltage 100 µV(rms)COUT = 10 µF CERTHERMALSTSD Thermal shutdown TJ rising 170 — °CΔTSD Thermal shutdown hysteresis TJ falling from TSD 10 — °C





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6.6 Typical CharacteristicsUnless otherwise specified: TJ = 25°C, VIN = 2.7 V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA, VOUT = 1.8 V.

Figure 2. Noise DensityFigure 1. Noise Density

Figure 4. IGND(OFF) vs TemperatureFigure 3. IGND vs Load Current

Figure 5. VADJ vs Temperature Figure 6. Dropout Voltage vs Load Current





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Typical Characteristics (continued)Unless otherwise specified: TJ = 25°C, VIN = 2.7 V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA, VOUT = 1.8 V.

Figure 7. VEN vs Temperature Figure 8. Turnon Characteristics

Figure 9. PSRR





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7 Detailed Description

7.1 OverviewThe LP38500-ADJ and LP38502-ADJ are flex-cap and low-dropout adjustable regulators, the output voltage canbe set from 0.6 V to 5 V. Standard regulator features, such as overcurrent and overtemperature protections, arealso included.

The LP38500-ADJ and LP38502-ADJ contains several features:

Stable with any type of output capacitor

Fast load transient response

Disable Mode (LP38502-ADJ only)

7.2 Functional Block Diagrams

Figure 10. LP38500-ADJ DDPAK/TO-263 Block Diagram

Figure 11. LP38502-ADJ DDPAK/TO-263 Block Diagram

Figure 12. LP38500-ADJ WSON Block Diagram





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Functional Block Diagrams (continued)

Figure 13. LP38502-ADJ WSON Block Diagram

7.3 Feature Description

7.3.1 Stability And Phase MarginAny regulator which operates using a feedback loop must be compensated in such a way as to ensure adequatephase margin, which is defined as the difference between the phase shift and –180 degrees at the frequencywhere the loop gain crosses unity (0 dB). For most LDO regulators, the ESR of the output capacitor is required tocreate a zero to add enough phase lead to ensure stable operation. The LP38500-ADJ and LP38502-ADJ eachhave a unique internal compensation circuit which maintains phase margin regardless of the ESR of the outputcapacitor, so any type of capacitor may be used.

Figure 14 shows the gain/phase plot of the LP38500-ADJ and LP38502-ADJ with an output of 1.2 V, a 10-µFceramic output capacitor, delivering 1.5 A of load current. It can be seen that the unity-gain crossover occurs at150 kHz, and the phase margin is about 40° (which is very stable).

Figure 14. Gain-Bandwidth Plot for 1.5-A Load

Figure 15 shows the gain and phase with no external load. In this case, the only load is provided by the gainsetting resistors (about 12 kΩ total in this test). It is immediately obvious that the unity-gain frequency issignificantly lower (dropping to about 500 Hz), at which point the phase margin is 125°.





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PL OUT

1F

2 R C

u S u u


Feature Description (continued)

Figure 15. Gain-Bandwidth Plot for No Load

The reduction in unity-gain bandwidth as load current is reduced is normal for any LDO regulator using a P-FETor PNP pass transistor, because they have a pole in the loop gain function given by:

(1)

This illustrates how the pole goes to the highest frequency when RL is minimum value (maximum load current).In general, LDOs have maximum bandwidth (and lowest phase margin) at full load current. In the case of theLP38500-ADJ or LP38502-ADJ, it can be seen that it has good phase margin even when using ceramiccapacitors with ESR values of only a few mΩ.

7.3.2 Load Transient ResponseLoad transient response is defined as the change in regulated output voltage which occurs as a result of achange in load current. Many applications have loads which vary, and the control loop of the voltage regulatormust adjust the current in the pass FET transistor in response to load current changes. For this reason,regulators with wider bandwidths often have better transient response.

The LP38500-ADJ and LP38502-ADJ employs an internal feed-forward design which makes the load transientresponse much faster than would be predicted simply by loop speed: this feedforward means any voltagechanges appearing on the output are coupled through to the high-speed driver used to control the gate of thepass FET along a signal path using very fast FET devices. Because of this, the pass transistor’s current canchange very quickly.

Figure 15 shows the output voltage load transient which occurs on a 1.8-V output when the load changes from0.1 A to 1.5 A at an average slew rate of 0.5 A/µs. As shown, the peak output voltage change from nominal isabout 40 mV, which is about 2.2%.

Figure 16. Load Transient Response





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Feature Description (continued)In cases where extremely fast load changes occur, the output capacitance may have to be increased. For fastchanging loads, the internal parasitics of ESR (equivalent series resistance) and ESL (equivalent seriesinductance) degrade the capacitor’s ability to source current quickly to the load. The best capacitor types fortransient performance are (in order):1. Multilayer Ceramic: with the lowest values of ESR and ESL, they can have ESR values in the range of a few

mΩ. Disadvantage: capacitance values above about 22 µF significantly increase in cost.2. Low-ESR Aluminum Electrolytics: these are aluminum types (like OSCON) with a special electrolyte which

provides extremely low ESR values, and are the closest to ceramic performance while still providing largeamounts of capacitance. These are cheaper (by capacitance) than ceramic.

3. Solid tantalum: can provide several hundred µF of capacitance, transient performance is slightly worse thanOSCON type capacitors, cheaper than ceramic in large values.

4. General purpose aluminum electrolytics: cheap and provide a lot of capacitance, but give the worstperformance.

In general, managing load transients is done by paralleling ceramic capacitance with a larger bulk capacitance.In this way, the ceramic can source current during the rapidly changing edge and the bulk capacitor can supportthe load current after the first initial spike in current.

7.3.3 Dropout VoltageThe dropout voltage of a regulator is defined as the input-to-output differential required by the regulator to keepthe output voltage within 2% of the nominal value. For CMOS LDOs, the dropout voltage is the product of theload current and the RDS(on) of the internal MOSFET pass element.

Since the output voltage is beginning to “drop out” of regulation when it drops by 2%, electrical performance ofthe device will be reduced compared to the values listed in the Electrical Characteristics table for someparameters (line and load regulation and PSRR would be affected).

7.3.4 Reverse Current PathThe internal MOSFET pass element in the LP38500-ADJ and LP38502-ADJ has an inherent parasitic diode.During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reversebiased. However, if the output is pulled above the input in an application, then current flows from the output tothe input as the parasitic diode gets forward biased. The output can be pulled above the input as long as thecurrent in the parasitic diode is limited to 200-mA continuous and 1-A peak. The regulator output pin should notbe taken below ground potential. If the LP38500-ADJ and LP38502-ADJ is used in a dual-supply system wherethe regulator load is returned to a negative supply, the output must be diode-clamped to ground.

7.4 Device Functional Modes

7.4.1 Short-Circuit ProtectionThe LP38500-ADJ and LP38502-ADJ contain internal current limiting which will reduce output current to a safevalue if the output is overloaded or shorted. Depending upon the value of VIN, thermal limiting may also becomeactive as the average power dissipated causes the die temperature to increase to the limit value (about 170°C).The hysteresis of the thermal shutdown circuitry can result in a “cyclic” behavior on the output as the dietemperature heats and cools.

7.4.2 Enable Operation (LP38502-ADJ Only)The Enable pin (EN) must be actively terminated by either a 10-kΩ pull-up resistor to VIN, or a driver whichactively pulls high and low (such as a CMOS rail to rail comparator). If active drive is used, the pull-up resistor isnot required. This pin must be tied to VIN if not used (it must not be left floating).





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8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe LP38500-ADJ and LP38502-ADJ devices can provide 1.5-A output current with 2.7-V to 5.5-V input voltage.These ultra-low-dropout linear regulators respond very quickly to step changes in load, making them suitable forlow-voltage microprocessor applications. Input and output capacitors of at least 10 µF are required.

8.2 Typical Applications

Figure 17. Typical Circuit (LP38500)Figure 18. Typical Circuit (LP38502)

8.2.1 Design RequirementsFor LP3850x-ADJ typical applications, use the parameters listed in Table 1 as the input parameters.

Table 1. Design ParametersDESIGN PARAMETERS VALUE

Input voltage 2.7 V to 5.5 VOutput voltage 0.6 V to 5 V (adjustable)Output current 1.5 A (maximum)Input capacitor 10 µF (minimum)

Output capacitor 10 uF (minimum)

8.2.2 Detailed Design Procedure

8.2.2.1 External CapacitorsThe LP38500-ADJ and LP38502-ADJ require that at least 10-µF (±20%) capacitors be used at the input andoutput pins located within one cm of the device. Larger capacitors may be used without limit on size for both CINand COUT. Capacitor tolerances such as temperature variation and voltage loading effects must be consideredwhen selecting capacitors to ensure that they will provide the minimum required amount of capacitance under alloperating conditions for the application.

In general, ceramic capacitors are best for noise bypassing and transient response because of their ultra lowESR. It must be noted that if ceramics are used, only the types with X5R or X7R dielectric ratings should be used(never Z5U or Y5F). Capacitors which have the Z5U or Y5F characteristics will see a drop in capacitance of asmuch as 50% if their temperature increases from 25°C to 85°C. In addition, the capacitance drops significantlywith applied voltage: a typical Z5U or Y5F capacitor can lose as much as 60% of its rated capacitance if only halfof the rated voltage is applied to it. For these reasons, only X5R and X7R ceramics should be used.





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8.2.2.2 Input CapacitorAll linear regulators can be affected by the source impedance of the voltage which is connected to the input. Ifthe source impedance is too high, the reactive component of the source may affect the control loop’s phasemargin. To ensure proper loop operation, the ESR of the capacitor used for CIN must not exceed 0.5 Ω. Anygood quality ceramic capacitor will meet this requirement, as well as many good quality tantalums. Aluminumelectrolytic capacitors may also work, but can possibly have an ESR which increases significantly at coldtemperatures. If the ESR of the input capacitor may exceed 0.5 Ω, it is recommended that a 2.2-µF ceramiccapacitor be used in parallel, as this will assure stable loop operation.

8.2.2.3 Output CapacitorAny type of capacitor may be used for COUT, with no limitations on minimum or maximum ESR, as long as theminimum amount of capacitance is present. The amount of capacitance can be increased without limit.Increasing the size of COUT typically will give improved load transient response.

8.2.2.4 Setting The Output VoltageThe output voltage of the LP38500/2-ADJ can be set to any value between 0.6V and 5V using two externalresistors shown as R1 and R2 in Figure 19.

Figure 19. Setting Output Voltage

The value of R2 should always be less than or equal to 10 kΩ for good loop compensation. R1 can be selectedfor a given VOUT using the following formula:

VOUT = VADJ (1 + R1/R2) + IADJ (R1)

where• VADJ is the adjust pin voltage• IADJ is the bias current flowing into the adjust pin (2)

8.2.2.5 RFI/EMI SusceptibilityRadio Frequency Interference (RFI) and Electro-Magnetic Interference (EMI) can degrade any integrated circuit'sperformance because of the small dimensions of the geometries inside the device. In applications where circuitsources are present which generate signals with significant high frequency energy content (> 1 MHz), care mustbe taken to ensure that this does not affect the device regulator.

If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comesfrom the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of thedevice to reduce the amount of EMI conducted into the device.

If the LP38500, LP38502-ADJ output is connected to a load which switches at high speed (such as a clock), thehigh-frequency current pulses required by the load must be supplied by the capacitors on the device output.Since the bandwidth of the regulator loop is less than 300 kHz, the control circuitry cannot respond to loadchanges above that frequency. This means the effective output impedance of the device at frequencies above300 kHz is determined only by the output capacitor(s). Ceramic capacitors provide the best performance in thistype of application.





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In applications where the load is switching at high speed, the output of the device may need RF isolation fromthe load. In such cases, it is recommended that some inductance be placed between the output capacitor andthe load, and good RF bypass capacitors be placed directly across the load. PCB layout is also critical in highnoise environments, since RFI/EMI is easily radiated directly into PC traces. Noisy circuitry should be isolatedfrom clean circuits where possible, and grounded through a separate path. At MHz frequencies, ground planesbegin to look inductive and RFI/EMI can cause ground bounce across the ground plane. In multi-layer PC Boardapplications, care should be taken in layout so that noisy power and ground planes do not radiate directly intoadjacent layers which carry analog power and ground.

8.2.2.6 Output NoiseNoise is specified in two ways:• Spot noise or output noise density is the RMS sum of all noise sources, measured at the regulator output, at

a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on a curve as afunction of frequency.

• Total output noise or broadband noise is the RMS sum of spot noise over a specified bandwidth, usuallyseveral decades of frequencies.

Spot noise is measured in units µV/√Hz or nV/√Hz and total output noise is measured in µV(rms). The primarysource of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low-frequency component and a high frequency component, which depend strongly on the silicon area and quiescentcurrent.

Noise can generally be reduced in two ways: increase the transistor area or increase the reference current.However, enlarging the transistors will increase die size, and increasing the reference current means higher totalsupply current (ground pin current).

8.2.3 Application Curves

Figure 21. Turnon TimeFigure 20. Turnon Time





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9 Power Supply RecommendationsThe LP38500-ADJ and LP38502-ADJ devices are designed to operate from an input voltage supply rangebetween 2.7 V and 5.5 V. The input voltage range provides adequate headroom in order for the device to have aregulated output. This input supply must be well regulated. An input capacitor of at least 10 μF is required.

9.1 Power Dissipation/HeatsinkingThe maximum power dissipation (PD(MAX)) of the LP38500-ADJ and LP38502-ADJ is limited by the maximumjunction temperature of 125°C, along with the maximum ambient temperature (TA(MAX)) of the application, and thethermal resistance (RθJA) of the package. Under all possible conditions, the junction temperature (TJ) must bewithin the range specified in the Recommended Operating Conditions. The total power dissipation of the deviceis given by:

PD = ((VIN − VOUT) × IOUT) + (VIN × IGND)

where• IGND is the operating ground current of the device (specified under Electrical Characteristics) (3)

The maximum allowable junction temperature rise (ΔTJ) depends on the maximum expected ambienttemperature (TA(MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)):

ΔTJ = TJ(MAX)− TA(MAX) (4)

The maximum allowable value for junction-to-ambient thermal resistance, RθJA, can be calculated using theformula:

RθJA = ΔTJ / PD(MAX) (5)

The LP38500-ADJ and LP38502-ADJ are available in the DDPAK/TO-263, TO-263, and WSON packages. Thethermal resistance depends on the amount of copper area allocated to heat transfer.





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Ground

INOUT

N/C

Input Capacitor

Output Capacitor

ADJ

R2

R1


10 Layout

10.1 Layout Guidelines

10.1.1 Printed Circuit Board LayoutGood layout practices will minimize voltage error and prevent instability which can result from ground loops. Theinput and output capacitors should be directly connected to the device pins with short traces that have no othercurrent flowing in them (Kelvin connect).

The best way to do this is to place the capacitors very near the device and make connections directly to thedevice pins via short traces on the top layer of the PCB. The regulator’s ground pin should be connected throughvias to the internal or backside ground plane so that the regulator has a single point ground.

The external resistors which set the output voltage must also be located very near the device with all connectionsdirectly tied via short traces to the pins of the device (Kelvin connect). Do not connect the resistive divider to theload point or DC error will be induced.

10.2 Layout Examples

Figure 22. LP38500-ADJ TO-263 Layout (LP38500)





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Ground

VOUT

VIN

Input Capacitor

Output Capacitor

BYPASS

N/C

GROUND

IN OUT

SHUTDOWN

SENSE

ERROR

Error Pullup Resistor

VOUT

Ground

INOUT

EN

Input Capacitor

Output Capacitor

Pull-up Resistor

ADJ

R2

R1


Layout Examples (continued)

Figure 23. LP38502-ADJ TO-263 Layout

Figure 24. LP3850x WSON Layout

10.2.1 Heatsinking WSON PackageThe junction-to-ambient thermal resistance for the WSON package is dependent on how much PCB copper ispresent to conduct heat away from the device. The LP38502SD-ADJ evaluation board (980600046-100) wastested and gave a result of about 52.5°C/W with a power dissipation of 1 W and no external airflow. Thisevaluation board is a two layer board using two ounce copper, and the copper area on topside for heatsinking isapproximately two square inches. Multiple vias under the DAP also thermally connect to the backside layer whichhas about three square inches of copper dedicated to heatsinking.

With four thermal vias directly under the DAP to the first copper plane, the modeling predicts a RθJA of 52.5°C/W.

Adding a dog-bone copper area with four additional thermal vias in the dog-bone area to the first copper planecan improve RθJA to 45°C/W.





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Layout Examples (continued)See Application Note AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages(SNVA183) for additional thermal considerations for printed circuit board layouts.





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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related DocumentationApplication Note AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages(SNVA183).

11.1.2 Related LinksTable 2 lists quick access links. Categories include technical documents, support and community resources,tools and software, and quick access to sample or buy.

Table 2. Related LinksTECHNICAL TOOLS & SUPPORT &PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

LP38500-ADJ Click here Click here Click here Click here Click hereLP38502-ADJ Click here Click here Click here Click here Click here

11.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.3 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.5 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.





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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

LP38500ASD-ADJ/NOPB ACTIVE WSON NGS 8 1000 RoHS & Green SN Level-1-260C-UNLIM LKUA

LP38500ASDX-ADJ/NOPB ACTIVE WSON NGS 8 4500 RoHS & Green SN Level-1-260C-UNLIM LKUA

LP38500ATJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 RoHS & Green SN Level-1-260C-UNLIM LP38500ATJ-ADJ

LP38500SD-ADJ/NOPB ACTIVE WSON NGS 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LKUB

LP38500SDE-ADJ/NOPB ACTIVE WSON NGS 8 250 RoHS & Green SN Level-1-260C-UNLIM LKUB

LP38500SDX-ADJ/NOPB ACTIVE WSON NGS 8 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LKUB

LP38500TJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LP38500TJ-ADJ

LP38500TS-ADJ/NOPB ACTIVE DDPAK/TO-263

KTT 5 45 RoHS-Exempt& Green

SN Level-3-245C-168 HR -40 to 125 LP38500TS-ADJ

LP38500TSX-ADJ/NOPB ACTIVE DDPAK/TO-263



LP38502ASD-ADJ/NOPB ACTIVE WSON NGS 8 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LKVA

LP38502ASDX-ADJ/NOPB ACTIVE WSON NGS 8 4500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LKVA

LP38502ATJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LP38502ATJ-ADJ

LP38502SD-ADJ/NOPB ACTIVE WSON NGS 8 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LKVB

LP38502SDE-ADJ/NOPB ACTIVE WSON NGS 8 250 RoHS & Green SN Level-1-260C-UNLIM LKVB

LP38502SDX-ADJ/NOPB ACTIVE WSON NGS 8 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LKVB

LP38502TJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LP38502TJ-ADJ

LP38502TS-ADJ/NOPB ACTIVE DDPAK/TO-263



LP38502TSX-ADJ/NOPB ACTIVE DDPAK/TO-263



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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

LP38500ASD-ADJ/NOPB WSON NGS 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1

LP38500ASDX-ADJ/NOPB

WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1

LP38500ATJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LP38500SD-ADJ/NOPB WSON NGS 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1

LP38500SDE-ADJ/NOPB WSON NGS 8 250 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1

LP38500SDX-ADJ/NOPB WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1

LP38500TJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LP38500TSX-ADJ/NOPB DDPAK/TO-263

KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2



LP38502ASDX-ADJ/NOPB

WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1

LP38502ATJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LP38502SD-ADJ/NOPB WSON NGS 8 1000 180.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1

LP38502SDE-ADJ/NOPB WSON NGS 8 250 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1

LP38502SDX-ADJ/NOPB WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1

LP38502TJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Mar-2022

Pack Materials-Page 1

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

LP38502TSX-ADJ/NOPB DDPAK/TO-263

KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP38500ASD-ADJ/NOPB WSON NGS 8 1000 208.0 191.0 35.0

LP38500ASDX-ADJ/NOPB WSON NGS 8 4500 367.0 367.0 35.0

LP38500ATJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0

LP38500SD-ADJ/NOPB WSON NGS 8 1000 208.0 191.0 35.0

LP38500SDE-ADJ/NOPB WSON NGS 8 250 208.0 191.0 35.0

LP38500SDX-ADJ/NOPB WSON NGS 8 4500 367.0 367.0 35.0

LP38500TJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0

LP38500TSX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0



LP38502ASDX-ADJ/NOPB WSON NGS 8 4500 367.0 367.0 35.0

LP38502ATJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0

LP38502SD-ADJ/NOPB WSON NGS 8 1000 200.0 183.0 25.0

LP38502SDE-ADJ/NOPB WSON NGS 8 250 208.0 191.0 35.0

LP38502SDX-ADJ/NOPB WSON NGS 8 4500 367.0 367.0 35.0




Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP38502TJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0

LP38502TSX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0




TUBE


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

LP38500TS-ADJ/NOPB KTT TO-263 5 45 502 25 8204.2 9.19

LP38502TS-ADJ/NOPB KTT TO-263 5 45 502 25 8204.2 9.19




MECHANICAL DATA

NDQ0005A

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TJ5A (Rev F)

MECHANICAL DATA

KTT0005B

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BOTTOM SIDE OF PACKAGE

TS5B (Rev D)

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PACKAGE OUTLINE

C

8X 0.30.2

1.5 0.1

8X 0.50.3

2X1.5

1.6 0.1

6X 0.5

0.80.7

0.050.00

B 3.12.9

A

2.62.4

(0.1) TYP

WSON - 0.8 mm max heightNGS0008CPLASTIC SMALL OUTLINE - NO LEAD

4214924/A 07/2018

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

1

4 5

8

PIN 1 ID 0.1 C A B0.05 C

THERMAL PADEXPOSED

9

SYMM

SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 5.000

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EXAMPLE BOARD LAYOUT

0.07 MINALL AROUND

0.07 MAXALL AROUND

(1.6)

6X (0.5)

(2.8)

8X (0.25)

8X (0.6)

(1.5)

(R0.05) TYP( 0.2) VIA

TYP

(0.5)


4214924/A 07/2018

SYMM

1

4 5

8

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:20X

9

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASKOPENINGSOLDER MASK

METAL UNDER

SOLDER MASKDEFINED

EXPOSED METAL

METALSOLDER MASKOPENING

SOLDER MASK DETAILS

NON SOLDER MASKDEFINED

(PREFERRED)

EXPOSED METAL

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EXAMPLE STENCIL DESIGN

8X (0.25)

8X (0.6)

6X (0.5)

(1.38)

(1.47)

(2.8)

(R0.05) TYP


4214924/A 07/2018

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 9:

82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:20X

SYMM

1

45

8

SYMM

METALTYP

9

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