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LabVIEWTM Real-Time 2: Architecting Embedded Systems Course Manual

Course Software Version 2012November 2012 EditionPart Number 325995B-01LabVIEW Real-Time 2 Course ManualCopyright 20102012 National Instruments Corporation. All rights reserved. Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.National Instruments respects the intellectual property of others, and we ask our users to do the same. NI software is protected by copyright and other intellectual property laws. Where NI software may be used to reproduce software or other materials belonging to others, you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction.

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TrademarksCVI, LabVIEW, National Instruments, NI, ni.com, the National Instruments corporate logo, and the Eagle logo are trademarks of National Instruments Corporation. Refer to the Trademark Information at ni.com/trademarks for other National Instruments trademarks.The mark LabWindows is used under a license from Microsoft Corporation. Windows is a registered trademark of Microsoft Corporation in the United States and other countries. Other product and company names mentioned herein are trademarks or trade names of their respective companies.Members of the National Instruments Alliance Partner Program are business entities independent from National Instruments and have no agency, partnership, or joint-venture relationship with National Instruments.

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Contents

Student GuideA. NI Certification .....................................................................................................vB. Course Description ...............................................................................................viC. What You Need to Get Started .............................................................................viD. Installing the Course Software..............................................................................viiE. Course Goals.........................................................................................................viiF. Course Conventions ..............................................................................................viii

Lesson 1Real-Time Application Design Flow

A. Analyzing Your Real-Time Application...............................................................1-2B. Real-Time Target Considerations .........................................................................1-6C. Host Considerations ..............................................................................................1-6

Lesson 2Documenting Your Design

A. Overview of Diagrams..........................................................................................2-2B. Creating a Communication Diagram ....................................................................2-2C. Common Real-Time System Diagrams ................................................................2-3D. Additional Documentation....................................................................................2-6

Lesson 3Real-Time Processes and Inter-Process Communication

A. Implementing Real-Time Processes .....................................................................3-2B. Avoid Shared Resources .......................................................................................3-6C. Inter-Process Data Communication ......................................................................3-8

Lesson 4Network Communication

A. Network Communication Overview.....................................................................4-2B. Selecting a Data Transfer Mechanism ..................................................................4-2C. Data Transfer Mechanisms for Network Communication....................................4-2

Lesson 5Managing Memory and Monitoring System Health

A. Impacts of Memory Usage....................................................................................5-2B. Memory Pre-Allocation ........................................................................................5-3C. Dynamic Memory Allocation ...............................................................................5-5D. System Monitoring ...............................................................................................5-8Sa

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Lesson 6Reliability

A. Reliability Overview.............................................................................................6-2B. Safe Shutdown ......................................................................................................6-2C. Error Handling ......................................................................................................6-3D. Watchdog ..............................................................................................................6-6E. Redundancy ..........................................................................................................6-8

Lesson 7Debugging, Benchmarking, and Testing

A. Debugging.............................................................................................................7-2B. Benchmark Performance.......................................................................................7-3C. Testing ..................................................................................................................7-15

Lesson 8Deploying and Replicating

A. LabVIEW IDE Deployment Method....................................................................8-2B. Targeting Imaging Deployment Method ..............................................................8-2C. (Optional) FPGA Deployment..............................................................................8-3

Appendix AAdditional Information and Resources

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3Real-Time Processes and Inter-Process Communication

This lesson describes different methods of sharing data between tasks on the RT target. You will learn the appropriate use case for each method.

TopicsA. Implementing Real-Time ProcessesB. Avoid Shared ResourcesC. Inter-Process Data Communication

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Lesson 3 Real-Time Processes and Inter-Process Communication

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A. Implementing Real-Time ProcessesIn the LabVIEW Real-Time 1 course, you learned how to separate deterministic and non-deterministic processes. You learned to place your deterministic process in a Timed Loop and your non-deterministic processes in While Loops in normal priority VIs.

Timed Loop Advanced FunctionalityMonitoring and Debugging FunctionalityYou can use the Previous IterationFinished Late terminal on the Left Data node for the following: Display running count of how many loop iterations did not complete before the expected

deadline, as shown in Figure 3-1. If a critical loop finishes late, send application into a recovery or safe shutdown mode.

Figure 3-1. Using the Finished Late Terminal

You can use the Previous IterationFinished Late terminal on the Left Data node for the following: Monitor a running average of loop iteration durations, as shown in Figure 3-2. If loop finishes late, you can use the iteration duration to calculate exactly how late.

Figure 3-2. Using the Iteration Duration terminalSam

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Timed Loop Assigning ProcessorsLabVIEW is compatible with multi-processor and multi-core machines. When you execute LabVIEW code in a multi-processor environment, LabVIEW separates the code into threads and assigns threads to available processors. This makes efficient use of the processors because it prevents a processor from waiting on a particular thread. You can override the default processor assignment in LabVIEW by using a Timed Loop. Timed Loops allow you to assign a core or processor to each Timed Loop by specifying the processor number. Manually assigning processors can help to improve the determinism of time-critical code by causing it to execute on a dedicated processor while non-critical code shares the other processor(s). Manually assigning processors can also help to improve performance in some systems because threads do not need to be swapped on and off the processor as often. However, manually assigning processors generally uses the processors less efficiently, because a processor can be idle waiting for a particular thread while other threads are ready to execute.

Timed Loop ModesOccasionally, an iteration of a Timed Loop might execute later than the time you specified. The mode of the Timed Loop determines how the loop handles any late executions. Use the options in the Action on Late Iterations section of the Configure Timed Loop dialog box or the Mode input of the Input node to specify the mode a Timed Loop uses to handle the late execution of a Timed Loop iteration.

You can handle the late execution of a Timed Loop in the following ways: The LabVIEW Timed Loop Scheduler can align the execution with the original established

schedule. The LabVIEW Timed Loop Scheduler can define a new schedule that starts at the current time. The Timed Loop can process the missed iterations. The Timed Loop can skip any missed iterations.

For example, if you set a Timed Loop with a period of 100 ms and an offset of 30 ms, you expect the first loop iteration to execute 30 ms after the first timing source starts running and in multiples of 100 ms after that at 130 ms, 230 ms, 330 ms, and so on. However, the first execution of the Timed Loop might occur after 240 ms have elapsed. Because other Timed Loops or hardware devices might already be running at the schedule you specified, you might want to align the late Timed Loop with the already running global schedule, which means the Timed Loop should align itself as quickly as possible with the schedule you specified. In this case, the next Timed Loop iteration would run at 330 ms and continue to run in multiples of 100 at 430 ms, 530 ms, and so on. If aligning the Timed Loop with other Timed Loops or other hardware devices is not important, the Timed Loop can run immediately and use the current time as its actual offset. In this case, the subsequent loop iterations would run at 240 ms, 340 ms, 440 ms, and so on.

If the Timed Loop is late, it might miss data other Timed Loops or hardware devices generate. For example, if the Timed Loop missed two iterations and some of the data from the current period, a buffer could hold the data from the missed iterations. You might want the Timed Loop to process the missed data before it aligns with the schedule you specified. However, a Timed Loop that

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processes the missed iterations causes jitter. If you do not want to process the missed data, the Timed Loop can ignore the older data in the buffer that the loop iterations missed and process only the latest data, such as the data available at the next period and the subsequent iterations.

Timed Loop Changing Input Node Values DynamicallyUse the Left Data node to acquire information about the execution of the Timed Loop, such as if the timing source executed late or if the offset or period values changed. You can wire the values the Left Data node returns to the Right Data node or to nodes in the subdiagram within the Timed Loop.

Use the Right Data node to dynamically change the input values of the Timed Loop on the next loop iteration, as shown in Figure 3-3.

Figure 3-3. Changing Input Node Values Dynamically

If you dynamically change the offset of the Timed Loop by wiring a value to the Offset input of the Right Data node, you also must specify a mode with the Mode input of the Right Data node. To set the mode, right-click the Mode input of the Right Data node and select CreateConstant or CreateControl to create an enumerated constant or control you can use to select a mode.

Timed Loop Aborting ExecutionUse the Stop Timed Structure VI to abort the execution of a Timed Loop programmatically. Specify the name of the Timed Loop you want to abort by wiring that name in a string constant or control to the name input of the Stop Timed Structure VI.

Synchronizing Timed Loop StartsUse the Synchronize Timed Structure Starts VI to ensure all Timed Loops on a block diagram use the same start time and the same timing source. For example, you might have two Timed Loops and you want to ensure that they execute on the same schedule relative to each other. You might want the first Timed Loop to execute first and generate data, then have the second Timed Loop process that data when the Timed Loop execution finishes. To ensure that both Timed Loops use the same start time as the basis for their execution, you create a Timed Loop group by wiring a name for the group to the synchronization group name input and wiring an array of Timed Loop names to the structure names input.

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In Figure 3-4, the Synchronize Timed Structure Starts VI ensures both loops activate at the same time. However, because the bottom loop has an offset of 100, the bottom loop will always start 100 ms after the top loop starts. This is a method for ensuring the order in which multiple Timed Loops start.

Figure 3-4. Synchronize Timed Loop Starts with Offset

Software Defined Timing ResourcesYou can create a software-triggered timing source to trigger a timed structure based on a software-defined event. Use the Create Timing Source VI to create a software-triggered timing source. Use the Fire Software-Triggered Timing Source VI to programmatically trigger a Timed Loop controlled by a software-triggered timing source.

You can use a software-triggered timing source as an RT-compatible event handler or to notify a consumer Timed Loop when new data becomes available in a producer-consumer application. You also can use software-triggered timing sources for discrete event simulation. Use the number of ticks input of the Fire Software-Triggered Timing Source VI to specify the number of ticks that elapse between each discrete event. The internal tick counter of the timed structure advances by number of ticks when the Fire Software-Triggered Timing Source VI executes. If the internal tick counter jumps past one or more Timed Loop periods, the Timed Loop regards those periods as missed periods. If you want to trigger multiple Timed Loop iterations with a single call to the Fire Software-Triggered Timing Source VI, you can remove the checkmark from the Discard missed periods checkbox in the Configure Timed Loop dialog box.Sa

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Figure 3-5. Software Defined Timing Source Triggering a Timed Loop

While Loop Inside Timed Sequence Structure OptimizationIf you are only using Timed Loop for its priority features and not timing features, you can use a While Loop inside a Timed Sequence structure instead. In this case, the Timed Sequence structure provides the priority features, and the While Loop executes continuously inside the Timed Sequence structure. This method is more optimized because it uses less overhead than a Timed Loop.

Figure 3-6. While Loop Inside Timed Sequence Structure Optimization

B. Avoid Shared ResourcesIn LabVIEW, two or more VIs might need to share resources. Shared resources can cause jitter and prevent applications from taking advantage of multiple CPUs. Certain data structures, driver libraries, and variables can only be accessed serially, one process at a time. A simple example of a shared resource common to all programming languages is the global variable. You cannot access global variables simultaneously from multiple processes. Therefore, compilers automatically

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protect the global variable as a shared resource while one process needs to access it. Meanwhile, if a second process tries to access the global variable while it is protected, the second process must wait until the first process finishes with the global variable. Understanding shared resources and how to identify them is an important skill when programming real-time applications.

LabVIEW Real-Time shared resources include the following: Global variables LabVIEW memory manager Single-threaded DLLs Shared variables Non-reentrant subVIs Networking code (TCP/IP, UDP, VI Server)* File I/O* Semaphore VIs*

Note The operations marked with an asterisk are inherently non-deterministic. Never use them inside a time-critical priority loop if you are attempting to achieve real-time performance.

Avoid Shared Resources PrioritiesImagine a scenario where there is a shared resource, such as a global variable, that is shared by two VIsone set to normal priority and one set to time-critical priority.

The RTOS uses priority inheritance to resolve the priority inversion as quickly as possible using the following procedure: Allow the lower priority thread to temporarily inherit the time-critical priority setting long

enough to finish using the shared resource and release the mutex. After releasing the mutex, the lower priority thread resumes its normal priority setting and is

taken off the processor. The time-critical priority thread proceeds to use the resource, that is, access the global variable.

The priority inversion increases software jitter in the time-critical priority thread. The jitter induced by a mutexed global variable is small compared to the jitter induced by a mutexed LabVIEW memory manager. Unlike accessing global variables, performing memory allocations is unbounded in time and can introduce a broad range of software jitter while parallel operations try to allocate blocks of memory in a wide variety of sizes. The larger the block of memory to be allocated, the longer the priority inheritance takes to resolve the priority inversion.Sa

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Shared Resources SubVIsSharing subVIs can cause priority inversions the same as global variables. You can set a VI to subroutine priority and select the Skip Subroutine Call If Busy option to skip that VI within time-critical code and avoid software jitter that occurs from a priority inversion.

However, if you run unrelated parallel processes that call the same VI, you can configure the VI for reentrant execution. Use a reentrant VI to allow multiple instances of a VI to execute in parallel with distinct and separate data storage. LabVIEW RT can call multiple instances of a reentrant VI simultaneously. Because reentrant VIs use their own data space, you cannot use them to share or communicate data between threads. You should use reentrancy only when you must simultaneously run multiple instances of a VI within unrelated processes that do not need to share data within the reentrant VI.

To make a VI reentrant, select FileVI Properties, select Execution in the VI Properties dialog box and enable the Preallocated clone reentrant execution option.

Shared Resources Memory ManagementWhen a VI allocates memory, the VI accesses the LabVIEW memory manager. The LabVIEW memory manager allocates memory for data storage. The LabVIEW memory manager is a shared resource and might be locked by a mutex for up to several milliseconds. Allocating memory within a deterministic VI can affect the determinism of the VI.

If you allow LabVIEW to dynamically allocate memory at run time, your application could suffer from software jitter for the following reasons: The memory manager may already be mutexed, causing a shared resource conflict. If the memory manager is immediately available, allocating memory is non-deterministic

because there is no upper bound on the execution time of the memory allocation.

C. Inter-Process Data CommunicationThis section reviews inter-process communication methods discussed in the LabVIEW Real-Time1 course and also discusses new additional inter-process communication methods.

Review Single-Process Shared Variables with the RT FIFO EnabledUse single-process shared variables to share data between two locations in a block diagram or between VIs running on an RT target. Right-click an RT target in the Project Explorer window and select NewVariable from the shortcut menu to open the Shared Variable Properties dialog box, which you can use to create a single-process shared variable.

The Real-Time Module adds real-time FIFO (first in, first out) buffer capability to the shared variable. By enabling the real-time FIFO of a shared variable, you can share data without affecting the determinism of VIs running on an RT target. From the Real-Time FIFO page of the Shared

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Variable Properties dialog box, enable the Enable Real-Time FIFO checkbox to enable the real-time FIFO of a shared variable.

Single-process shared variables provide a communication method that is easy to use and deterministic when you enable the Real-Time FIFO.

Note If you enable the Real-Time FIFO on a shared variable of waveform datatype, the variant element of the waveform does not transfer because variants are variable-sized and therefore incompatible with the Real-Time FIFO.

Review QueuesTo share buffered data between non-deterministic loops, you can use the Queue functions. The Queue API consists of a full-featured set of functions you can use to programmatically create, read from, write to, and get the status of a multiple-element FIFO. Unlike shared variables with the RT FIFO option enabled and RT FIFO functions, queues are compatible with data types of variable size such as strings and variants.

The Asynchronous Message Communication (AMC) Reference Library is a general purpose LabVIEW API developed by the NI Systems Engineering group for sending messages between processes on a local target or on different targets. The inter-process communication in this API is based on queues. Refer to the Asynchronous Message Communication (AMC) Reference Library document on ni.com for download and documentation.

RT FIFO FunctionsUse the Real-Time FIFO functions to share data between VIs running on an RT target. An RT FIFO acts like a fixed-sized queue, where the first value you write to the FIFO is the first value that you can read from the FIFO. RT FIFOs and LabVIEW Queues both transfer data from one VI to another. However, unlike a Queue function, an RT FIFO ensures deterministic behavior by imposing a size restriction on the data you share and preallocating memory for the data. You must define the number and size of the RT FIFO elements and ensure that you do not attempt to read and write data of different sizes. Both a reader and writer can access the data in an RT FIFO at the same time, allowing RT FIFOs to work safely from within a deterministic loop.

Because of the fixed-size restriction, an RT FIFO can be a lossy communication method. If the RT FIFO does not have empty elements, this function waits for an amount of time equal to the value of timeout in ms for an element to become available. If an empty element does not become available before the value of timeout in ms expires and the overwrite on timeout input is TRUE, this function overwrites the oldest element in the RT FIFO and returns TRUE in the timed out? output.

A larger FIFO gives the normal priority loop more time to catch up if it falls behind, which can help avoid FIFO overwrites. However, setting a FIFO too large wastes memory.

Use the RT FIFO Create function to create a new FIFO or to create a reference to a FIFO that you previously created. Use the RT FIFO Read and RT FIFO Write functions to read and write data to

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the FIFO. Use the RT FIFO Delete function to delete a reference to an RT FIFO and release the memory allocated to the FIFO on the RT target.

Note If you use a Real-Time FIFO to transfer waveform data, the variant element of the waveform does not transfer because variants are variable-sized, and therefore incompatible with the Real-Time FIFO.

Using RT FIFO FunctionsUse the RT FIFO Create function to create a new FIFO or open a reference to a FIFO that you previously created. Use the RT FIFO Read and RT FIFO Write functions to read and write data to the FIFO. Use the RT FIFO Delete function to delete a reference to an RT FIFO and release the memory allocated to the FIFO on the RT target. Refer to the RT FIFO Functions topic in the LabVIEW Help for more information about the RT FIFO functions and the data types supported by the RT FIFO functions.

Defining Read and Write Modes for Real-Time FIFOsAn RT FIFO function can wait until an empty slot becomes available for a write operation or wait until a value is available for a read operation. You can specify a read and write mode for an RT FIFO that defines the way you read a value from an empty FIFO or write a value to a FIFO that does not have an empty slot. You can specify one of the following modes for reads and writes on the r/w modes input of the RT FIFO Create function: PollingUse this mode to optimize the throughput performance of read and write operations.

The polling mode continually polls the FIFO for new data or an open slot. The polling mode responds quicker than the blocking mode to new data or new empty slots, but requires more CPU overhead. Use the timeout in ms input of the RT FIFO Read or RT FIFO Write function to specify the amount of time that a write operation should poll for an empty slot or the amount of time a read operation should poll for new data. You also can use the overwrite on timeout input of the RT FIFO Write function to specify whether to overwrite the oldest value in the RT FIFO when the value of the timeout in ms input expires.

BlockingUse this mode to optimize the utilization of the CPU during read and write operations. The blocking mode allows the thread of the VI to sleep while it waits, allowing other tasks in the system to execute. Use the timeout in ms input of the RT FIFO Read or RT FIFO Write function to specify an amount of time a read operation can wait for a new value or an amount of time a write operation can wait for an empty slot. You also can use the overwrite on timeout input of the RT FIFO Write function to specify whether to overwrite the oldest value in the RT FIFO when the value of the timeout in ms input expires.

Note If you use the RT FIFO Create function to return a reference to an existing RT FIFO, the reference uses the read and write mode of the existing FIFO and ignores the modes specified with read/write modes.Sa

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Static versus Dynamic ConfigurationShared variables are configured statically. This means that the properties of a shared variable are defined through interactive dialog boxes as you write your application. For dynamically configured entities such as a Real-Time FIFO, properties are defined at run-time.

Static configuration simplifies programming and conserves space on the block diagram because you do not need to create controls and constants for each configuration option. Shared variables do not require reference wires, thus keeping the block diagram cleaner. In general, you must know the value of all variable properties before running the VI. This means that user input or acquired data cannot determine the values of properties. You can configure some shared variable properties dynamically through VI Server calls, but this requires significant programming.

Use the dynamic configuration capability of the RT FIFO functions to specify configuration settings as the program runs. For example, you can set the size of the RT FIFO based on user input or by calculating loop frequencies. You also can destroy and recreate an RT FIFO with new properties as a program runs. For example, if overflow errors occur consistently you can destroy the RT FIFO and create a new, larger RT FIFO. The ability to create and destroy the RT FIFO helps manage memory in systems where memory is limited. Dynamic configuration also makes it easier to determine the properties of the RT FIFO by inspecting the block diagram.

Choosing Your RT FIFO MethodConsider the following characteristics of shared variables and RT FIFO functions when choosing which RT FIFO method to use. Shared variables store the timestamp of each piece of data they receive, making write

operations slightly slower than the low-level FIFO functions. You can change shared variable FIFOs to other shared-variable types. For example, without

any significant changes to the block diagram code, you can change a single-process shared variable FIFO to a network-published shared variable FIFO to communicate with the host.

For small applications, single-process shared variables with the RT FIFO enabled are a good choice for inter-task communication. However, to create a scalable architecture for large applications, use the RT FIFO functions instead.

When you need a scalable inter-task communication architecture for a large application, use the RT FIFO Create function to create RT FIFOs programmatically. For example, you can use the RT FIFO Create function inside a For Loop to create as many RT FIFOs as you need. You then can use the RT FIFO Read and RT FIFO Write functions inside For Loops to read from and write to all your RT FIFOs consecutively. Using this technique, you can scale your application up to use as many RT FIFOs as you need while keeping the size of your block diagram manageable. Sa

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Functional Global VariablesFunctional global variables (FGV) are VIs that use loops with uninitialized shift registers to hold global data. A functional global variable usually has an action input parameter that specifies which task the VI performs. The VI uses an uninitialized shift register in a While Loop to hold the result of the operation. Functional global variables are discussed in detail in the LabVIEW Core 2 course.

Normally, functional global variables act as a shared resource because they are implemented as non-reentrant subVIs. However, you can implement functional global variables such that they are not a shared resource. First, you must set the priority of the functional global variable VI to subroutine. Then, you can right-click any functional global variable subVI in the calling VI and select Skip Subroutine Call If Busy to force the execution system to skip the subVI if the functional global variable subVI is currently running in another thread. Skipping a functional global variable subVI helps in deterministic loops because the deterministic loop does not wait for the functional global variable subVI resource if it is already currently in use.

If you skip the execution of a subVI, the subVI returns the default indicator value. If you want to detect the execution of a functional global variable, wire a TRUE constant to a Boolean output on the functional global variable block diagram, and ensure that the default indicator value is set to FALSE. If the Boolean output returns TRUE, the functional global variable executed. If the Boolean output returns the default value of FALSE, the functional global variable did not execute.

Conversely, you can instead wire a FALSE constant to a Boolean output on the functional global variable block diagram, as shown in Figure 3-7, and ensure that the default indicator value is set to TRUE. If the Boolean output returns FALSE, the functional global variable executed. If the Boolean output returns TRUE, the functional global variable did not execute.

Figure 3-7. Example Functional Global Variable VI Block Diagram with Boolean Indicator

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Figure 3-8. Skip Subroutine Call If Busy Selection

Skip functional global variables in deterministic loops but not in non-deterministic loops. In non-deterministic loops, you can wait to receive non-default values.

Functional global variables can be a lossy communication method if a VI overwrites the shift register data before another VI reads the data.

Using Functional Global Variables for EncapsulationA critical section of code is code that must behave consistently in all circumstances. When you use multi-tasking programs, one task may interrupt another task as it is running. In nearly all modern operating systems, this happens constantly. Normally, this does not have any effect upon running code, however, when the interrupting task alters a shared resource that the interrupted task assumes is constant, then a race condition occurs. Race conditions and critical sections of code are discussed in the LabVIEW Core 1 course.

One way to protect critical sections is to place them in non-reentrant subVIs. You can only call a non-reentrant subVI from one location at a time. Therefore, placing critical code in a non-reentrant subVI keeps the code from being interrupted by other processes calling the subVI. Using the functional global variable architecture to protect critical sections is particularly effective because shift registers can replace less protected storage methods like global or single-process shared variables. Functional global variables also encourage the creation of multi-functional subVIs that handle all tasks associated with a particular resource.

After you identify each section of critical code in your VI, group the sections by the resources they access, and create one functional global variable for each resource. Critical sections performing different operations each can become a command for the functional global variable, and you can group critical sections that perform the same operation into one command, thereby re-using code.

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Using Functional Global Variables for a Current Value TableA Current Value Table (CVT) is a central data repository containing only the current values of all its data. A CVT centralizes operations with data shared by many processes, allows many application components to share a common data repository, and allows direct access to latest values of data.

Figure 3-9. Example Application Using Current Value Table

A CVT can be implemented using a set of functional global variables that developers use to store and retrieve data asynchronously from different parts of an application. Implementing a CVT using functional global variables will allow you to: Dynamically create variables at run-time. For example, you could create and initialize variables

based on a configuration file.

Figure 3-10. Dynamically Create Variables at Run-Time

Figure 3-11. Dynamically Create Variables from a Config File

Alarm Detection

User Interface

Data Logging

CurrentValueTable

I/O

I/O Hardware

Process Logic

Communication

Network Interface

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Dynamically access large groups of variables. For example, you could initialize 300 PWM variables to the same value and perform the same logic on 500 thermocouple variables.

Figure 3-12. Dynamically Write to Large Groups of Variables

The main reason to use a CVT is for dynamic access to your variables.

Example CVT ImplementationDeveloping your own CVT will require extra development time. To download a completed CVT implementation using functional global variables, view the Current Value Table (CVT) Reference Library document on ni.com and download the implementation. This implementation will install the CVT VIs to the User Library palette in LabVIEW.

This CVT implementation is implemented in a two layer hierarchy consisting of core VIs and API VIs. The core contains all of the functionality of the CVT, including the data storage mechanism and additional service functions. The API VIs provide access to the CVT functionality in a simple interface. There are three groups of API functions that provide slightly different access to the CVT and vary in flexibility and performance, as well as ease-of-use.

Figure 3-13. Example CVT Implementation VI Hierarchy

Across the core and API implementations, the CVT manages different data types in different sets of VIs. For all of the core and API VIs there are separate implementations for each CVT supported data type. Users can extend the supported data types in the CVT by using the current VIs as a template and adding VIs for additional data types. Booleans, 32-bit integers, double precision floating-point numbers, and strings are currently supported.

Init

DataProperties(TagListVI)

DataStorage

(MemBlockVI)

Read

Application

Write API

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Summary Quiz1. Match the following items with their attributes.

Functional Global Variables A. Configure FIFO size dynamically using block diagram code.

Shared Variables with RT FIFO enabled B. Configure FIFO size statically using dialog boxes.

RT FIFO Functions C. Can have several inputs and outputs. Can contain additional custom code.

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Summary Quiz Answers1. Match the following items with their attributes.

Functional Global Variables C. Can have several inputs and outputs. Can contain additional custom code.

Shared Variables with RT FIFO enabled

B. Configure FIFO size statically using dialog boxes.

RT FIFO Functions A. Configure FIFO size dynamically using block diagram code.

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Notes

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