major mos ppt

7/30/2019 Major Mos Ppt

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PROJECT GUIDE:-Mr. Prashant Gupta


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CONTENTS

Introduction Software Used

Block Diagram

Working

DC and Transient analysis

CMOS Layout

NMOS Layout

Conclusion Applications

Future Aspects

References


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INTRODUCTION

This project presents a technique for creatinginverter circuits using discrete MOSFETtransistors.

The inverter stage is a basic building block for

digital logic circuits and memory cells. It consistsof two devices, a pull-up device and a pull-downdevice.

Comparison on various parameters such as dcanalysis, transient analysis, noise analysis etc. hasbeen done for inverters.

Tanner EDA is used in this project for layoutdesigning and comparing for different parameterson T-Spice Pro.


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SOFTWARE USED

L-EDIT. It isfor layout design and editing, including LVSfor

layout versus schematic comparison.

S-EDIT SCHEMATIC EDITOR. S-Edit is a powerful design

capture and analysis package that can generate netlists directly

usable in T-Spice simulations.

T-SPICE CIRUIT SIMULATOR. T-Spice performs fast and

accurate simulation of analog and mixed analog/digital

circuits.

W-EDIT WAVEFORM VIEWER. W-Edit displays T-Spice

simulation output waveforms as they are being generated

during simulation.


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BLOCK DIAGRAM

A generic inverter stage


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WORKING

NMOS ENHANCEMENTMODE PULL-UP.

Dissipation is high since

current flows when Vin =logical 1

Vout can never reach

Vdd (logical 1), if Vgg=

Vdd as is normally thecase.

If Vgg is higher than

Vdd then an extra supply

rail is required.Enhancement mode transistor pull-up


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NMOS DEPLETION MODE PULL-UP.

Dissipation is high sincecurrent flows when Vin

= logical 1

Switching of output

from 1 to 0 when Vin

exceeds Vt of pull-down

device.

Pull-up is non-saturatedinitially and this

presents lower

resistance.

Depletion mode transistor pull-up


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DC AND TRANSIENT ANALYSIS OF

ENHANCEMENT LOAD NMOS

DC Analysis Transient analysis


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DEPLETION LOAD NMOS

DC Transfer Analysis Transient Analysis


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CMOS

DC Transfer Analysis Transient Analysis


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CMOS INVERTER LAYOUT


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NMOS INVERTER LAYOUT


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CONCLUSION

Depletion load advantages over

enhancement load:

Sharp VTC transition.

Better noise margin.

Require single power supply.

Smaller overall layout area.


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CONCLUSION CONTD.

CMOS advantages over NMOS

Steady state power dissipation of CMOS

inverter is negligible. VTC transition is very sharp.

Full output voltage swing between 0V

and Vdd.

High packing density.


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APPLICATIONS

Microprocessors Microcontrollers

Static RAM Image Sensors

Data Converters

Integrated Transceivers Digital Logic Circuits


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FUTURE ASPECTS

Can be used in digital combinational

circuits by using as basic gates.

Used as a basic gate for sequential circuitdesign.

Can be used as a building block in ALU,

microcontroller, RAM devices.


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REFERENCES

Sung-Mo-Kang, Yusuf Leblibici ,CMOS Digital integrated

circuits, Analysis and design,Tata Mcgraw Hill , ISBN 0-07-

119644-7(ISE).

Weste, Neil H. E., Harris, David M. (2005). CMOS VLSI

Design: A Circuits and Systems Perspective, Third Edition.

Boston: Pearson/Addison-Wesley. ISBN 0-321-26977-2

Mead, Carver A. and Conway, Lynn (1980). Introduction to

VLSI systems. Boston: Addison-Wesley. ISBN 0-201-04358-

0.

Baker, R.Jacob (2008). CMOS: Circuit Design, Layout, and

Simulation, Revised Second Edition. Wiley-IEEE. ISBN 978-

0-470-22941-5


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major mos ppt

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