memory inte

8/18/2019 Memory Inte

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Memory Interface

Every microprocessor based system has

some memory. All most all systems contain two types ofmemory: Read Only Memory (ROM) and

Random Access Memory (RAM).There are four common types of memory.

Read Only Memory (ROM) !lash Memory

(EE"ROM) #tatic Random Access Memory(#RAM) and $ynamic Random AccessMemory (RAM).


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% Types of Memories:% % Random vs. sequential% & Random-Access Memory: each word is

accessible separately e'ual access time% & Sequential-Access Memory: nformation stored

is not immediately accessible but only at certainintervals of time

% % manetic dis* or tape% % access time is variable% % Volatile vs. non-volatile% & volatile: stored information is lost when power is

turned off % & Non-volatile: remains even after power is turned

off % % manetic dis* flash memory


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% % Static vs. dynamic% & SRAM: consists essentially of internal

latches and remains valid as lon as poweris applied to the unit% % advantae: shorter read and write cycles% & DRAM: n the form of electric chares oncapacitors which are provided inside thechip by MO# transistors

% % $ra!ac": Tend to dischare with time and

must be periodically rechared by refreshincyclin throuh the words every few ms.

% % advanta#e: reduced power consumption

and larer storae capacity


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% Memory $in %onnections:

% "in connections common to all memory devices are theaddress inputs data outputs or input+outputs some type of

selection input and at least one control input used to select aread or write operation.

% The fiure below is for a ROM and RAM devices


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% Address %onnections: All memory devices haveaddress inputs that select a memory location withinthe memory device.

% Most of the common memory devices havebetween ,- to ,M memory locations.

% Even /0M memory location devices are alsoavailable.

% ,- memory devices have ,1 address pins (A12A3)4% Means ,1 address pins are re'uired to select any

one of the ,1/5 memory locations.% #imilarly ,, pins for /- locations% ,/ pins for 5- locations etc.% A device containin ,M locations re'uires /1 bit

address (A12A,3).


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% 5116 represents a ,-2 byte of memory section.

% f a memory device is decoded to bein at memoryaddress ,11116 and is ,- device its last locationis at address ,17!!.

% A memory device is containin a startin address of,51116 and it is havin 5- locations then its last

address is ,5!!!% i.e. one less than ,1116

% 5- is e'ual to ,11116 f a memory starts at711116 and is 5- then its last address is 7!!!!6.

% ,M memory contains ,111116 memory locations.% 11111 to !!!!! is ,M locations.


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% Data %onnections: All memory devices have a setof data outputs or input+outputs.

% $ata connections are the points at which data are

entered for storae or e8tracted for readin.% $ata pins are labeled as $1 throuh $9 for an 2

bit wide memory device.% f a memory device is havin +O connections it

can store bits of data in each memory location.% An 2bit wide memory is often called a byte2 wide

memory.% ;atalo listins for memory devices often refer to

memory locations times bits per memory location.% E8ample:% ,- <


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% Selection %onnections:% Each memory device has an input sometimes

more than one that selects or enables the

memory device.% ;hip #elect (=;#) ;hip Enable (=;E) orsimply (=#) input.

% >oic 1 enables and loic , disables the

memory device.% f more than one =;# connection is presentall must be activated to read or to write.


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% %ontrol %onnections: All memory devices havesome form of control input or inputs.

% A ROM usually has only one control input while

RAM often has one or two inputs.% The control input most often found on ROM is the

output enable (=OE) or ate (=?) connection whichallows data to flow out of the output data pins of theROM.

% The =OE connection enables and disable a set ofthree state buffers located within the memory deviceand must be active to read data.

% A RAM memory device has either one or two control

inputs. f there is one control input it is often calledR+ @.% This pin selects a read or write operation only if the

device is selected


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% ROM Memory: ROM is available in manyforms4 E"ROM "ROM EAROM etc.

% /9, is /-8 E"ROM


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% 6avin ,, Address inputs

% data outputs

% , ;# line

% The access time is measured from the appearance of theaddress at the address inputs until the appearance of thedata at the output connections


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% Static RAM &SRAM' Devices:

% Retain data as lon as power is applied.

% As no special action is re'uired to retainstored data e8cept power these devices arecalled as #tatic memory.

% 51, is a representative device for all#RAMs

% 6avin /-


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% $ynamic RAM ($RAM) Memory:

% The larest static RAM available today is a ,/8.

% $RAMs are available in much larer sie upto,M8,.

% $RAM is same as #RAM e8cept it retains dataonly for / or 5 ms.

% #o after / or 5 ms it has to be rewritten (refreshed)because the capacitors which store a loic , orloic 1 lose their chare.

% TM#555 is $RAM which stores /0 - bits of data.

% $RAM memory is usually placed on small circuitboards called Sinle n2line Memory Modules(#MM).


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% Address Decodin#:% n order to attach a memory device to the microprocessor it

is necessary to decode the address from the microprocessor

to ma*e the memory function at a uni'ue section or partitionof the memory map.% @ithout an address decoder only one memory device can be

connected to a microprocessor which would ma*e it virtuallyuseless.

% ()y Decode memory *% @hen the 1+1 is compared to the /9, E"ROM a

difference in number of address connections E"ROM ishavin ,, and Microprocessor is havin /1.

% Means the microprocessor sends out /12bit address% #o there is mismatch. This mismatch is corrected by the

address decoders.


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% Simple NAND +ate Decoder :

% @hen /-8 E"ROM is used address connections A,12A1 1fthe microprocessor are connected to address inputs A,12A1

of E"ROM.% The remainin address pins (A,32A,,) are connected to the

inputs of a BAB$ ate decoder


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% n this circuit a sinle BAB$ ate decodes the memoryaddress.

% The output of BAB$ ate is a loic 1 whenever the address

inputs A,32A,, are all loic ,s.% The active low loic 1 output of the BAB$ ate decoder is

connected to the ;E bar input which selects the E"ROM.

% E8ample:

% A,3

A,

A,9

A,

A,0

A,5

A,7

A,/

A,,

A,1

A3

A

A9

A

A0

A5

A7

A/

A,

A1

% , , , , , , , , , 8 8 8 8 8 8 8 8 8 8 8

% or

% , , , , , , , , , 1 1 1 1 1 1 1 1 1 1 1

C!!116 % To

% , , , , , , , , , , , , , , , , , , , ,C!!!!!6


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% Althouh this e8ample serves to illustrate decodin BAB$ates are rarely used to decode memory because eachmemory device re'uires its own BAB$ ate decoder.

% T)e ,- to- line Decoder : 95>#,7% Most commonly found decoder


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% The truth table shows only one of the outputsever oes low at any time.

% Once the 95>#,7 is enabled the address inputs(;D and A) select which output pin oes low.

% This decoder provides E"ROM ;E outputs.

% t is very powerful device because it selects

different memory devices at the same time.% A #ample decoder: eiht /95 E"ROM memory

devices are connected to the decoder

% The decoder selects eiht - bytes bloc*s ofmemory for a total of 5- bytes of memory.


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% !iure : A circuit that uses eiht /95 E"ROM for a 5- < section ofmemory in an 1 microprocessor based system. The addressesselected in this circuit are !111162!!!!!6

%


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% All the address connections of 1+1 are connected.% The ;E bar inputs of E"ROMs are connected to the eiht

outputs of the decoder

% R$ bar sinal from the microprocessor is connected to theOE bar inputs of the E"ROMs.% This allows only the selected E"ROM to be enabled and to

send its data to the microprocessor throuh the data buswhenever Rd bar is 1

% n this circuit a 72input BAB$ ate is connected to addressbits A,32A,9.

% E8ample:% A,3 A, A,9 A, A,0 A,5 A,7 A,/ A,, A,1 A3 A A9 A A0 A5 A7 A/ A, A1% , , , , 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8

% or % , , , , 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1C!11116

% To% , , , , , , , , , , , , , , , , , , , ,

C!!!!!6


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% "ROM Address $ecoder:

% Another common decoder is bipolar "ROM

% A$: >are no. of input connections2 whichreduces the no. of other ;ircuits

% 95>#,7 has inputs for address

connections "ROM decoder may have moreinputs for address decodin

% /#,59 (0,/8) "ROM

% 3 address inputs and data outputs% & replace 95>#,7 without e8tra 72inputBAB$ ate


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% "ROM is a memory device that must beprorammed with the correct binary bit

pattern to select the eiht E"ROM memorydevices.

% The "ROM has nine address inputs thatselect one of the 0,/ internal bit memorylocations.

% The remainin input ;E bar must berounded.

% The main advantae of "ROM decoder isthat the address map can be easily chanedin the field.


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%


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% ">$ prorammable $ecoders:

% Recently "A> has replaced "ROM address

decoders in the memory interface.% There are three types of ">$s that function in

the same manner but have different.

% ">A "A> and ?A>% Memory interface:

% The 1 differs from 1 in three ways: ,.

data bus% /. M+O bar in 1 is O+M bar in 1 and

% 7.D6E bar in 1


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% , Dit Dus ;ontrol: $ata bus of 1 is twice as wide as thebus for 1.

% #o the processor must able to write data to any , bit

location or any bit location.% #o , bit data must be divided into two separate sections

that are bits wide so the microprocessor can write to either

half or both halves.

% =D6E = D>E

!!!!! !!!!$ 222222222

6ih ban* 22222222 11110 11117 1111,

!!!!E!!!!;!!!!A

22222222>ow ban*22222222111151111/11111


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% 1 uses the D6E bar sinal and A1address bit or D>E bar to select one or both

ban*s of memory for the data transfer.D6E D>E(A1) !unction

1 1 Doth ban*s enabled for a , bit transfer

1 1 6ih ban* enabled for an bit transfer

, 1 >ow ban* enabled for an bit transfer

, , Bo ban* enabled


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% Dan* selection is accomplished in two ways:

% ,.A separate write sinal is developed to

select a write to each ban* of the memory or/. separate decoders are used for each ban*.

% #eparate ban* decoder is the least effective

way to decode memory address for 1.% #eparate Dan* write strobe method is the

most effective way for address decodin.

% This techni'ue re'uires only one decoder toselect a , bit wide memory.


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% This often saves money and reduces thenumber of components in a system.

% 6ere

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