memristor based arbiter puf: cryptanalysis threat and its mitigation · 2016-01-13 · memristor...

Memristor based Arbiter PUF: Cryptanalysis Threat andits Mitigation

Urbi Chatterjee, Rajat Subhra Chakraborty IIT Kharagpur,India

Jimson Mathew University of Bristol, UK/ RSET, Kochi, India

Dhiraj K. Pradhan University of Bristol, UK

13/10/2015 Urbi Chatterjee , Weekly Talk 1/28

Outline

Introduction to Physical Unclonable Functions

Introduction to Memristors

Operating Principle and Structure of Memristors

Proposed Memristor PUF: Architecture, Operation and CircuitAnalysis

Cryptanalysis of the PUF Circuit

Modified Memristor based PUF Circuit

Experimental Setup and Results

Conclusions



PUF is a mapping γ : 0, 1p −→ 0, 1q, where the output q-bitwords are unambiguously identified by both the p challenge bits andthe unclonable, unpredictable (but repeatable) instance specificsystem behavior.

Easy to design and fabricate, but infeasible to replicate, even if giventhe exact manufacturing process.



Advantages over traditional cryptographic algorithms:

Attacks for revealing the secret key are irrelevant, as it is not explicitlystored, but an inherent property of the security primitive instance.The hardware security primitives offload much of the expensivecomputations necessary for cryptographic algorithms and protocols.

Major Threat against PUFs: Model Building Attacks


Introduction to Memristors

Proposed as missing fundamental circuit element in the seminal workby Chua 1971.

Metal-oxide memristors: an exciting new addition to the novel classof nano devices,especially those beyond silicon but having processingtechnology, relatively compatible with CMOS.

Demonstrates controlled sensitivity of process variations, which makesbuilding of hybrid memristor-CMOS devices feasible.

Applications: Efficient non-volatile storage, content-addressablememory (CAM) and general logic design following the threshold logicstyle.



w(t): The instantaneous width of the conductive TiO2−x

layer,depends on the history of the applied voltage to the device.

D: The total width of the device.

Ron: The low-resistance of the device if the entire device is doped.

Roff :The high-resistance of the device if the entire device is undoped.

µ: The average ion mobility.

η(= ±1): The polarity of the applied voltage signal

φ(t): The flux that incorporates the history of the applied voltage tothe device.



Req(t) =w(t)

D· Ron +

(1− w(t)

D

)· Roff

provided Roff >> Ron

Req(t) = R0

√(1− 2η∆Rφ(t)

D2R20

· µRon

)where R0 ≈ Roff ; ∆R = Roff − Ron;

φ(t) =

∫ t

−∞Vappl (t)dt



Demonstrate a switching behavior between two distinct conductionmodes (depending on its applied voltage):a low and a high-resistancestate

The instantaneous “memresistance” value, Req(t), is retained even ifthe excitation voltage is removed.

This property is utilized in using the device as a non-volatile storageelement.

R0 term is affected by process variations in the lateral dimensions (Land W ).

The impact of process variations on the thickness parameter (D) isnon linear.

This property is utilized for unique hardware-specific signature.


Proposed Memristor PUF: Architecture, Operation andCircuit Analysis



The width of the RESET pulse is dependent on the the length of thememristor chains.

The effective potential difference across each memristor device isdifferent during the reset phase.

The memristors are in a random resistance state after reset,depending on their individual device-level properties.



The delay modelling follows a Elmore Delay Model based analysis.

Dupper = CMOS ·M1+CMOS ·(M1+M2)+ · · ·+CMOS ·(M1+M2+ · · ·+Mp)

Dlower = CMOS ·M ′1+CMOS ·(M ′1+M ′2)+ · · ·+CMOS ·(M ′1+M ′2+ · · ·+M ′p)

∆D = Dupper − Dlower

= CMOS · (M1 −M ′1) + CMOS ·[M1 + M2 − (M ′1 + M ′2)

]+ · · ·+ CMOS ·

[M1 + M2 + · · ·+ Mp − (M ′1 + M ′2 + · · ·+ M ′p)

]= CMOS ·

[p(M1 −M ′1) + (p − 1)(M2 −M ′2) + · · ·+ (Mp −M ′p)

]= CMOS · [p∆M1 + (p − 1)∆M2 + · · ·+ ∆Mp]

= −→w T ·−→Φ



We have used Mi ≡ Mi (−→C ) M ′i ≡ M ′i (

−→C )

∆Mi (−→C ) = Mi (

−→C )−M ′i (

−→C ), with:

−→w (−→C ) =

CMOS ·∆M1(

−→C )

CMOS ·∆M2(−→C )

...

CMOS ·∆Mp(−→C )

and−→Φ =

p

p−1...1

Response = −(−→w T (

−→C ) ·−→Φ )


Pros and Cons of the Proposed Model

It is attractive as a PUF because of its relative lightweightedness,regularity of design and ease of implementation.

It is resistant to machine learning modelling attack, since the featurevector is challenge-dependent (unlike the CMOS arbiter PUF).

Still the model is vulnarable against cryptanalysis attack.



Partitioning of Set of Challenges

Each partition is representable by a unique bit pattern:(0?)(1(0|1)+)1)(0?).

The number of partitions (PC) for the set of challenges C: O(n2) foran n–bit memristor APUF.



Enumeration of Partitions of Challenge Set

The challenge bits for an n-bit PUF are indexed as C1, C2, · · · Cn.

If C1 and Cn are both set to 1, the challenges are of the form1 xxx · · · x︸︷︷︸(n − 2) don’t cares

1, and hence there are 2n−2 challenges for which the

response would be the same.

If C1 = 1 = Cn−1 = 1 but Cn = 0, there will be 2n−3 challenges forwhich the responses will be the same.

Therefore, the total number of challenges that will produce the sameresponse when C1 = 1 is given by:

N′1′ = 2n−2 + 2n−3 + ...+ 2 = 2n−1 − 2




Set C1 = 0, C2 = 1, and Cn = 1.

The number of challenges for which the output will remain same is2n−3.

The total number of equivalent challenges will be:

N′01′ = 2n−3 + 2n−4 + ...+ 2 = 2n−2 − 2

C1 = C2 = · · · = Cn−3 = 0, Cn−2 = Cn = 1, then there will be twoequivalent challenges with the same response.




The set of challenges C can be partitioned into several subsetsdepending on the different challenge patterns.

All challenges having the pattern ′1xx · · · x1′ forms a subset.

If C1 = 1, then there will be in total n − 2 subsets in the partition,having cardinalities 21, 22, · · · 2n−2 respectively. Similarly, if the firsttwo bits are set to 01, then there will be n − 3 subsets of challenges.

the total number of subsets in the partition of C will be:

PC = (n − 2) + (n − 3) + ...+ 1 = (n2 − 3n + 2)/2


Modified Memristor based PUF Circuit



The simulations were carried out using HSPICE.

Table : Memristor Device Parameters

Memristor Parameter ValueRon 121 Ω

Roff 12.1 kΩ

L 10 nm

D 10 nm

W 10 nm

µ 10−14 m2/(V·s)

Table : Monte Carlo Simulation Setup

Memristor Parameters CMOS Parameters Environmental Conditions Simulation Count(% variation) (% variation) (variation range)

D (±15%) Vth (±15%) Temperature: 10 – 50C 5000

Supply Voltage: 0.90 – 1.10 V



Table : Machine Learning Modelling Setup

PUF Size Total CRP Set Size Training Set Sizes Feature(fraction of total CRP set)

16–bit 1000 20%, 50%, 70%−→Φ (Eqn. (14))

32–bit 2000 —do— —do—

48–bit 2000 —do— —do—

64–bit 5000 —do— —do—



Table : Memristor PUF Performance Metrics

PUF Size Uniqueness Uniformity Bit–aliasing Reliability (temperature) Reliability (voltage)(%) (%) (%) (%) (%)

16–bit 51.06 51.20 50.60 99.70 98.80

32–bit 50.01 50.30 52.10 98.50 98.60

48–bit 52.00 54.80 48.50 99.60 97.90

64–bit 49.40 51.20 53.37 99.20 97.20



Table : Machine Learning Modeling Accuracy Results

PUF Size Training Set Size SVM LR LR-RProp Training Runtime(%) Accuracy (%) Accuracy (%) Accuracy (%) (sec.)20 55.00 50.00 50.00 0.03

16–bit 50 55.80 50.00 50.00 0.1070 60.67 50.00 50.00 0.14

20 50.75 50.00 50.00 0.0732–bit 50 51.20 50.00 50.00 0.13

70 51.33 50.00 50.00 0.19

20 50.37 50.00 50.00 0.3248–bit 50 52.20 50.00 50.00 0.47

70 58.00 50.00 50.00 0.58

20 53.44 50.00 50.00 0.4264–bit 50 55.50 50.00 50.00 0.52

70 54.66 50.00 50.00 0.69


Robustness to Cryptanalytic Attacks

The 1000 challenges for the 16-bit PUF belonged to 52 differentsubsets (out of the 105 possible).

The cryptanalysis is considered to be successful if the proportion of0’s and 1’s for the responses in each subset deviates from the idealfraction of 50% by more than ±10%.

For the insecure 16–bit APUF, 32 out of the 52 (i.e. 61.5%) subsetsshowed this bias, while for the PUF proposed in this paper, only 18out of the 52 (i.e. 34.6%) subsets showed this bias.

Similar results were obtained for larger PUFs.


Conclusions

We have demonstrated that a recently proposed hybridCMOS-memristor APUF circuit, although lightweight and resistantagainst machine learning modelling attacks, is vulnerable to a chosenchallenge cryptanalytic attack.

We have then modified the design to make it robust against theproposed cryptanalysis, while retaining its low hardware footprint andits resistance against model building attack.

We have validated the usefulness of the new circuit with extensivecircuit simulations, machine learning based and cryptanalytic analyses.


Thank You


memristor based arbiter puf: cryptanalysis threat and its mitigation · 2016-01-13 · memristor...

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