research article a new arbiter puf for enhancing

Research ArticleA New Arbiter PUF for Enhancing Unpredictability on FPGA

Takanori Machida1 Dai Yamamoto2 Mitsugu Iwamoto1 and Kazuo Sakiyama1

1The University of Electro-Communications 1-5-1 Chofugaoka Chofu-shi Tokyo 182-8585 Japan2Fujitsu Laboratories Ltd 4-1-1 Kamikodanaka Nakahara-ku Kawasaki-shi Kanagawa 211-8588 Japan

Correspondence should be addressed to Takanori Machida machidauecacjp

Received 24 April 2015 Revised 27 July 2015 Accepted 19 August 2015

Academic Editor Israel Koren

Copyright copy 2015 Takanori Machida et al This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

In general conventional Arbiter-based Physically Unclonable Functions (PUFs) generate responses with low unpredictability The119873-XOR Arbiter PUF proposed in 2007 is a well-known technique for improving this unpredictability In this paper we proposea novel design for Arbiter PUF called Double Arbiter PUF to enhance the unpredictability on field programmable gate arrays(FPGAs) and we compare our design to conventional 119873-XOR Arbiter PUFs One metric for judging the unpredictability ofresponses is to measure their tolerance to machine-learning attacks Although our previous work showed the superiority of DoubleArbiter PUFs regarding unpredictability its details were not clarified We evaluate the dependency on the number of trainingsamples for machine learning and we discuss the reason why Double Arbiter PUFs are more tolerant than the 119873-XOR ArbiterPUFs by evaluating intrachip variation Further the conventional Arbiter PUFs and proposed Double Arbiter PUFs are evaluatedaccording to other metrics namely their uniqueness randomness and steadiness We demonstrate that 3-1 Double Arbiter PUFarchives the best performance overall

1 Introduction

11 Background Nowadays many products related to ourdaily life are being connected to the Internet and controlled bycomputers Thus machine-to-machine communication is anincreasingly common phenomenon Secure authenticationsbetween these machines are needed for security for exam-ple to avoid fake integrated circuits Physically UnclonableFunctions (PUFs) [1 2] have been proposed as a solution tothis problem [3] Authentication utilizing PUFs can providethe protection of an authentication chip on a device andintellectual property core protection for field programmablegate arrays (FPGAs) [4 5]

PUFs are physical functions that output a unique value asa response to an input known as a challenge The responsereflects the manufacturing variation of the physical unit Averifier stores challenge-response pairs (CRPs) to test theauthenticity of the so-called prover The stored responses inthe verifier are compared with the responses provided by theprover according to the same challenge This comparison ofresponses enables the verifier to confirm whether the prover

is genuine This authentication mechanism is consideredsecure insofar as it is difficult to copy the manufacturingvariation of the PUF Because PUFs can be implementedwith comparatively small circuits they facilitate lightweightauthentication

PUFs can be implemented not only on an application spe-cific integrated circuit (ASIC) [6] but also on an FPGA [7]FPGAs are embedded in various products that require bothcustomizability and security because synthesizing FPGAs isprogrammable For low-volume manufacturing it is rela-tively less expensive to produce a product with an FPGA thana product with an ASIC

Many types of PUFs have been proposed The authorsof [8] categorize them into two types memory-based anddelay-based PUFsWe focus onArbiter-based PUFs a varietyof delay-based PUFs Delay-based PUFs use delay-timeinformation from the signal propagation in the circuit Thebasic concept of an Arbiter PUF was described in 2002 [9]They are based on the delay-time difference between twosignals Arbiter PUFs that consist of symmetrically locatedwires and selectors were proposed in 2004 [10 11] and

Hindawi Publishing Corporatione Scientific World JournalVolume 2015 Article ID 864812 13 pageshttpdxdoiorg1011552015864812

2 The Scientific World Journal

they were evaluated using various metrics Other authorscategorize PUFs into strong PUFs and weak PUFs [5] On theone hand the former PUFs have a relatively large challengespace that is they can use many challenges making themsuitable for the device identification and authentication Therelation between challenges and responses is too complexto be accurately predicted Previous work also suggests thatthe responses from some of these PUFs can be predicted bymodeling attacks based on machine learning which uses amathematical model established by authorized CRPs Con-sequently the Arbiter PUF was once considered a candidatefor a strong PUF but has since been found to be vulnerableto such modeling attacks [12 13] On the other hand weakPUFs have either no challenge space or one that is relativelysmall Weak PUFs can be used for key generation or for somecryptographic protocols on a device because it often generatesstable responses in repeated measurements [14 15]

In this paper we discuss secureArbiter PUF implementedon FPGA (Parts of this paper are based on [16ndash18]This papernewly discusses optimal implementations for high toleranceagainst machine-learning attack along with high uniquenessand steadiness)

12 Motivation and Contribution The authors of [19] pro-posed the 119873-XOR Arbiter PUF that uses the XOR 119873responses from the 119873 Arbiter PUFs implemented on thesame chip to decrease the predictability of the responsesIn this paper we introduce a novel Arbiter PUF DoubleArbiter PUF whichwas originally proposed as a technique forgenerating highly unique responses [16] We expect that ourDouble Arbiter PUF will be a valid approach for enhancingunpredictability even on FPGAs that have wiring problem(see Section 3 below) The authors of [17] proposed 2-1Double Arbiter PUF whose response is obtained by twoXORing responses from the Double Arbiter PUF 3-1 DoubleArbiter PUF was also proposed in [17] This PUF has a thirdbuilding block and its response is generated by six XORingresponses from these building blocks Although the authorsof [18] considered the tolerance of conventional ArbiterPUF and Double Arbiter PUFs to machine-learning attacksthey did not compare them with the 119873-XOR Arbiter PUFFurther there were no results that showed a dependency onthe number of training samples in [18] We newly evaluate119873-XOR Arbiter PUFs and Double Arbiter PUFs accordingto this tolerance by using between 100 and 1000 trainingsamples In order to clarify the reasonwhy theDoubleArbiterPUF is more effective than the conventional119873-XOR ArbiterPUF at XORing responses for adding the unpredictabilitywe evaluate these PUFs according to intrachip variationa metric defined in this paper Our experimental resultsshow that the intrachip variation of Double Arbiter PUFsis much higher than that of the conventional Arbiter PUFand that its tolerance against machine-learning attacks is alsorelatively high regardless of number of training samplesIn particular it is difficult to predict responses from the 3-1 Double Arbiter PUF because the prediction rate of theresponses for randomly chosen challenges is approximately57 and this is close to 50 random guess

XORing responses from multiple PUFs within the samechip can be also expected to increase the interchip dif-ference among chips that has been evaluated according touniqueness [20] We introduce the results from [17] regardinguniqueness and confirm that the uniqueness of the DoubleArbiter PUFs is almost ideal and much higher than that ofconventional 119873-XOR Arbiter PUFs In this paper we newlypropose 4-1 Double Arbiter PUF that has a fourth buildingblock The response from this PUF is generated by moreXORing responses than the 3-1 Double Arbiter PUF Fromour experimental results we demonstrate the proposed PUFrsquostolerance to machine-learning attacks and its uniquenessboth of which are comparable to the 3-1 Double Arbiter PUFA high level of stability in the responses is also needed whenrepeating the same challenge for the device authenticationusing PUFs a metric referred to as steadiness [20] Becauseour results show low steadiness in the 4-1 Double ArbiterPUF we conclude that the 3-1 Double Arbiter PUF is themostsuitable PUF for device authentication

Our contributions are summarized as follows(i) We show that the 3-1 Double Arbiter PUF has much

higher tolerance tomachine-learning attacks than theconventional119873-XOR Arbiter PUF

(ii) We also conclude that the 3-1 Double Arbiter PUFdemonstrates the best performance from among theintroduced PUFs in terms of tolerance uniquenessand steadiness

13 Organization of This Paper Section 2 shows the relatedwork the structure of conventional Arbiter PUFs the reasonwhy conventional Arbiter PUFs are vulnerable to machine-learning attacks and their countermeasures In Section 3 weintroduce the Double Arbiter PUFs as an alternative coun-termeasure Our experimental environment and the metricsfor our evaluation including the intrachip variation aredescribed in Section 4 Section 5 compares the conventionalArbiter PUF with the Double Arbiter PUF in terms of theirtolerance to machine-learning attacks Section 6 provides theresults from a performance evaluation based on [17] anddiscusses the feasibility of the introduced PUFs for deviceauthentication Finally we conclude the paper in Section 7

2 Related Work

21 Arbiter PUF The Arbiter PUF proposed in [10 11]consists of selector pairs connected in a series and anArbiter (an SR-Latch is used as shown in Figure 1) thatdetermines its response as shown in Figure 1 First an inputsignal is supplied to the first left and right selectors at thesame time The genetic idea behind Arbiter PUFs is to racethe delay times between the two signals The two signalspropagate through various routes depending on the valueof the challenges These routes are determined by an 119899-bitchallenge that is given as the selection input for the selectorpairsThe (119894+1)th challenge bit 119888

119894out from the 119899-bit challenge

corresponds to the selection inputs for the (119894 + 1)th selectorpair where 119894 = 0 1 119899 minus 1 When 119888

119894= 1 two output

signals from the 119894th selector pair are crossed and supplied to

The Scientific World Journal 3

0 01

0 1

0 1

1

01

01

RSQ Q

r

c0

c1

cnminus1

Figure 1 Structure of the Arbiter PUF

the selection inputs for the (119894+1)th selector pairWhen 119888119894= 0

the two signals are directly supplied to the selection inputs forthe (119894 + 1)th selector pair A 1-bit response 10 is determinedby which signal reaches an Arbiter faster than the other Thesize of the challenge space is 2119899 such that 2119899 patterns of thepropagation delay time can be organized Physically the wirelength of the two lines should be the same

22 Machine-Learning Attacks for Arbiter PUFs In this sec-tion a framework for machine-learning attacks with a delaymodel is explained by referring to [12 13] and we discusshow responses from the Arbiter PUF can be predicted withmachine learning

The basic concept formachine learning is as follows Eachroute through which two signals traverse is determined by achallenge for the Arbiter PUF and a response is determinedby the delay-time difference of the signals Let w be a modelof the delay times for an Arbiter PUF Let 120593 be a modelextracted from a challenge for this Arbiter PUF and let 119903 be aresponse Because a response is determined with a sign of thedelay-time difference between two signals the response canbe expressed as

119903 = sgn (w119879120593) (1)

where sgn is a sign function and w119879 denotes the transposedw Because it is difficult to know the delay times w the pairfor a response 119903 and a model for the challenge 120593 is given anda model for the delay times is constructed

The procedure for machine learning consists of twophases a training phase and a classification phase as shownin Figure 2 During the training phase several pairs ofchallenges 119888 and responses 119903 from the target Arbiter PUFare initially prepared Then feature extraction is performedChallenge 119888 is transformed in order to simplify the machinelearning process The procedure of this challenge transfor-mation from 119888 to 120593 is as follows Let 119888

119896be the 119896th bit of

Pairc r

Training

Parameterw

Classification

120593998400 Inputr998400 = sgn(wT 998400)

c998400

r998400

phase phase

Featureextraction

Featureextraction

120593

120593

Figure 2 Machine-learning attack against an Arbiter PUF

a challenge where 119896 (= 1 2 119899) denotes the length of thechallenge Let 120593

119894be the 119894th bit of the transformed challenge

where 119888 isin 1 0119899 119894 = 1 2 119899 + 1 and 120593 isin 1 minus1119899minus1 Thechallenge model is 120593 expressed as

120593119894=

119899

prod

119896=119894

(1 minus 2119888119896) (119894 = 1 2 119899)

1 (119894 = 119899 + 1)

(2)

After feature extraction a model for the delay times w isconstructed depending on the pair of the challenge model120593 and the response 119903

A different challenge 1198881015840 whose response is unknownis provided during the classification phase After featureextraction from 1198881015840 to 1205931015840 the response 1199031015840 is predicted byusing the model for the delay timesw constructed during thetraining phase as follows

1199031015840= sgn (w1198791205931015840) (3)

The response 1199031015840 is the output from machine learning and wecan evaluate whether 1199031015840 is equivalent to the response obtainedfrom the Arbiter PUF given 1198881015840

Feature extraction must be more fully elaborated Firstwe explain the relationship between 119888 and 120593 by using theexample shown in Figure 3 Figure 3 shows one part of anArbiter PUF including the selector pairs and wires to which achallenge from the (119899minus3)th to the 119899th is givenThe dashed redand solid black lines refer to an example of two paths whenthe challenge 119888

119896from the (119899 minus 3)th to the 119899th is ldquo0110rdquo Then

we focus on the wire illustrated as a dashed line out of thetwo wires The value of the challenge model 120593 shows whichsignal is located in the right position between selector pairsSuppose that a signal through the wire (the dashed line) hasa long delay time at the output of the (119899minus 4)th selector pair Ifwe use the challenge model 120593 we can easily recognize whichsignal (whether the dashed or solid line) is located in the rightposition at the output of the last selector pair

Suppose that there is a pair of challenges where oneis chosen randomly and the other involves a 1-bit flip ofthis challenge Although the Hamming distance between thepair of challenges is small that is insofar as the challengesare similar the pair of responses related to the pair of


k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1

Challenge ck Model 120593i

0

0

Figure 3 Relationship between the challenge and model

challenges can have different values because the position ofthe signal through the dashed or solid line at the output ofthe last selector pair is exchanged By contrast when thesame pair of challenge model vectors 120593 is given namely therandomly chosen vector and the 1-bit flipped vector the pairof responses can have the same value because the positionof the signal is not exchanged It is worth noting that thesignal through the dashed and solid line with the originalchallenge has a total delay time similar to that of the signalwith the similar challengeThis consideration is important toSection 51 when discussing a challenge model for a DoubleArbiter PUFs

23 119873-XORArbiter PUFs forUnpredictability Previouswork[19] has proposed the119873-XORArbiter PUFs as a countermea-sure against machine-learning attacks The authors of [19]aimed to obfuscate the response by XORing 119873 responsesobtained from 119873 Arbiter PUFs on the same chip Figures 4and 5 show the structures for the 2- and 3-XOR Arbiter PUFrespectively

3 New Arbiter PUFs for Unpredictability

In this section we introduce the Double Arbiter PUF [16]as another approach to enhance the unpredictability ofresponses The Double Arbiter PUF was originally proposedin [16] as a technique for increasing variety of responsesamong chips

In general it is difficult to implement two wires of exactlythe same length (so-called equal-length wiring) not onlyon FPGAs but also on ASICs With two wires of unequallength the two signals through these wires will have obviousdifferences in delay times Suppose that we compare twosignals through specific paths where the length of the wiresis unequal in an Arbiter PUF If this delay time is longerthan the delay time based solely on the physical variation of

c0 0 01 1

01

01

0 1

0 1

010 1

010 1

010 1cnminus1 cnminus1

S R

Q Q

S R

Q Q

c1

c0

c1

r

Figure 4 Structure of the 2-XOR Arbiter PUF

the devices the response from the chips will be the sameThat is there will be no difference in the responses of thedevices Further because it is easy to predict these responsesthis wiring problem is pertinent to the unpredictability of theresponses from PUFs

Our approach to this problem involves duplicatinganother selector chain for a different reason than the 2-XOR Arbiter PUF as shown in Figure 6 The duplicatedselector chain is implemented in SLICEs that neighbor theoriginal selector chain Each signal through the same routein each selector chain competes with the other The DoubleArbiter PUF generates 2-bit responses 1199031 and 1199032 as shownin Figure 6 This duplication-based approach can escape thewiring problem because the length of the duplicated wire isexpected to be similar to that of the original wire given thesymmetric layout implemented on neighboring SLICEs

The authors of [17] proposed a 2-1 Double Arbiter PUFwhose 1-bit response is generated by XORing 2-bit responsesfrom a Double Arbiter PUF as shown in Figure 7 The aim ofthe 119873-XOR Arbiter PUFs is to improve the unpredictabilityby XORing multiple responses To render the response lesspredictable we can increase the number of XORed responsesfromDouble Arbiter PUFsThe authors of [17] proposed a 3-1Double Arbiter PUF (the main purpose of [17] is to increasevariety of responses among chips) that XORs six responses byimplementing a thirdArbiter PUFon the same chip as shownin Figure 8We discuss the unpredictability of its responses inSection 5 with evaluation results showing howdifferent theseresponses are among Double Arbiter PUFs in Section 6

4 Preliminaries of Our Experiments

41 Experimental Environment In our experiment 64-bitArbiter PUFs (ie where 64-bit challenges are available) wereimplemented on three Xilinx Virtex-5 FPGAs (XC5VLX30)[21] FPGA A FPGA B and FPGA C These FPGAs wereset up on a side-channel attack standard evaluation boardG-II (SASEBO G-II) [22] and we provided challenges andobtained responses through aRS-232C cable connected to theSASEBOG-II Xilinx ISE 132 andXilinx PlanAhead 132 were


Table 1 Placement of primitives on SLICEs for 3-1 Double Arbiter PUF The value for the variable 119895 can range from 0 to 63

Descriptions Primitives SLICEs(MUX 1L (119895) MUX 1R (119895))

F7BMUX

(SLICE X14Y(76minus119895) SLICE X15Y(76minus119895))(MUX 2L (119895) MUX 2R (119895)) (SLICE X16Y(76minus119895) SLICE X17Y(76minus119895))(MUX 3L (119895) MUX 3R (119895)) (SLICE X18Y(76minus119895) SLICE X19Y(76minus119895))(MUX 4L (119895) MUX 4R (119895)) (SLICE X20Y(76minus119895) SLICE X21Y(76minus119895))

Pair of NAND in

SR-Latch 1

C6LUT

(SLICE X14Y12 SLICE X16Y12)SR-Latch 2 (SLICE X16Y11 SLICE X18Y11)SR-Latch 3 (SLICE X18Y10 SLICE X14Y10)SR-Latch 4 (SLICE X15Y12 SLICE X17Y12)SR-Latch 5 (SLICE X17Y11 SLICE X19Y11)SR-Latch 6 (SLICE X19Y10 SLICE X15Y10)

r

S R

QQ

S R

QQ

S R

QQ

c0

c1

cnminus1

0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01

c0

c1

cnminus1

c0

c1

cnminus1


r1 r2

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

Figure 6 Structure of the Double Arbiter PUF

used for the logic synthesis and for the floorplanning respec-tively Part of floorplanning design for the 3-1 Double ArbiterPUF is illustrated in Figure 9 In addition Table 1 details theplacement of primitives on SLICEs for our experiments Thenotations for the PUF components in the first column ofTable 1 are defined in Figure 8

42 Intrachip Variation The main goal of this paper is toevaluate the efficiency of XORing responses from ArbiterPUFs on the same chip If several pairs of XORed responseshave the same value most of XORed responses become

r

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

Figure 7 Structure of the 2-1 Double Arbiter PUF

0s Because it is easy to predict the XORed responses inthis situation the pairs of responses should be completelydifferent The intrachip variation metrics is calculated withthe following procedure First we implement two ArbiterPUFs that generate two responses on the same chip Secondwe provide the PUFs with 119873 randomly chosen challengesand the pair of 119873-bit responses is generated Third wecalculate the Hamming distance (HD) between the pair ofresponses The intrachip variation is defined as the HD


r

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

c0

c1

c0

c1

c0

c1

cnminus1 cnminus1 cnminus1

0 1

0 1

0 1

01 0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

01

01

MUX_1L_0 MUX_1R_0

MUX_1L_1 MUX_1R_1

MUX_1L_(n) MUX_1R_(n) MUX_2R_(n)

MUX_2R_0

MUX_2R_1

MUX_3L_(n)

MUX_3L_0

MUX_3L_1

MUX_3R_(n)

MUX_3R_0

MUX_3R_1

SR-Latch_1 SR-Latch_2SR-Latch_3


MUX_2L_0

MUX_2L_1

MUX_2L_(n)


divided by the response bit length 119873 Ideally the intrachipvariation is 50 In our experiment119873 = 5 000

In order to confirm the potential of our duplication-based approach in terms of unpredictability the intrachipvariation for a Double Arbiter PUF was compared to thatof a conventional Arbiter PUF As the preliminary to thisevaluation we define 1199031 and 1199032 as two responses from twoconventional Arbiter PUFs implemented on the same chipAs shown in the second column of Table 2 the intrachipvariation of the conventional Arbiter PUF between 1199031 and1199032 was approximately 5 which is quite low These resultsimply that two Arbiter PUFs on the same chip will generatethe same responses with the probability of 95 That is 95of the responses from 2-XOR Arbiter PUF will become 0sbecause pairs with the same value are XORed It is easy topredict such responses even without machine learning Theintrachip variation of the Double Arbiter PUF was evaluatedby calculating the HD between two responses 1199031 and 1199032 froma Double Arbiter PUF as shown in Figure 6 Because theintrachip variation of the Double Arbiter PUF ismuch higherthan that of the conventional Arbiter PUF as shown in thethird column of Table 2 we can see potential of 2-1 DoubleArbiter PUF to enhance the unpredictability

43 Machine-Learning Environment The authors of [23]reported the results of a machine-learning attack based on asupport vector machine (SVM) We used an implementationof SVM called SVMlight [24] as machine-learning softwareBetween 100 and 1000 CRPs were obtained from the ArbiterPUFs on each FPGA and they were used by the SVM astraining samples For test samples 10000 challenges were

Table 2 Intrachip variation [] of Arbiter PUF and Double ArbiterPUF

FPGA Arbiter PUF Double Arbiter PUFA 534 5562B 482 3266C 492 5060

provided to the SVM and its responses were evaluatedaccording to the prediction rate The training and test sam-ples were chosen randomly With each number of trainingsamples the prediction rate of the machine-learning attackwas calculated as the average of five trials

5 Evaluation of Tolerance toMachine-Learning Attacks

First the machine-learning results from [18] are introducedin Table 3 Note that these values are the average of the resultsshown in Table 4They evaluated conventional Arbiter PUFs2-1 Double Arbiter PUFs and 3-1 Double Arbiter PUFs using1000 training samples and 10000 test samples As shownin Table 3 the prediction rate for the responses from the3-1 Double Arbiter PUF was 57 and this approximates arandom guess (ie 50)

However there are no results from119873-XOR Arbiter PUFsdesigned as countermeasures to machine-learning attacks(the results from the 119873-XOR Arbiter PUFs are shown inFigures 11 and 12) In this section we compare the 2-XOR


1st selector chain 2nd selector chain 3rd selector chain

Selector

Arbiters

F7BMUX

C6LUT

chains

SLICE SLICE SLICE SLICE SLICE SLICE






Figure 9 Design of the 3-1 Double Arbiter PUF on Xilinx Virtex-5 FPGA SR-Latches as Arbiters are fabricated by pairing the NAND withLookUp Table (LUT)

Table 3 Evaluation results of Arbiter PUF 2-1 Double Arbiter PUF and 3-1 Double Arbiter PUF

Indicators Arbiter PUF 2-1 Double Arbiter PUF 3-1 Double Arbiter PUF IdealPred rate [] 863dagger 690dagger 570dagger 50Cost (ratio) 1 2 3 mdashdaggerThese values are introduced from [18]

Arbiter PUF with the 2-1 Double Arbiter PUF and the 3-XORArbiter PUF with the 3-1 Double Arbiter PUF That is eachpair of PUFs has the same hardware cost Further becausethere are no results regarding a dependency on the numberof training samples in [18] we evaluate the four PUFsusing between 100 and 1000 training samples According to

the results from this evaluation and the intrachip variation(see Section 42) we can conclude that the Double ArbiterPUFs have more potential in terms of unpredictability Toconfirm the effectiveness of XORing responses with theDouble Arbiter PUFs we developed and evaluated a 4-1Double Arbiter PUF


Table 4 Results of the overall evaluation

Metrics FPGA ConventionalArbiter PUF

2-XORArbiter PUF

2-1 DoubleArbiter PUF

3-XORArbiter PUF


4-1 DoubleArbiter PUF Ideal

Prediction rate[] (with 1000training data)

A 8632dagger

9350 8072dagger 8582 5647dagger 561150B 8636dagger 9528 6952dagger 8595 5745dagger 5560

C 8630dagger 9541 5664dagger 8525 5675dagger 5473

Uniqueness []A with B 472Dagger 496Dagger 4136Dagger 596Dagger 5060Dagger 5046

50B with C 496Dagger

562Dagger 4970Dagger 676Dagger 5134Dagger 4986C with A 444Dagger 558Dagger 4806Dagger 632Dagger 4878Dagger 4976

Randomness[]

A 5381Dagger 632Dagger 5519Dagger 5488Dagger 5568Dagger 556750B 5653Dagger 472Dagger 3140Dagger 5505Dagger 5254Dagger 5476

C 5400Dagger 493Dagger 5063Dagger 5496Dagger 5359Dagger 5459

Steadiness []A 076Dagger 143Dagger 779Dagger 143Dagger 1411Dagger 3496

0B 083Dagger 136Dagger 1122Dagger 136Dagger 1093Dagger 1899C 045Dagger 052Dagger 1005Dagger 074Dagger 1035Dagger 2585

Cost ( ofSLICEs) mdash 177lowast 299 303lowast 426 436lowast 577 mdashdaggerThese values are introduced from [17]DaggerThe results of [18] shown in Table 3 are the averages of these valueslowastThese values are introduced from [18]

51 Challenge Model for Double Arbiter PUFs This paperaims at increasing tolerance tomachine-learning attacks withthe general delay model described in [12] and introducedin Section 22 This section discusses the validity of such amodel for Double Arbiter PUFs To do so we return to thedelay model for conventional Arbiter PUFs outlined brieflyin Section 2 Figure 10 shows part of the Double Arbiter PUFwhich has the same signal condition as Figure 3 Considera pair of challenges where one is randomly chosen and theother is 1-bit flipped In the case of a Double Arbiter PUFwhen a 1-bit flipped challenge is provided it is exchangedthrough whichever signal is supplied to right or left SR-Latchwhether the dashed or solid line Certainly the influenceof the 1-bit flipped challenge is not equivalent to that ofa conventional Arbiter PUF However when the same pairis converted into model vectors that is an original vectorand a 1-bit flipped vector the pair of signals through thedashed or solid line with the original vector has a total delaytime similar to that of the pair of signals with the 1-bitflipped vector Therefore we believe that this model is alsovalid for Double Arbiter PUFs Further our complementaryexperiments show that the prediction rate using this modelis higher than the prediction rate from using unconvertedchallenges

It seems that themodel for aDouble Arbiter PUF requirestwice as many parameters as there are additional selectorchains There is however no reason to introduce new delayparameters additionally to the conventional model sinceit is natural to assume that the delay parameters for twoduplicated selector chains have identical properties

52 2-XOR Arbiter PUF versus 2-1 Double Arbiter PUFThe results from the machine-learning attack are shown inFigure 11 Only 100 training samples were needed to predict

k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0

SR SR

Figure 10 The challenge model for the Double Arbiter PUF

10000 responses from the 2-XORArbiter PUFs on all FPGAswith approximately 95 probability This is because 95 ofthe responses were 0s as explained in Section 42 and Table 2

Although the prediction rate for the 2-1 Double ArbiterPUF with few training samples appears to be low 80 ofthe responses from the 2-1 Double Arbiter PUF on FPGAA with 1000 training samples could be predicted as shownin Figure 11(a) We cannot exclude the possibility that anattacker might predict the responses with even higher prob-ability According to the intrachip variation of the DoubleArbiter PUF on FPGA B shown in the third column ofTable 2 approximately 70 of the responses were 0s Thus


Pred

ictio

n ra

te (

)

Number of training samples

100

95

90

85

80

75

70

65

60

55

50

2-XOR Arbiter PUF2-1 Double Arbiter PUF

100 200 300 400 500 600 700 800 900 1000

(a) FPGA A


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(b) FPGA B


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(c) FPGA C

Figure 11 Prediction rates of 2-XOR Arbiter PUF and 2-1 Double Arbiter PUF

approximately 70 of these responses could be predicted onFPGAB regardless of the number of training samples as seenin Figure 11(b) As implied by these results the general delaymodel proposed in [12] can predict most of the responsesfromDouble Arbiter PUFs However we can see the potentialof the 2-1 Double Arbiter PUF in terms of unpredictabilitybecause the prediction rate on FPGA C with 1000 trainingdata was approximately 57 as shown in Figure 11(c) andbecause the tbl2-chip variation with the Double Arbiter PUFwas high as described in Section 42 with Table 2

53 3-XOR Arbiter PUF versus 3-1 Double Arbiter PUF Inorder to enhance the effectiveness of XORing responses withour duplication-based approach we can increase the numberof XORed responses The machine-learning attack resultsfrom the 3-XOR Arbiter PUF and the 3-1 Double ArbiterPUF are shown in Figure 12 The prediction rate of responsesfrom the 3-XOR Arbiter PUF on all FPGAs increased withmore training samples Approximately 85 of the responsescould still be predicted on all FPGAs By contrast even

if an attacker obtained 1000 training samples it would bedifficult to predict the responses from the 3-1 Double ArbiterPUF because its prediction rate comes close to 50 (ierandomguess)Theunpredictability of the 3-1DoubleArbiterPUF improved drastically when compared to the 2-1 DoubleArbiter PUF It is true that the large number of PUF instancesis preferable for determining the general properties of PUFsHowever considering the purpose of this paper which is toenhance unpredictability could be confirmed to some extenteven with three FPGAs since the machine-learning attack formeasuring the unpredictability is performed on each FPGAin our experiments

54 4-1 Double Arbiter PUF In order to judge the effect ofincreasing the number of XORed responses we developeda 4-1 Double Arbiter PUF with a fourth selector chain asshown in Figure 13 Figure 12 includes the machine-learningattack results for this 4-1 Double Arbiter PUF As shown inFigure 12 the tolerance of the 4-1 Double Arbiter PUF didnot increase and its resultswere comparable to the 3-1Double


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50

3-XOR Arbiter PUF3-1 Double Arbiter PUF4-1 Double Arbiter PUF

100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50


Number of training samples100 200 300 400 500 600 700 800 900 1000

Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C

Figure 12 Prediction rates of 3-XOR Arbiter PUF and 3-1 and 4-1 Double Arbiter PUF

(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ



Arbiter PUF In Section 6 we compare the 3-1 Double ArbiterPUFwith the 4-1 Double Arbiter PUF using othermetrics (asdiscussed in Section 51 it is easy to predict that most of theresponses from the 4-XORArbiter PUF will be 0 because thenumber of XORed responses is an even number)

6 Overall Evaluation of the Conventional119873-XOR Arbiter PUF and the119873-1 DoubleArbiter PUF

Previous work reported in [25 26] suggests that the con-ventional Arbiter PUF on a Xilinx Virtex-5Kintex-7Artix-7FPGA generates responses that are not particularly uniqueThe 119873-XOR Arbiter PUF [19] was designed not onlyto improve the unpredictability but also to increase thisuniqueness Further the Double Arbiter PUFs introducedin Section 3 were originally proposed as a technique forimproving the uniqueness [16] This section provides anoverall evaluation of these PUFs that includes an evaluationof the uniqueness [17] That is our evaluation establisheswhich PUF performs best in terms of device authenticationThe same FPGAs mentioned in Section 41 were used for thisexperiment namely FPGA A FPGA B and FPGA C Firstwe provide a summary of themachine-learning attack resultsusing 1000 training samples and 10000 test samples (seeTable 4) The additional metrics are defined in the followingsection

61 Other Metrics for the Overall Evaluation

611 Uniqueness When the same challenge is given to thePUFs on different chips their responses should be completelydifferent We evaluated this requirement by using the metricof uniqueness which is calculated as follows When weprovide119873 randomly chosen challenges to PUFs on two chipsthe pair of119873-bit responses is generated and we calculate theHDbetween the pairs of responsesThe uniqueness is definedas the HD divided by the response bit length 119873 Ideally theuniqueness is 50 In our experiment119873 = 5 000

612 Randomness One metric to measure the randomnessof the responses is to analyze the proportion of 1s to 0sin the responses from a PUF which should almost be thesame when randomly chosen challenges are provided In ourexperiment we counted the number of 1s in the responsesthat were generated from a PUF when 216 randomly chosenchallenges were provided The randomness is defined as thisnumber divided by the response bit length 216 Again theideal randomness is 50 (the authors of [25] refer to thismetric as uniformity)

613 Steadiness When the same challenges are provided tothe samePUFon the same chip the responses should have thesame value We evaluated this requirement by using a metricfor steadiness calculated as follows The same 119873 challengesare repeatedly given to the same PUF 119872 times and theaverage HD between two arbitrary 119873-bit responses out of119872 119873-bit responses is calculated The steadiness is defined as

this average divided by response bit length 119873 Ideally thesteadiness is 0 In our experiment 119873 = 128 and119872 = 128(the authors of [25] refer to this metric as reliability)

614 Cost It is also important to evaluate the hardware costof the PUFs We evaluated the number of occupied SLICEsduring floorplanning A lower cost is obviously better

The uniqueness randomness and steadiness of the con-ventional Arbiter PUF the 2-XOR Arbiter PUF the 2-1Double Arbiter PUF the 3-XOR Arbiter PUF and the 3-1Double Arbiter PUF were introduced from [17] to the thirdthe fourth and the fifth rows in Table 4 respectively Notethat the eighth column in Table 4 is newly introduced andprovides the evaluation results for the 4-1 Double ArbiterPUF

62 2-XOR Arbiter PUF versus 2-1 Double Arbiter PUF Theuniqueness of the 2-XOR Arbiter PUF was slightly improvedfrom that of the conventional Arbiter PUF as shown in thethird and fourth columns of Table 4 However because theconventional Arbiter PUF has relatively low uniqueness the2-XOR Arbiter PUF whose 1-bit response is obtained by twoXORing responses from two conventional Arbiter PUFs alsogenerates responses with low uniqueness By contrast theuniqueness of the 2-1 Double Arbiter PUF was higher thanthat of the 2-XOR Arbiter PUF as shown in the fourth andfifth columns of Table 4 It is clear that XORing responsesfrom the Double Arbiter PUF are more effective than thatfrom the conventional Arbiter PUF

The randomness of the 2-XOR Arbiter PUF was consid-erably low as shown in the fourth column of Table 4 Thisis because the intrachip variation was also low since 1-bitresponses generated by the twoXORing responses become 0sas discussed in Section 51The randomness of the 2-1 DoubleArbiter PUFwasmuch higher than that of the 2-XORArbiterPUF as shown in the fourth and fifth columns of Table 4

The steadiness of the 2-XOR Arbiter PUF is approxi-mately 1 as shown in the fourth column of Table 4 Wemight say that the ideal steadiness is correlated with the lowuniqueness of the 2-XORArbiter PUF that there is a trade-offbetween these two metrics The steadiness of the 2-1 DoubleArbiter PUF was around 10 and this means that it is lessstable than the 2-XOR Arbiter PUF as shown in the fourthand fifth columns of Table 4 However the steadiness of the2-1 Double Arbiter PUF was comparable to that of the SRAMPUF and the Ring Oscillator PUF reported in [14]

63 3-XOR Arbiter PUF versus 3-1 Double Arbiter PUF Theuniqueness of the 3-XORArbiter PUFwas approximately 6as shown in the sixth column of Table 4 whichmeans that theresponses were almost as unique as those from the 2-XORArbiter PUF By contrast the uniqueness of the 3-1 DoubleArbiter PUFwas approximately 50 as shown in the seventhcolumn of Table 4 and this is an ideal resultWe can concludethat the 3-1 Double Arbiter PUF utilizes XORing responseseffectively

The randomness of the 3-XOR Arbiter PUF was close tothe ideal result as shown in the sixth column of Table 4 This


is because three responses (an odd number) were XORedwith the conventional Arbiter PUFThe randomness of the 3-1DoubleArbiter PUFwas almost ideal as shown in the seventhcolumn of Table 4 and this represented an improvement overthe 2-1 Double Arbiter PUF

The steadiness of the 3-XOR Arbiter PUF was approxi-mately 1 as shown in the sixth columnof Table 4This resultis identical to that of the 2-XOR Arbiter PUF The steadinessof the 3-1 Double Arbiter PUF was less than 15 as shown inthe seventh column of Table 4 The meaning of this result isdiscussed in next section

64 4-1 Double Arbiter PUF We evaluated the 4-1 DoubleArbiter PUF described in Section 53 using the above threemetrics The uniqueness and the randomness of the 4-1Double Arbiter PUFwere almost ideal and these results werecomparable to those of the 3-1 Double Arbiter PUF as shownin the seventh and eighth columns of Table 4 However theresponses from the 4-1 Double Arbiter PUF were less stablethan those from the 3-1 Double Arbiter PUF The authors of[27] demonstrated that when the bit-error probability (iethe steadiness) of a response is less than 15 the responsecan be corrected using error-correcting code with a highlevel of probability Because the steadiness of the 3-1 DoubleArbiter PUF was less than 15 we conclude that the 3-1 Double Arbiter PUF outperformed all other PUF-basedauthentication

7 Conclusion

This paper introduced a new Arbiter PUF called the Dou-ble Arbiter PUF for enhancing the unpredictability of itsresponses First we evaluated the tolerance of the DoubleArbiter PUFs to machine-learning attacks and compared itwith the119873-XOR Arbiter PUF a well-known countermeasureagainst such machine-learning attacks Our results showedthat 85 of the responses from the conventional 3-XORArbiter PUF could be predicted with machine learning Bycontrast a 3-1 Double Arbiter PUF resulted in a predictionrate of 57 which is close to 50 (a random guess)Second we provided an overall evaluation of119873-XORArbiterPUFs and 119873-1 Double Arbiter PUFs We evaluated theseapproaches using metrics for the uniqueness randomnessand steadiness and we provided a comprehensive discussionof the results The uniqueness of the 3-1 Double Arbiter PUFwas almost ideal (50) whereas that of the conventional3-XOR Arbiter PUFs was approximately 6 Further wedesigned a 4-1 Double Arbiter PUF and evaluated it usingthe same metrics Although its tolerance and uniquenesswere almost the same as the 3-1 Double Arbiter PUF the 4-1 Double Arbiter PUF was less stable than the 3-1 DoubleArbiter PUF Consequently the 3-1 Double Arbiter PUFarchived the best performance overall However the bestparameter119873 for the119873-1 Double Arbiter PUF might dependon the implementation platform or the PUF method ThePUF designer must carefully select optimal parameters inorder to ensure the best performance

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] R S Pappu Physical one-way functions [PhD thesis] Mas-sachusetts Institute of Technology Cambridge Mass USA2001

[2] R Pappu B Recht J Taylor andN Gershenfeld ldquoPhysical one-way functionsrdquo Science vol 297 no 5589 pp 2026ndash2030 2002

[3] P Tuyls B Skoric andTKevenaar Security withNoisyData OnPrivate Biometrics Secure Key Storage and Anti-CounterfeitingSpringer New York NY USA 2007

[4] E Simpson and P Schaumont ldquoOffline hardwaresoftwareauthentication for reconfigurable platformsrdquo in CryptographicHardware and Embedded SystemsmdashCHES 2006 8th Interna-tional Workshop Yokohama Japan October 10ndash13 2006 Pro-ceedings vol 4249 of Lecture Notes in Computer Science pp 311ndash323 Springer Berlin Germany 2006

[5] J Guajardo S S Kumar G J Schrijen and P Tuyls ldquoFPGAintrinsic PUFs and their use for IP protectionrdquo in Proceedingsof the 9th International Workshop on Cryptographic Hardwareand Embedded Systems (CHES rsquo07) pp 63ndash80 Vienna Austria2007

[6] R Maes Physically Unclonable Functions Constructions Prop-erties and Applications Springer New York NY USA 2013

[7] J H Anderson ldquoA PUF design for secure FPGA-based embed-ded systemsrdquo in Proceedings of the 15th Asia and South PacificDesign Automation Conference (ASP-DAC rsquo10) pp 1ndash6 IEEETaipei Taiwan January 2010

[8] R Maes and I Verbauwhede ldquoPhysically unclonable functionsa study on the state of the art and future research directionsrdquo inTowards Hardware-Intrinsic Security pp 3ndash37 Springer BerlinGermany 2010

[9] B Gassend D Clarke M Van Dijk and S Devadas ldquoSiliconphysical random functionsrdquo in Proceedings of the 9th ACMConference onComputer andCommunications Security pp 148ndash160 Washington DC USA November 2002

[10] J W Lee D Lim B Gassend G E Suh M Van Dijk andS Devadas ldquoA technique to build a secret key in integratedcircuits for identification and authentication applicationsrdquo inProceedings of the Symposium on VLSI Circuits (VLSI rsquo04) pp176ndash179 Honolulu Hawaii USA June 2004

[11] B Gassend D Lim D Clarke M van Dijk and S DevadasldquoIdentification and authentication of integrated circuitsrdquo Con-currency Computation Practice and Experience vol 16 no 11pp 1077ndash1098 2004

[12] U Ruhrmair F Sehnke J Solter G Dror S Devadas and JSchmidhuber ldquoModeling attacks on physical unclonable func-tionsrdquo in Proceedings of the 17th ACM Conference on Computerand Communications Security (CCS rsquo10) pp 237ndash249 ChicagoIll USA October 2010

[13] U Ruhrmair J Solter F Sehnke et al ldquoPUFmodeling attacks onsimulated and silicon datardquo IEEE Transactions on InformationForensics and Security vol 8 no 11 pp 1876ndash1891 2013

[14] S Katzenbeisser U Kocabas V Rozic A-R Sadeghi I Ver-bauwhede and C Wachsmann ldquoPUFs myth fact or busted Asecurity evaluation of physically unclonable functions (PUFs)cast in siliconrdquo in Cryptographic Hardware and Embedded


SystemsmdashCHES 2012 14th International Workshop LeuvenBelgium September 9ndash12 2012 Proceedings vol 7428 of LectureNotes in Computer Science pp 283ndash301 Springer Berlin Ger-many 2012

[15] D Yamamoto K Sakiyama M Iwamoto et al ldquoA new methodfor enhancing variety and maintaining reliability of PUFresponses and its evaluation onASICsrdquo Journal of CryptographicEngineering vol 5 no 3 pp 187ndash199 2015

[16] T Machida D Yamamoto M Iwamoto and K Sakiyama ldquoAstudy on uniqueness of arbiter PUF implemented on FPGArdquoin Proceedings of the 31st Symposium on Cryptography andInformation Security (SCIS rsquo14) 2014 (Japanese)

[17] T Machida D Yamamoto M Iwamoto and K Sakiyama ldquoAnew mode of operation for arbiter PUF to improve uniquenesson FPGArdquo in Proceedings of the Federated Conference onComputer Science and Information Systems (FedCSIS rsquo14) pp871ndash878 Warsaw Poland September 2014

[18] T Machida D Yamamoto M Iwamoto and K SakiyamaldquoImplementation of double arbiter PUF and its performanceevaluation on FPGArdquo in Proceedings of the 20th Asia and SouthPacific Design Automation Conference (ASP-DAC rsquo15) pp 6ndash7Chiba Japan January 2015

[19] G E Suh and S Devadas ldquoPhysical unclonable functions fordevice authentication and secret key generationrdquo in Proceedingsof the 44th ACMIEEE Design Automation Conference (DACrsquo07) pp 9ndash14 San Diego Calif USA June 2007

[20] YHori T Yoshida T Katashita andA Satoh ldquoQuantitative andstatistical performance evaluation of arbiter physical unclon-able functions on FPGAsrdquo in Proceedings of the InternationalConference on Reconfigurable Computing and FPGAs (ReConFigrsquo10) pp 298ndash303 IEEEQuintana RooMexico December 2010

[21] XILINX ldquoVirtex-5 FPGA User Guiderdquo httpwwwxilinxcomsupportdocumentationuser guidesug190pdf

[22] National Institute of Advanced Industrial Science and Tech-nology ldquoSide-Channel Attack Standard Evaluation Board(SASEBO)rdquo httpwwwrisecaistgojpprojectsasebo

[23] G Hospodar R Maes and I Verbauwhede ldquoMachine learningattacks on 65nm arbiter PUFs accurate modeling poses strictbounds on usabilityrdquo in Proceedings of the IEEE InternationalWorkshop on Information Forensics and Security (WIFS rsquo12) pp37ndash42 Seattle Wash USA December 2012

[24] T Joachims ldquoSVM lightrdquo httpsvmlightjoachimsorg[25] AMaiti V Gunreddy and P Schaumont ldquoA systematicmethod

to evaluate and compare the performance of physical unclon-able functionsrdquo in Embedded Systems Design with FPGAs pp245ndash267 Springer New York NY USA 2012

[26] Y Hori H Kang T Katashita A Satoh S Kawamura and KKobara ldquoEvaluation of physical unclonable functions for 28-nmprocess field-programmable gate arraysrdquo Journal of InformationProcessing vol 22 no 2 pp 344ndash356 2014

[27] C Bosch J Guajardo A Sadeghi J Shokrollahi and P TuylsldquoEfficient helper data key extractor on FPGAsrdquo in Proceedings ofthe 10th InternationalWorkshop onCryptographicHardware andEmbedded Systems (CHES rsquo08) pp 181ndash197 Washington DCUSA August 2008

Submit your manuscripts athttpwwwhindawicom

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ReconfigurableComputing

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Applied Computational Intelligence and Soft Computing

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Industrial EngineeringJournal of


Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014


Human-ComputerInteraction

Advances in

Computer EngineeringAdvances in



they were evaluated using various metrics Other authorscategorize PUFs into strong PUFs and weak PUFs [5] On theone hand the former PUFs have a relatively large challengespace that is they can use many challenges making themsuitable for the device identification and authentication Therelation between challenges and responses is too complexto be accurately predicted Previous work also suggests thatthe responses from some of these PUFs can be predicted bymodeling attacks based on machine learning which uses amathematical model established by authorized CRPs Con-sequently the Arbiter PUF was once considered a candidatefor a strong PUF but has since been found to be vulnerableto such modeling attacks [12 13] On the other hand weakPUFs have either no challenge space or one that is relativelysmall Weak PUFs can be used for key generation or for somecryptographic protocols on a device because it often generatesstable responses in repeated measurements [14 15]

In this paper we discuss secureArbiter PUF implementedon FPGA (Parts of this paper are based on [16ndash18]This papernewly discusses optimal implementations for high toleranceagainst machine-learning attack along with high uniquenessand steadiness)

12 Motivation and Contribution The authors of [19] pro-posed the 119873-XOR Arbiter PUF that uses the XOR 119873responses from the 119873 Arbiter PUFs implemented on thesame chip to decrease the predictability of the responsesIn this paper we introduce a novel Arbiter PUF DoubleArbiter PUF whichwas originally proposed as a technique forgenerating highly unique responses [16] We expect that ourDouble Arbiter PUF will be a valid approach for enhancingunpredictability even on FPGAs that have wiring problem(see Section 3 below) The authors of [17] proposed 2-1Double Arbiter PUF whose response is obtained by twoXORing responses from the Double Arbiter PUF 3-1 DoubleArbiter PUF was also proposed in [17] This PUF has a thirdbuilding block and its response is generated by six XORingresponses from these building blocks Although the authorsof [18] considered the tolerance of conventional ArbiterPUF and Double Arbiter PUFs to machine-learning attacksthey did not compare them with the 119873-XOR Arbiter PUFFurther there were no results that showed a dependency onthe number of training samples in [18] We newly evaluate119873-XOR Arbiter PUFs and Double Arbiter PUFs accordingto this tolerance by using between 100 and 1000 trainingsamples In order to clarify the reasonwhy theDoubleArbiterPUF is more effective than the conventional119873-XOR ArbiterPUF at XORing responses for adding the unpredictabilitywe evaluate these PUFs according to intrachip variationa metric defined in this paper Our experimental resultsshow that the intrachip variation of Double Arbiter PUFsis much higher than that of the conventional Arbiter PUFand that its tolerance against machine-learning attacks is alsorelatively high regardless of number of training samplesIn particular it is difficult to predict responses from the 3-1 Double Arbiter PUF because the prediction rate of theresponses for randomly chosen challenges is approximately57 and this is close to 50 random guess

XORing responses from multiple PUFs within the samechip can be also expected to increase the interchip dif-ference among chips that has been evaluated according touniqueness [20] We introduce the results from [17] regardinguniqueness and confirm that the uniqueness of the DoubleArbiter PUFs is almost ideal and much higher than that ofconventional 119873-XOR Arbiter PUFs In this paper we newlypropose 4-1 Double Arbiter PUF that has a fourth buildingblock The response from this PUF is generated by moreXORing responses than the 3-1 Double Arbiter PUF Fromour experimental results we demonstrate the proposed PUFrsquostolerance to machine-learning attacks and its uniquenessboth of which are comparable to the 3-1 Double Arbiter PUFA high level of stability in the responses is also needed whenrepeating the same challenge for the device authenticationusing PUFs a metric referred to as steadiness [20] Becauseour results show low steadiness in the 4-1 Double ArbiterPUF we conclude that the 3-1 Double Arbiter PUF is themostsuitable PUF for device authentication

Our contributions are summarized as follows(i) We show that the 3-1 Double Arbiter PUF has much

higher tolerance tomachine-learning attacks than theconventional119873-XOR Arbiter PUF

(ii) We also conclude that the 3-1 Double Arbiter PUFdemonstrates the best performance from among theintroduced PUFs in terms of tolerance uniquenessand steadiness

13 Organization of This Paper Section 2 shows the relatedwork the structure of conventional Arbiter PUFs the reasonwhy conventional Arbiter PUFs are vulnerable to machine-learning attacks and their countermeasures In Section 3 weintroduce the Double Arbiter PUFs as an alternative coun-termeasure Our experimental environment and the metricsfor our evaluation including the intrachip variation aredescribed in Section 4 Section 5 compares the conventionalArbiter PUF with the Double Arbiter PUF in terms of theirtolerance to machine-learning attacks Section 6 provides theresults from a performance evaluation based on [17] anddiscusses the feasibility of the introduced PUFs for deviceauthentication Finally we conclude the paper in Section 7

2 Related Work

21 Arbiter PUF The Arbiter PUF proposed in [10 11]consists of selector pairs connected in a series and anArbiter (an SR-Latch is used as shown in Figure 1) thatdetermines its response as shown in Figure 1 First an inputsignal is supplied to the first left and right selectors at thesame time The genetic idea behind Arbiter PUFs is to racethe delay times between the two signals The two signalspropagate through various routes depending on the valueof the challenges These routes are determined by an 119899-bitchallenge that is given as the selection input for the selectorpairsThe (119894+1)th challenge bit 119888

119894out from the 119899-bit challenge

corresponds to the selection inputs for the (119894 + 1)th selectorpair where 119894 = 0 1 119899 minus 1 When 119888

119894= 1 two output

signals from the 119894th selector pair are crossed and supplied to


0 01

0 1

0 1

1

01

01

RSQ Q

r

c0

c1

cnminus1






119903 = sgn (w119879120593) (1)




Pairc r

Training

Parameterw

Classification

120593998400 Inputr998400 = sgn(wT 998400)

c998400

r998400

phase phase

Featureextraction

Featureextraction

120593

120593





120593119894=

119899

prod

119896=119894

(1 minus 2119888119896) (119894 = 1 2 119899)

1 (119894 = 119899 + 1)

(2)



1199031015840= sgn (w1198791205931015840) (3)







k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0







c0 0 01 1

01

01

0 1

0 1

010 1

010 1


S R

Q Q

S R

Q Q

c1

c0

c1

r










F7BMUX


Pair of NAND in

SR-Latch 1

C6LUT


r

S R

QQ

S R

QQ

S R

QQ

c0

c1

cnminus1

0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01

c0

c1

cnminus1

c0

c1

cnminus1


r1 r2

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1




r

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1




r

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

c0

c1

c0

c1

c0

c1


0 1

0 1

0 1

01 0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

01

01

MUX_1L_0 MUX_1R_0

MUX_1L_1 MUX_1R_1


MUX_2R_0

MUX_2R_1

MUX_3L_(n)

MUX_3L_0

MUX_3L_1

MUX_3R_(n)

MUX_3R_0

MUX_3R_1



MUX_2L_0

MUX_2L_1

MUX_2L_(n)













Selector

Arbiters

F7BMUX

C6LUT

chains















2-XORArbiter PUF


3-XORArbiter PUF




A 8632dagger






Randomness[]









k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0

SR SR





Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(b) FPGA B


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(c) FPGA C







Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C


(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ






















7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in




0 01

0 1

0 1

1

01

01

RSQ Q

r

c0

c1

cnminus1






119903 = sgn (w119879120593) (1)




Pairc r

Training

Parameterw

Classification

120593998400 Inputr998400 = sgn(wT 998400)

c998400

r998400

phase phase

Featureextraction

Featureextraction

120593

120593





120593119894=

119899

prod

119896=119894

(1 minus 2119888119896) (119894 = 1 2 119899)

1 (119894 = 119899 + 1)

(2)



1199031015840= sgn (w1198791205931015840) (3)







k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0







c0 0 01 1

01

01

0 1

0 1

010 1

010 1


S R

Q Q

S R

Q Q

c1

c0

c1

r










F7BMUX


Pair of NAND in

SR-Latch 1

C6LUT


r

S R

QQ

S R

QQ

S R

QQ

c0

c1

cnminus1

0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01

c0

c1

cnminus1

c0

c1

cnminus1


r1 r2

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1




r

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1




r

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

c0

c1

c0

c1

c0

c1


0 1

0 1

0 1

01 0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

01

01

MUX_1L_0 MUX_1R_0

MUX_1L_1 MUX_1R_1


MUX_2R_0

MUX_2R_1

MUX_3L_(n)

MUX_3L_0

MUX_3L_1

MUX_3R_(n)

MUX_3R_0

MUX_3R_1



MUX_2L_0

MUX_2L_1

MUX_2L_(n)













Selector

Arbiters

F7BMUX

C6LUT

chains















2-XORArbiter PUF


3-XORArbiter PUF




A 8632dagger






Randomness[]









k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0

SR SR





Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(b) FPGA B


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(c) FPGA C







Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C


(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ






















7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in




k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0







c0 0 01 1

01

01

0 1

0 1

010 1

010 1


S R

Q Q

S R

Q Q

c1

c0

c1

r










F7BMUX


Pair of NAND in

SR-Latch 1

C6LUT


r

S R

QQ

S R

QQ

S R

QQ

c0

c1

cnminus1

0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01

c0

c1

cnminus1

c0

c1

cnminus1


r1 r2

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1




r

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1




r

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

c0

c1

c0

c1

c0

c1


0 1

0 1

0 1

01 0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

01

01

MUX_1L_0 MUX_1R_0

MUX_1L_1 MUX_1R_1


MUX_2R_0

MUX_2R_1

MUX_3L_(n)

MUX_3L_0

MUX_3L_1

MUX_3R_(n)

MUX_3R_0

MUX_3R_1



MUX_2L_0

MUX_2L_1

MUX_2L_(n)













Selector

Arbiters

F7BMUX

C6LUT

chains















2-XORArbiter PUF


3-XORArbiter PUF




A 8632dagger






Randomness[]









k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0

SR SR





Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(b) FPGA B


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(c) FPGA C







Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C


(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ






















7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in






F7BMUX


Pair of NAND in

SR-Latch 1

C6LUT


r

S R

QQ

S R

QQ

S R

QQ

c0

c1

cnminus1

0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01 0 1

0 1

0 01 1

01

01

c0

c1

cnminus1

c0

c1

cnminus1


r1 r2

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1




r

S RQQ

S RQQ

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1

0 1

0 1

0 1

01

01

01

c0

c1

cnminus1




r

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

c0

c1

c0

c1

c0

c1


0 1

0 1

0 1

01 0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

01

01

MUX_1L_0 MUX_1R_0

MUX_1L_1 MUX_1R_1


MUX_2R_0

MUX_2R_1

MUX_3L_(n)

MUX_3L_0

MUX_3L_1

MUX_3R_(n)

MUX_3R_0

MUX_3R_1



MUX_2L_0

MUX_2L_1

MUX_2L_(n)













Selector

Arbiters

F7BMUX

C6LUT

chains















2-XORArbiter PUF


3-XORArbiter PUF




A 8632dagger






Randomness[]









k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0

SR SR





Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(b) FPGA B


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(c) FPGA C







Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C


(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ






















7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in




r

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

S R

QQ

c0

c1

c0

c1

c0

c1


0 1

0 1

0 1

01 0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

0 1 01

01

01

MUX_1L_0 MUX_1R_0

MUX_1L_1 MUX_1R_1


MUX_2R_0

MUX_2R_1

MUX_3L_(n)

MUX_3L_0

MUX_3L_1

MUX_3R_(n)

MUX_3R_0

MUX_3R_1



MUX_2L_0

MUX_2L_1

MUX_2L_(n)













Selector

Arbiters

F7BMUX

C6LUT

chains















2-XORArbiter PUF


3-XORArbiter PUF




A 8632dagger






Randomness[]









k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0

SR SR





Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(b) FPGA B


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(c) FPGA C







Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C


(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ






















7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in





Selector

Arbiters

F7BMUX

C6LUT

chains















2-XORArbiter PUF


3-XORArbiter PUF




A 8632dagger






Randomness[]









k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0

SR SR





Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(b) FPGA B


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(c) FPGA C







Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C


(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ






















7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in






2-XORArbiter PUF


3-XORArbiter PUF




A 8632dagger






Randomness[]









k

i

n minus 3

n minus 3

n minus 2

n minus 2

n minus 1

n minus 1

n

1

1

1

1

1

1

minus1

n

n + 1


0

0

SR SR





Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(b) FPGA B


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(c) FPGA C







Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C


(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ






















7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in




Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(b) FPGA B


Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50100 200 300 400 500 600 700 800 900 1000

(c) FPGA C







Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C


(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ






















7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in




Pred

ictio

n ra

te (

)


100

95

90

85

80

75

70

65

60

55

50


100 200 300 400 500 600 700 800 900 1000

(a) FPGA A

100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(b) FPGA B100

95

90

85

80

75

70

65

60

55

50



Pred

ictio

n ra

te (

)

(c) FPGA C


(i)(i) (i)

(i)

(ii) (ii) (ii)

(ii)

(iii) (iii) (iii)

(iii)

(iv) (iv)(iv)

(iv)

r

c0

c1

cnminus1

0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01 0 1

0 1 01

0 1 01

01

c0

c1

cnminus1

c0

c1

cnminus1

c0

c1

cnminus1

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ

S RQQ






















7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in























7 Conclusion




References





































Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in

























Advances in

FuzzySystems


Volume 2014












Journal of

Journal of





Advances in

Multimedia


Biomedical Imaging



Advances in


RoboticsJournal of










Advances in



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