mipi devcon 2016: how to use the vesa display stream compression (dsc) standard to create higher...

VESA Display Stream

Compression (DSC) How to Use the VESA Display Stream

Compression (DSC) Standard to Create Higher Resolution Displays for

Consumer Electronics Applications

Alain Legault, Hardent, Inc.

Agenda • What Is DSC?

•  DSC in Consumer Electronics Applications

•  How To Integrate DSC In Your Next Semiconductor Design

PART 1: WHAT IS DSC?

Why Is DSC Needed?

Mobileapplica+onprocessorMIPIDSIDDIC

ComputerGPUcardDisplayPortcableComputermonitor

Carapplica+onprocessorProprietarytransportCarinfotainmentdisplay

Processor TXPort

DisplayModule

RXPort

ToDisplayVideoIn

2011 2012 2013 2014 2015 2016

WXGA HD FHD QHD UHD 5K

Mind the Gap

PHY trend +20%/year

PHY per Lane Gb/s

Display resolution CAGR >2x / year

MPixels

1.0

2.0

3.0

4.0

5.0

Source: Dale Stolitzka & David Hoffman Samsung Display Company

1444

12

10

8

6

4

2

0

Compression Power & Area Trade-off

SWEETSPOT2x–3xcompression


Increase In Available Bandwidth

Time PHYSpeed

BitCoding(8b/10b!128b/

132b)

ImageCoding

LinkSpeed

T=0 1x 1x 1x 1x

T+2years 1.44x 1,23x 2x–3x 3.5–5x

PHYBit

Coding(ifapplicable)

ImageCoding

PixelData

LinkPayload

PHY Speed / Display Resolution

ResoluYonFHD

(1080x1920)WQHD

(1440x2560)WQXGA

(1600x2560)UHD

(2160x3840)WQUXGA

(2400x3840)5K

(2880x5120)8K

(4320x8192)

Bandwidth 3.58Gbps 6.37Gbps 7.08Gbps 14.33Gbps 15.93Gbps 25.49Gbps 61.16Gbps

Nocompression 3lanes 6or8lanes 6or8lanes N/A N/A N/A N/A

2xcompression 2lanes 3lanes 3lanes 8or6lanes 8or6lanes N/A N/A

3xcompression 1lane 2lanes 2lanes 4lanes 4lanes 8lanes N/A

D-PHYv1.11.5Gbps/lane

ResoluYonFHD

(1080x1920)WQHD

(1440x2560)WQXGA

(1600x2560)UHD

(2160x3840)WQUXGA

(2400x3840)5K

(2880x5120)8K

(4320x8192)

Bandwidth 3.58Gbps 6.37Gbps 7.08Gbps 14.33Gbps 15.93Gbps 25.49Gbps 61.16Gbps

Nocompression 2lanes 3lanes 3lanes 8or6lanes 8lanes N/A N/A

2xcompression 1lane 2lanes 2lanes 3lanes 4lanes 8or6lanes N/A

3xcompression 1lane 1lane 1lane 2lanes 3lanes 4lanes N/A

D-PHYv1.22.5Gbps/lane

DSI Link Compression

TXPort

RXPort

ToDisplay

Processor

GPU

DSCEncoder

DSCDecoder

DisplayModule

FrameBuffer

VideoIn

VESA DSC Task Group - 2013

VESA DSC Task Group: Work Completed

•  Call for proposals in the industry •  Six proposals were presented •  Selection committee

•  Reviewed proposals •  Conducted video quality tests using various types of content (images,

text, and graphics) •  Broadcom BDC algorithm was chosen •  Liaison committee with the MIPI Alliance •  Several image quality test iterations and algorithmic

improvements •  DSC C-model golden reference code

•  Version 31 was released

VESA DSC Standard

January2013

DSCTaskGroupFormed

April2014

DSCAnnounced

July2014

DSCv1.1Released

January2016

DSCv1.2Released

VESA DSC Task Group - 2016

Overview of DSC Algorithm

Overview of DSC Algorithm

•  Intra-frame Constant Bit Rate (CBR) encoder • Based on Delta Pulse Code Modulation (DPCM) • Mid Point (MPP), Block Predictor (BP) • Modified Median Adaptive Predictor (MMAP) •  Indexed Color History (ICH) • Requires a single line of pixel storage + rate buffer • Visually lossless compression between 2X – 3X • Video quality excellent with all types of content

• Natural and test images, text and graphics

Subjective Testing Evaluates Image Quality

ISO/IEC IS 29170-2 test method

Ref Test

Ref Test

Ref Test

Ref vs. 5Hz


Objective Metrics Do Not Predict Performance

Mean response fraction Mean response fraction

log 1

0(H

DR

VD

P2)

PSN

R

PSNR = peak signal to noise ratio HDR VDP2 = high dynamic range visual difference predictor #2

Visually lossless Barely perceptible

Impaired


Subjective Testing Guidelines

E = 30 pixels/degree (PPD) 5⁰


ISO/IECIS29170-2

Display Conditions

ISO 3664, ISO 9241-303

Monitor Calibrated monitor

Color sRGB, BT.709, BT.2010

Viewing Distance

Distance at 30 PPD

EvaluaYonprocedurefornearlylosslesscoding

Image Viewing

1:1 side/side or interleaved

Image Sets

Wide set of images, graphics, text and engineered images

Video Sets

SVT fairytale and game screen captures

ISO/IECIS29170-2Evalua+onprocedurefornearlylosslesscoding

Why Adopt DSC?

DSC Helps Save Power, Area, and Cost

MIPIDSITransportLanes

DSCEncoder

MIPIDSITx

ApplicaYonProcessor

MIPIDSITx

MIPIDSIRx

MIPIDSIRx

DSCDecoder

SDRAM

DisplayDriverIC

FrameBuffer

SDRAM SDRAM



DSCEncoder

MIPIDSITx

ApplicaYonProcessor

MIPIDSITx

MIPIDSIRx

MIPIDSIRx

DSCDecoder

SDRAM

DisplayDriverIC

FrameBuffer

SDRAM SDRAM

RemoveMIPITx+PHYMIPIRx+PHY



DSCEncoder

MIPIDSITx

ApplicaYonProcessor

MIPIDSITx

MIPIDSIRx

MIPIDSIRx

DSCDecoder

SDRAM

DisplayDriverIC

FrameBuffer

SDRAM

RemoveSDRAMs SDRAM



DSCEncoder

MIPIDSITx

ApplicaYonProcessor MIPIDSI

Rx

DSCDecoder

DisplayDriverIC

FrameBuffer

SDRAM

LesspowerSmallerfootprintLowercost

Transport Standards Using DSC

MIPI®DSI1.2

eDisplayPort™1.4b

DisplayPort™1.4

DSC Standard Availability and Support

Source: VESA

Products Using DSC

QualcommSnapdragon820 NVIDIATegraX1

PART 2: DSC IN CONSUMER ELECTRONICS APPLICATIONS

DSCDecoder

DisplayDriverIC


ApplicaYonProcessor

MIPIDSIandD-PHY

MIPIDSIandD-PHY

DSCEncoder

GPU

Use Case: Mobile and Tablet Applications •  Application processor •  DDIC (Display Driver IC) and touch

panel controller

High-DefiniYonDisplay

Source: MIPI Alliance

Use Case: In-car Video Applications

•  Application processor •  Infotainment display

module •  Video cameras •  HDMI sources •  Ability to transport

multiple video sources simultaneously

•  Automotive serial interfaces and transport

DISPLAY Display I / F

MIPI DSI Enet

I / F IP Decap Disp

Ctlr DSC Dec

Telematic Hub

Hub

Infotainment Hub

Hub Hub Hub

Sensor I / F MIPI I 3 C IP

Encap Enet I / F SENSOR

Camera I / F MIPI CSI Enet

I / F IP Encap ISP DSC

Enc CAMERA

Use Case: AR / VR Head-Mounted Display

•  Video capture •  Application

processor and GPU

•  Micro-display driver IC

SDRAM SDRAM SDRAM

Shared Memory Bus

APU / GPU

DSC Encoder

DSC Decoder

Capture System

DSC Encoder

DMA Ctrl

MIPI CSI

MIPI CSI

µ Display L µDisplay R

LPDDR

ISP

ISP DMA Ctrl

DMA Ctrl

µ Display Driver

DSC Decoder

DMA Ctrl

MIPI DSI

MIPI DSI

Display Controller Display

Controller

Use Case: USB Type-C Laptop & Extended Display (1)

•  USB Type-C triple use •  Peripheral •  DisplayPort (Alt Mode) •  Power delivery

•  Shared bandwidth •  Ex. Dual external monitors

USB type-C DP 1.4 transport •  Storage •  Networking

•  DSC usage saves bandwidth for other external devices (storage, networking)

DisplayPortAlt-ModeforUSBType-CImage source: Cadence

Use Case: USB Type-C Laptop & Extended Display (2)

•  Laptop with GPU •  Dual external

monitors •  USB Type C

DisplayPort 1.4 transport

Peripheral ( Storage , etc ) Peripheral ( Storage , etc )

Internal Display

CPU

GPU

DP Tx DSC

Encoder

eDP Tx

USB - C Ethernet

WIFI I / F

Display Driver IC

eDP Rx

Display Driver IC

SDRAM SDRAM SDRAM

DP Rx DSC

Decoder Display

4 K @ 60 Hz

External Monitor # 1

USB / DP I / F

USB Hub

DDR Ctrl

Laptop

Single USB Type - C

Connector

Display Driver IC

DP Rx DSC

Decoder Display

4 K @ 60 Hz

External Monitor # 2

Peripheral ( Storage , etc ) USB - C Peripheral

( Storage , etc ) USB - C

Use Case: Professional Video Transport

•  Compression of UHD signals allows transport over inexpensive Ethernet links •  Ex. UHD (14.33Gbps) over

10GE with 2:1 compression

Encoder System

DSC Encoder

Video Interface

IP Encapsulation

Video Input Uncompressed Video

Ethermet I / F

Video Ouput Uncompressed Video

Decoder System

DSC Decoder

Video Interface

IP Decapsulation

Ethermet I / F

Use Case: 8K Digital TV

•  TVs, STBs, and DVRs •  Multimedia SoC

processor •  TCON (Timing controller) •  Inside 8K TV •  Based on DSC 1.2

Ethernet

DISPLAY 8 K @ 60 Hz

TCON IC

Multimedia SoC DDR

Controller

Audio

CPU

GPU

H . 264 / 5 Video / Audio

Decoder DTV

Tuner I / F

eDP Tx DSC

Encoder

Ethernet I / F WIFI

I / F

eDP Rx DSC

Decoder

RF

USB - Type C or DisplayPort 1 . 4

Over USB - C Alt Mode

4 x 10 Gb / s lanes

S / PDIF USB - C

TS DeMUX

DP Rx DSC

Decoder

SDRAM SDRAM SDRAM

HDMI HDMI

PART 3: HOW TO INTEGRATE DSC IN YOUR NEXT SEMICONDUCTOR DESIGN

DSC Encoder and Decoder IP

DSCEncoder DSCDecoder

How Are Images Processed by DSC?

1VerYcalSlice2VerYcalSlices4VerYcalSlices

Use Case: Two Vertical Slices

•  Example: 4K video 60 fps

•  ASIC with pixel clock at 350 MHz

•  Each slice = 350 Mpixels / sec

•  Two vertical slices are needed

•  Number of slices need to match between DSC Encoder and Decoder

DSCEncoder DSCDecoder

Single DSC – Single DSI Stream Solution

1600x2560x60fps7Gbps

Dual DSC – Dual DSI Stream Solution

2400x3860x60fps16Gbps

Conformance Test Guideline (CTG)

UncompressedSourcePicture

CompressedPicture

ReconstructedDisplayPictureDSCEncoder DSCDecoder

CRCUncompressedSourcePicture

CRCCompressed

Picture

CRCReconstructedPixelStream

FPGA Prototyping

Further Reading •  DSC white paper

•  http://www.vesa.org/wp-content/uploads/2014/04/VESA_DSC-ETP200.pdf

•  DSC standard •  http://www.vesa.org/vesa-standards/

•  VESA membership •  http://www.vesa.org/join-vesamemberships/

Alain Legault Hardent Inc.

[email protected] www.hardent.com