Modeling of HEMT

By:Sandeep MandavaUnder the guidance of Prof(Dr) J.P. Raina

Index

• Objective

• Structure of HEMT

• Literature Survey and current status

• Project Schedule

• List of references

Objective

• To design a HEMT at a gate length below 22nm(current status) which can

sustain beyond an Ft=562GHz(current status).

150nm

Structure of HEMT

Ref: [1-4,6,9,10]

Literature Survey and current status

Ref:[3] Dae-Hyun Kim and Jesús A. del Alamo, “Beyond CMOS: Logic Suitability of In0.7Ga0.3As HEMT” CS MANTECH Conference, April 24-27, 2006, Vancouver, British Columbia, Canada.

Ref:[3] Dae-Hyun Kim and Jesús A. del Alamo, “Beyond CMOS: Logic Suitability of In0.7Ga0.3As HEMT” CS MANTECH Conference, April 24-27, 2006, Vancouver, British Columbia, Canada.

Ref:[1] D.-H. Kim and J. A. del Alamo, “Lateral and vertical scaling of In0.7Ga0.3As HEMTs for post-Si-CMOS logic applications,” IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2546–2553, Oct. 2008.

Ref:[1] D.-H. Kim and J. A. del Alamo, “Lateral and vertical scaling of In0.7Ga0.3As HEMTs for post-Si-CMOS logic applications,” IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2546–2553, Oct. 2008.

Ref:[1] D.-H. Kim and J. A. del Alamo, “Lateral and vertical scaling of In0.7Ga0.3As HEMTs for post-Si-CMOS logic applications,” IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2546–2553, Oct. 2008.

Ref[1] D.-H. Kim and J. A. del Alamo, “Lateral and vertical scaling of In0.7Ga0.3As HEMTs for post-Si-CMOS logic applications,” IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2546–2553, Oct. 2008.

Ref: [14] Naoki hara, Tsuyoshi Takahashi, Toshihiro Ohki, and Kozo Makiyama “Inp-based HEMTs suitable for ultra high speed MMIC's Fabrication” ECS Transactions, 16(7) 35-42(2008)

Ref: [14] Naoki hara, Tsuyoshi Takahashi, Toshihiro Ohki, and Kozo Makiyama “Inp-based HEMTs suitable for ultra high speed MMIC's Fabrication” ECS Transactions, 16(7) 35-42(2008)

Ref: [14] Naoki hara, Tsuyoshi Takahashi, Toshihiro Ohki, and Kozo Makiyama “Inp-based HEMTs suitable for ultra high speed MMIC's Fabrication” ECS Transactions, 16(7) 35-42(2008)

Ref:[8] E. Hwang, S. Mookerjea, M. K. Hudait and S. Datta “Scalability Study of Ino.7Ga0.3As HEMTs for 22nm node and beyond Logic Applications” ©2010 IEEE.

Project Schedule

0th Review From Sep1-Sep30 (30days)2010

Literature survey, understanding the current status and identifying the

problem areas1St Review From Oct1-Nov30(60 days)

2010Simulating the current

models and verification of their characteristics using

Synopsys 2nd Review From Dec 1-Jan 31(61 days)

2011Scaling the models up to 22nm verification of the

characteristics new problem identification

3rd Review From Feb1-April11(70days) 2011

Work on the identified problem area of HEMT

better than 22nm and verify the design for further

improvement and write a technical paper for

publication

Review Time allocated Work to be done

References

1. D.-H. Kim and J. A. del Alamo, “Lateral and vertical scaling of In0.7Ga0.3As HEMTs for post-Si-CMOS logic applications,” IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2546–2553, Oct. 2008.

2. Dae-Hyun Kim and Jesús A. del Alamo, “Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010.

3. Dae-Hyun Kim and Jesús A. del Alamo, “Beyond CMOS: Logic Suitability of In0.7Ga0.3As HEMT” CS MANTECH Conference, April 24-27, 2006, Vancouver, British Columbia, Canada.

4. Serge Oktyabrsky • Peide D. Ye “Fundamentals of III-V Semiconductor MOSFETs” ISBN 978-1-4419-1546-7 e-ISBN 978-1-4419-1547-4 DOI 10.1007/978-1-4419-1547-4 Springer New York Dordrecht Heidelberg London

5. Keisuke Shinohara, Yoshimi Yamashita, AkiraEndoh, Issei Watanabe, Kohki Hikosaka, Takashi Mimud, Satoshi Hiyamizu, andToshiaki Matsui “Nanogate InP-HEMT Technology for Ultrahigh-speed Performance” 2004 International Conference on Indium Phoshide and Related Materials Conference Proceedings 16th IPRM 31, May - 4, June 2004 Kagoshima, Japan.

6. Dae-Hyun Kim, Jesús A. del Alamo, Jae-Hak Lee, and Kwang-Seok Seo “The Impact of Side-Recess Spacing on the Logic Performance of 50 nm In0.7Ga0.3As HEMTs”.

7. Robert Chau, Suman Datta, and Amlan Majumdar “Opportunities and Challenges of III-V Nanoelectronics for Future High-Speed, Low-Power Logic Applications” CSIC 2005 Digest.

8. E. Hwang, S. Mookerjea, M. K. Hudait and S. Datta “Scalability Study of Ino.7Ga0.3As HEMTs for 22nm node and beyond Logic Applications” ©2010 IEEE.

9. J.Brad Boos,Ming-Jey Yang,Brian R.Bennett,Doewon Park,Kruppa “Channel Design to reduce Impact Ionization in Hetero structure Field Effect Transistor” Patent number 6,1333,593; Date of patent:oct 17,2000.

10. Partha Mukhopadhyay , Sudip Kundu, Palash Das, Saptarshi, Pathak, Edward Y. Chang and Dhrubes Biswas “W-band Penta-Composite Channel InAlAs/InGaAs Metamorphic HEMT for High Power Application and Comparison with Pseudomorphic HEMT” CS MANTECH Conference, May 17th-20th, 2010, Portland, Oregon, USA.

11. Alexander N. Ernst, Mark H. Somerville, and Jes´us A. del Alamo, Senior Member, IEEE “Dynamics of the Kink Effect in InAlAs/InGaAs HEMT’s” IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 12, DECEMBER 1997.

12. J. A. del Alamo and D.-H. Kim, “ The prospects for 10 nm III-V CMOS” ©2010 IEEE13. von Helmut Brech “Optimization of GaAs based High Electron Mobility Transistors by

Numerical Simulations” Dissertation München , im März 199814. Naoki hara, Tsuyoshi Takahashi, Toshihiro Ohki, and Kozo Makiyama “Inp-based HEMTs

suitable for ultra high speed MMIC's Fabrication” ECS Transactions, 16(7) 35-42(2008)

THANK YOU