modified new lut
TRANSCRIPT
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Project Seminar on
New Approach to Look-Up-Table Design &Memory-Based Realization of FIR Digital Filter
Presented By SARADA A
Reg.No: 010911407 Class:M.E(PTPG)
• Digital Systems (ECE )• UCE(Autonomous), OU • Internal Guide
Dr.P.Chandra Sekhar Associate Professor,
Dept of ECE, UCE(Autonomous),OU
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Contents
Aim of the Project
Technical Approach
Introduction
DA based Approach
Conventional LUT based Apporach
Proposed Method
Simulation Results
Conclusion
References
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Aim of the projectTo design an LUT using the proposed
new approachImplementation of the proposed LUT
based FIR Filter and comparing with the existing design.
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Technical ApproachThe project is implemented using VHDL and
Simulated for its Functional Verification
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Introduction FINITE-IMPULSE response (FIR) digital filter is widely used
as a basic tool in various digital signal processing applications
The order of an FIR filter primarily determines the width of the transition-band . The higher the filter order, the sharper is the transition between a pass-band and adjacent stop-band.
Many applications in digital signal processing require large order FIR filters Since the number of (MAC) operations required per filter output increases linearly with the filter order, real-time implementation of these filters of large orders is a challenging task.
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The memory-based computing structures are more regular than the multiply-accumulate structures; and offer many other advantages over MAC structures like greater potential for high throughput and low-latency implementation; and less dynamic power consumption.
Memory-based computing is well-suited for many digital signal processing (DSP) algorithms, which involve multiplication with fixed set of coefficients.
There are two basic variants of memory-based techniques.
Distributed arithmetic (DA) for inner product computation
Computation of multiplication by look-up-table (LUT)
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DA based Approach
The “basic” DA technique is bit-serial in natureDA is basically a bit-level rearrangement of the
multiply and accumulate operation.DA hides the explicit multiplications by ROM
look-ups an efficient technique to implement on Field Programmable Gate Arrays (FPGAs).
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DA Based Approach contd..
Let xk consisits of N-bits xk : {bk(N-1), ……bk2,bk1,bk0 }
K
kkk xAy
1
1
0
2N
n
nknk bx
…(1)
…(2)
K
k
N
n
nknk bAy
1
1
0
2
K
k
N
n
nknk bAy
1
1
0
2 …(3)
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DA Based Approach contd..
K
k
N
n
nkkn Aby
1
1
0
2
112
21
1
1212
2222
1121
1111
2112
1111
0220110
222
222
222
NKNKKKKK
NN
NN
KK
AbAbAb
AbAbAb
AbAbAb
AbAbAby
K
k
NNkkkkkkkk bAbAbAAby
1
)1()1(
22
110 222
…(3)
Expanding this part
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DA Based Approach contd..
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DA Based Approach contd..
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DA Based Approach contd..
1
0 1
2N
n
nK
kknk bAy
K
k
N
n
nkkn Aby
1
1
0
2
Bit Level Rearrangement
Original Equation
Modified Equation
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DA Based Approach contd..In the DA-based approach, an LUT is used to
store all possible values of inner-products of a fixed -point vector with any possible -point N bit-vector.
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Address and Contents of Look Up Table
LUT
If the inner-products are implemented in a straight-forward way the memory-size of the DA-based approach increases exponentially with the inner-product-length.
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Conventional LUT Based Approach
Conventional LUT Multiplier
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Conventional LUT based Approach contd..
In the LUT-multiplier-based approach, multiplications of input values with a fixed-coefficient are performed by an LUT consisting of all possible pre-computed product values corresponding to all possible values of input multiplicand.
If the inner-products are implemented in a straight-forward way, the memory-size of LUT-multiplier based implementation increases exponentially with the word length of input values.
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In the proposed LUT based multiplier the multiplication of an L -bit input with W-bit coefficient is carried out by the following strategy:
A memory-unit of 2L/2 words of (W+L) -bit width is used to store all the odd multiples of A.
A barrel-shifter for producing a maximum of (L-1)leftshifts is used to derive all the even multiples of A .
The L-bit input word is mapped to (L-1) -bit LUT-address by an encoder.
The control-bits for the barrel-shifter are derived by a control-circuit to perform the necessary shifts of the LUT output.
A RESET signal is generated by the same control circuit to reset the LUT output when X=0000.
The Proposed LUT Based Approach
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Proposed LUT design for multiplication of W-bit fixed coefficient(A) and 4-bit input operand(X)
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The 4-to-3 bits input encoder
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Control Circuit Structure of NOR Cell
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Simulation Results
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ConclusionThe proposed LUT-based-multiplication reduces
the LUT-size over that of conventional design by making use of odd-multiple-storage scheme.
For address-length 4, the LUT size is reduced to half by using a two-stage logarithmic barrel-shifter and (w+4) number of NOR gates, where W is the word-length of the fixed multiplying coefficients.
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References P. K. Meher, “New look-up-table optimizations for memory-based
multiplication,” in Proc. Int. Symp. Integr. Circuits (ISIC’09), Dec.2009, to be published.
P. K. Meher, “New approach to LUT implementation and accumulation for memory-based multiplication,” in Proc. 2009 IEEE Int. Symp. Circuits Syst., ISCAS’09, May 2009, pp. 453–456
H. Yoo and D. V. Anderson, “Hardware-efficient distributed arithmetic architecture for high-order digital filters,” in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing, (ICASSP’05), Mar. 2005, vol. 5, pp. v/125–v/128.
J. G. Proakis and D. G. Manolakis, Digital Signal Processing: Principles, Algorithms and Applications. Upper Saddle River, NJ: Prentice- Hall, 1996.
H. H. Dam, A. Cantoni, K. L. Teo, and S. Nordholm, “FIR variable digital filter with signed power-of-two coefficients,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 6, pp. 1348–1357, Jun. 2007.
K. K. Parhi, VLSI Digital Signal Procesing Systems: Design and Implementation. New York: Wiley, 1999.
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