opportunities and challenges in ultra low voltage cmosramirtha/talks/amirtharajah_012309_fina… ·...

Opportunities and Challenges in Ultra Low Voltage CMOS

Rajeevan AmirtharajahUniversity of California, Davis

2

Opportunities for Ultra Low Voltage

Moteiv Sky mote, 2006

• Battery Operated and Mobile Systems– Wireless sensors– RFID tags– Biomedical implants– Mobile Phones, internet devices, and

netbooks– Maximize operating lifetime for stored

energy (minimum energy operation)• Wall-plug and Rack Mounted Systems

– Power-down and sleep modes in servers

– Maintain state in on-chip caches, SRAM memory while minimizing leakage power

3

CMOS Delay and Power Dissipation

leakstaticcircuitshortdynamicTOT PPPPP +++= −

Total Power:

Voltage scaling decreases all power components, at expense of increasing circuit delay.

leakddstaticdd

frpeakddddL

IVIV

ftt

IVfVC

++

⎟⎟⎠

⎞⎜⎜⎝

⎛ ++=

22α

( )22 thddox

ddL

D

ddL

VVLWC

VCIVC

IVCt

−≈=

Δ=Δ μDelay:

4

Low Voltage CMOS Inverter Operation

Swanson and Meindl, JSSC 1972

• Thermal noise limit:

• Inverter gain limit:

• Equalized NMOS-PMOS off currents:

1004≈

qkT

mV

2008≈

qkT

mV

572≈

qnkT

mV

5

Supply Voltage Scaling With Technology Node

• From 2007 ITRS Roadmap

0

0.2

0.4

0.6

0.8

1

1.2

2007 2009 2011 2013 2015 2017 2019 2021

Year

VDD

(V

0

5

10

15

20

25

30

Leng

th (n

m

VDD (High Perf.)

VDD (Low Power)

MPU Physical Gate Length

6

Commercial Wireless Sensor Mote

Moteiv Sky mote, 2006Jiang, IPSN/SPOTS 2005

• Current sensor node: 70 mW all active, 17 μW idle• Power sources contribute significant volume and cost• Smaller system (1 cm3) desirable (less obtrusive military

sensor, implantable biomedical device)• Reduce power consumption, get energy from environment

7

Specific Opportunities for ULV Design• Extremely low power mixed-signal circuits

– Analog design without operational amplifiers

• Low voltage swing on-chip interconnects– Good current drive at low VDD desirable

• Power gates and cutoff devices to minimize leakage power during inactive state– Need steep subthreshold slope to limit leakage current when

blocks turned off

• Low voltage active mode and sleep mode memories, caches– Need reliable operation under variable VDD

• Low voltage standard cells– Operate at minimum energy point, balancing leakage and

dynamic power

IFC Pre-Annual Review - August 13, 2008 8

Low Voltage Sensor Interfaces

Initial evaluation of nanowire suitability for sensors: noise and power implications (Amirtharajah et al., Int’l J. Nanotechnology 2008)

Exploit ultra low power, low area, energy scalable ADC architecture based on passive switched capacitor modulator, digital comparator

Reza et al., IEEE Trans. Nanotechnology2005

Passive Sigma Delta Modulator ADC

9

Energy and Voltage Scalable Sensor Interfaces

Passive modulator Sigma Delta ADCChip verified over range of OSRs: about 10 bits, 450 nW power consumption for 1 kHz input BWUseful ENOB from VDD = 1V down to 200 mVSubmitted to VLSI 2009

Test Chip (90 nm CMOS) Measured Noise Shaping Spectrum

10

Energy Scalable Array

Several operations confirmed, working out configuration issuesCurrently testing array

Test Chip Features

– Sixteen tiles connected by island-style x and y routing

– Implemented in 0.25 μm CMOS from TSMC

– Includes test structures for low switching activity interconnect

– Includes multiple-input energy harvesting power supply (to appear ISSCC09)


Edge Position Signaling

Modulator

Demodulator

• Encode multiple bits per wire transition by modulating edge timing, Pulse Position (PPM), Pulse Width (PWM)

• Reduces worst case power consumption over binary signaling• What is circuit implementation area and power overhead?• Measured data from test chip: power vs. interconnect length


Edge Position Signaling Crossover

• Plot shows wire length at which power saved over binary signaling for various throughputs and minimum VDD (nominal VDD = 2.5V)

• Edge position signaling useful for global wires (length > 7mm)

Ring Oscillator Output

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

0 5 10 15 20time (ns)

Volts

VDDVout

• Self-timed datapath must be initialized at power-on• Must maintain state across power supply cycles

Frequency Variation With High Ripple / AC Supply

tHold

3T DRAM Cell Layout

Read

Store

M3

M1

M2

3T DRAMWrite

• 46 µm2 gate size chosen for 1.2ms retention

– Vdd = 400 mV– 0°C < T < 50°C

• Hold time for 60 Hz supply

AC Supply Test Chip Photo and Summary

Technology 180 nm CMOS

Dimensions 2.6 mm x 2.6 mm

Transistors 135KI/O VDD 1.8 VAC Supply (VPP = 1.8 V)

60 Hz –1 kHz

Core Freq. (max) 75.6 MHz

Flip-Flop DRV 153 mV

Power (Core)

127 –113 µW

POR OSC

FIR Filter

• Published Symposium on VLSI Circuits, 2007

16

Challenges for Ultra Low Voltage

• Device variability (within die, across dies, and across wafers)

– Variations in threshold voltage drastically affect critical circuit performance parameters

– Examples: Ion/Ioff ratios, gate delays, static memory noise margins, subthreshold slope for leakage limiting devices

• Noise and event tolerance– Approaching fundamental noise limit may decrease

reliability and MTTF– Limited charge storage on circuit nodes may increase

susceptibility to soft errors in both memory and logic

0 0.1 0.2 0.30

0.1

0.2

0.3

VIN

(V)

VO

UT (

V)

Sub-Vt Design Challenges

Sub-Vt static CMOS gates exhibit variation in logic levels (VOH, VOL)

Active

Leakage

on off

RDF

t

© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE

From Kwong et al., ISSCC 08

0 0.1 0.2 0.30

0.1

0.2

0.3

VIN

(V)

VO

UT (

V)

0 1 2 30

0.1

0.2

0.3

Time (µµµµs)

Vo

lta

ge

(V

)

Sub-Vt Logic Functionality

Degraded logic levels adversely impact functionality

CLK

N2N3

N4Not completely off, causing functional

failure

CLKCLK N3

N4

N2,Q



Sub-Vt Logic Design

Functional metric necessary to manage

sizing trade-off

0 0.1 0.20

0.1

0.2

VIN-NAND

, VOUT-NOR

VO

UT

-NA

ND,

VIN

-NO

R

NAND

NOR

0 0.1 0.20

0.1

0.2

VIN-NAND

, VOUT-NOR

VO

UT

-NA

ND,

VIN

-NO

R

Logic failure

NAND

NOR

NAND NOR

t

WLtVσ 1∝∝∝∝



Sub-Vt Standard Cell Library

0.2 0.25 0.30

500

1000

VOH

(V)

Occu

rren

ces

0.2 0.25 0.30

5000

10000

VOH

(V)

Occu

rren

ces

0 0.1 0.2 0.30

1000

2000

VOL

(V)

Occu

rren

ces

t

Leakage

Active

Outliers

t

0 0.1 0.2 0.30

5000

10000

VOL

(V)

Occu

rren

ces



Sub-Vt SRAM Challenges

Hold SNM Read SNM

Hold SNM preserved to low-voltages

NT NCNT NC

NC, NT (V)

0.2 0.4 0.6 0.8 1.00

NT

, N

C (

V)

0.2

0.4

0.6

0.8

1.0

0

NC, NT (V)

NT

, N

C (

V)

0.2

0.4

0.6

0.8

1.0

00.2 0.4 0.6 0.8 1.00

Read SNM degraded at low-voltages

WLWL

BLBL



SRAM Architecture and Bit-Cell

Buffer eliminates read SNM limitationPeripheral assists allow sub-Vt writing and sensing

Based on Verma, ISSCC 2007



Peripheral Assists

“0”

PCHRG

“1”

No sub-Vtleakage

VVDD

ReadWrite

“0”

“1” (64 Cells)

“1” (256 Cells)

“1” (256, 64 Cells)

RD

BL

Vo

ltag

e 0.3

0.4

0.2

0.1

0

10 20 30 40µs

6T Cell

VVDDWR

NTNC

0.3

0.2

0.1

0

Vo

lts

0.3

0.2

0.1

0

Vo

lts

10 12 14 16 18 20

10 12 14 16 18 20µs

NT NC

“1” “0”

VVDD

“1” “1”

WR



Sub-Vt Timing Analysis Challenges

Order-of-magnitude higher delay variation in sub-Vt

Oc

cu

rre

nc

es

Occ

urr

en

ces



0 200 4000

0.2

0.4

0.6

Mean delay [ns]

σσ σσ/ µµ µµ

(S

td.

de

v.

ov

er

me

an

)

Comprehensive Timing Simulations

Increasing mean delay

Delay (ns)Path #

Simulation of 30000 timing paths illustrates trends in sub-Vt delay variability



Test-Chip Summary

Performance

1.36mm2SRAM

0.12mm2DC-DC Converter

Area

0.14mm2Logic

65nm CMOSProcess

VDD = 300mVMinimum

Functional VDD

VDD = 500mVMinimum

Energy Point

2.29mm

128Kb SRAM

array

DC-DC

converter

Core logic

(2 power domains)

1.8

6m

m



17

Conclusions

• Many opportunities for ultra low voltage design exist– Energy Constrained Applications: wireless sensors,

mobile devices, biomedical implants

– Minimum Power Applications: sleep and minimum leakage modes in processors and memories

• Main challenge is device parameter variations– Threshold voltage variation severely impacts delays,

noise margins in logic and SRAM

• Very active area of circuits research– ISSCC 2009 Advanced Circuits Forum on Ultra Low

Voltage

18

Acknowledgments

• Jamie Collier

• Liping Guo

• Travis Kleeburg

• National Science Foundation CAREER Award

• FCRP Interconnect Focus Center

• Xilinx University Program and Xilinx Research Labs

• U.S. Dept. of Education GAANN Fellowship

• TSMC

• Jeff Loo

• Mackenzie Scott

• Justin Wenck

• Joyce Kwong, MIT

• Prof. Anantha Chandrakasan, MIT

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