1

Performance Results

• The following are some graphical performance results out of the literature for different ATM switch designs and configurations

• For more information, see [Tobagi 1990]

2

Input Buffering

• The first set of performance results is for input buffering (alone) with First Come First Serve (FCFS) service discipline (also known as First In First Out (FIFO))

• Suffers from the Head of the Line blocking problem

N Maximum Throughput

1 12 0.753 0.68254 0.65535 0.63996 0.63027 0.62348 0.6184 0.5858

Maximum Throughput for Input Buffering

NUMBER OF PORTS (N)

Maximum Throughput for Input Buffering

0 20 40 60 80 100

MA

XIM

UM

AC

HIE

VA

BLE T

HR

OU

GH

PU

T

0.8

0.5

0.6

0.7

5

Performance of Banyans

• The next set of performance results is for banyan multistage interconnection networks (NOTE: these are NOT Batcher-banyans)

• FACT: in a bufferless banyan, throughput T degrades significantly with an increase in N, the number of input ports, due to the blocking problems (path contention and output port contention)

• T = 40% for N = 32, T = 26% for N = 1024

6

Buffered Banyans

• Performance of banyans can be improved by adding internal buffers to the switch fabric at places where contention may occur (i.e., at outputs of each 2x2 module)

• This approach can increase the effective throughput of banyans

7

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.2 0.4 0.6 0.8 1.0

OFFERED LOAD p

TH

RO

UG

HP

UT

N=2

Throughput for Uniform Traffic (Single Buffered Banyan)

8

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.2 0.4 0.6 0.8 1.0

OFFERED LOAD p

TH

RO

UG

HP

UT

N=2

Throughput for Uniform Traffic (Single Buffered Banyan)

N=4

9

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.2 0.4 0.6 0.8 1.0

OFFERED LOAD p

TH

RO

UG

HP

UT

N=2

Throughput for Uniform Traffic (Single Buffered Banyan)

N=4

N=16

10

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.2 0.4 0.6 0.8 1.0

OFFERED LOAD p

TH

RO

UG

HP

UT

N=2

Throughput for Uniform Traffic (Single Buffered Banyan)

N=4

N=16N=64

11

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.2 0.4 0.6 0.8 1.0

OFFERED LOAD p

TH

RO

UG

HP

UT

N=2

Throughput for Uniform Traffic (Single Buffered Banyan)

N=4

N=16N=64

N=1024

12

0.3

0.4

0.5

0.6

0.7

0.8

0.3 0.4 0.5 0.6 0.7 0.8

OFFERED LOAD p

TH

RO

UG

HP

UT

B=4

Effect of Buffer Size (N = 64)

B=2

B=1

0.9 1.0

13

0.3

0.4

0.5

0.6

0.7

0.8

0.3

OFFERED LOAD p

TR

OU

GH

PU

T

HOL BYPASS

Effect of HOL Bypass (N = 64)

FIFO

(WITH HOL BLOCKING)

0.4 0.5 0.6 0.7 0.8 0.9 1.0

14

Buffered Banyans: Summary

• Performance depends on load

• The more buffers, the better the throughput

• HOL bypass helps

• Performance still degrades as N increases, due to blocking effects

15

Shared Memory Switches

• The next set of performance results looks at buffer managment strategies for shared memory switches

• In particular, looks at cell loss performance for partitioned versus shared buffering

16

Partitioned Buffers

SHARED MEMORY

17BUFFER SIZE, b (per port)

Cell Loss with Partitioned Buffers (=0.9)

-12

-10

-8

-6

-4

-2

0 20 40 60 80

CELL L

OS

S P

RO

BA

BIL

ITY

N=2

1.0

10

10

10

10

10

10

18BUFFER SIZE, b (per port)

Cell Loss with Partitioned Buffers (=0.9)

-12

-10

-8

-6

-4

-2

0 20 40 60 80

CELL L

OS

S P

RO

BA

BIL

ITY

N=2

N=4

1.0

10

10

10

10

10

10

19BUFFER SIZE, b (per port)

Cell Loss with Partitioned Buffers (=0.9)

-12

-10

-8

-6

-4

-2

0 20 40 60 80

CELL L

OS

S P

RO

BA

BIL

ITY

N=2

N=4

N=8

1.0

10

10

10

10

10

10

20BUFFER SIZE, b (per port)

Cell Loss with Partitioned Buffers (=0.9)

-12

-10

-8

-6

-4

-2

0 20 40 60 80

CELL L

OS

S P

RO

BA

BIL

ITY

N=2

N=4

N=8

1.0

10

10

10

10

10

10

N=

21BUFFER SIZE, b (per port)

0 10 20 30 40 50

CELL L

OS

S P

RO

BA

BIL

ITY

-12

-10

-8

-6

-4

-2

1.0

10

10

10

10

10

10

p=0.70

Cell Loss with Partitioned Buffers (N=)

22BUFFER SIZE, b (per port)

0 10 20 30 40 50

CELL L

OS

S P

RO

BA

BIL

ITY

-12

-10

-8

-6

-4

-2

1.0

10

10

10

10

10

10

p=0.70

0.75

Cell Loss with Partitioned Buffers (N=)

23BUFFER SIZE, b (per port)

0 10 20 30 40 50

CELL L

OS

S P

RO

BA

BIL

ITY

-12

-10

-8

-6

-4

-2

1.0

10

10

10

10

10

10

p=0.70

0.75

0.80

Cell Loss with Partitioned Buffers (N=)

24BUFFER SIZE, b (per port)

0 10 20 30 40 50

CELL L

OS

S P

RO

BA

BIL

ITY

-12

-10

-8

-6

-4

-2

1.0

10

10

10

10

10

10

0.85

p=0.70

0.75

0.80

Cell Loss with Partitioned Buffers (N=)

25BUFFER SIZE, b (per port)

0 10 20 30 40 50

CELL L

OS

S P

RO

BA

BIL

ITY

-12

-10

-8

-6

-4

-2

1.0

10

10

10

10

10

10

0.90

0.85

p=0.70

0.75

0.80

Cell Loss with Partitioned Buffers (N=)

26BUFFER SIZE, b (per port)

0 10 20 30 40 50

CELL L

OS

S P

RO

BA

BIL

ITY p=0.95

-12

-10

-8

-6

-4

-2

1.0

10

10

10

10

10

10

0.90

0.85

p=0.70

0.75

0.80

Cell Loss with Partitioned Buffers (N=)

27

Shared Buffers

SHARED MEMORY

28BUFFER SIZE, b (per port)

0 10 20 30 40 50

CELL L

OS

S P

RO

BA

BIL

ITY

N=16

-12

-10

-8

-6

-4

-2

1.0

10

10

10

10

10

10

Cell Loss with Shared Buffers (=0.9)

29BUFFER SIZE, b (per port)

0 10 20 30 40 50

CELL L

OS

S P

RO

BA

BIL

ITY

N=16

-12

-10

-8

-6

-4

-2

1.0

10

10

10

10

10

10

N=32

Cell Loss with Shared Buffers (=0.9)

30

Shared Memory: Summary

• Shared buffers provide much lower cell loss than partitioned buffers, for uniform input traffic (Note: the opposite may be true for non-uniform traffic!)

• For partitioned, cell loss gets worse with larger N, while for partitioned it gets better

31

Sunshine Switch

• The final set of graphs looks at the performance of the Sunshine switch

• Sunshine switch is based on a Batcher banyan design, but with recirculation lines and with the use of multiple banyans in parallel to accommodate multiple cells destined to the same output port

32

Batcher-Banyan Switching Fabric

RECIRCULATINGQUEUE

M M

BA

TC

HER

SO

RTER

TR

AP

NETW

OR

K

CO

NC

EN

TR

ATO

R

IN 1

IN N

...

......

......

......

BANYANROUTINGNETWORK

M+N M+NN

33

SUNSHINE SWITCH ARCHITECTURE

DELAY

M M

BA

TC

HE

R S

OR

TE

R

TR

AP

NETW

OR

K

CO

NC

EN

TR

ATO

R

IN 1

IN N

...

......

M+N

......

M+N

......

M+N

SELE

CTO

R

BANYAN 1

BANYAN K

...

OUT 1

OUT N

...

34

0.0

M/N

CELL L

OS

S R

ATIO

Cell Loss in Sunshine Switch (K=1)

p=0.4

-1010

-810

-610

-210

-410

010

0.2 0.4 0.6 0.8

Uniform TrafficN = 128

Single Banyan (K=1)

35

0.0

M/N

CELL L

OS

S R

ATIO

Cell Loss in Sunshine Switch (K=1)

p=0.6

p=0.4

-1010

-810

-610

-210

-410

010

0.2 0.4 0.6 0.8

Uniform TrafficN = 128

Single Banyan (K=1)

36

0.0

M/N

CELL L

OS

S R

ATIO

Cell Loss in Sunshine Switch (K=1)

p=0.8

p=0.6

p=0.4

-1010

-810

-610

-210

-410

010

0.2 0.4 0.6 0.8

Uniform TrafficN = 128

Single Banyan (K=1)

37

0.0

M/N

CELL L

OS

S R

ATIO

p=1.0

Cell Loss in Sunshine Switch (K=1)

p=0.8

p=0.6

p=0.4

-1010

-810

-610

-210

-410

010

0.2 0.4 0.6 0.8

Uniform TrafficN = 128

Single Banyan (K=1)

38

0.0 0.1 0.2 0.3 0.4 0.5

M/N

CELL L

OS

S R

ATIO

K=1

-1010

-810

-610

-210

-410

010

Uniform TrafficN = 128p = 1.0

Cell Loss in Sunshine Switch (K>1)

39

0.0 0.1 0.2 0.3 0.4 0.5

M/N

CELL L

OS

S R

ATIO

K=2

K=1

-1010

-810

-610

-210

-410

010

Uniform TrafficN = 128p = 1.0

Cell Loss in Sunshine Switch (K>1)

40

0.0 0.1 0.2 0.3 0.4 0.5

M/N

CELL L

OS

S R

ATIO

K=2

K=1

K=3

-1010

-810

-610

-210

-410

010

Uniform TrafficN = 128p = 1.0

Cell Loss in Sunshine Switch (K>1)

41

0.0 0.1 0.2 0.3 0.4 0.5

M/N

CELL L

OS

S R

ATIO

K=2K=4

K=1

K=3

-1010

-810

-610

-210

-410

010

Uniform TrafficN = 128p = 1.0

Cell Loss in Sunshine Switch (K>1)

42

Sunshine Switch: Summary

• Sunshine switch was designed and prototyped at Bellcore

• Multiple banyans provide parallel routing paths to accommodate multiple cells destined for the same output port

• Recirculation handles the “overflows”

• Very promising switch design