pixel detector r&d towards an ilc vertex detector€¦ · zstandard vlsi chip, with thin (10~15...

Pixel Detector R&DPixel Detector R&Dtowards an ILCtowards an ILCVertex DetectorVertex Detector

Tobias HaasTobias HaasDESY/F1DESY/F1

17 September 200717 September 2007

17 September 200717 September 2007 Tobias Haas: VXD R&DTobias Haas: VXD R&D

This TalkThis Talk

Introduction: ILCIntroduction: ILCVXD considerationsVXD considerationsSensor R&DSensor R&D

CCD, MAPS, DEPFET, …CCD, MAPS, DEPFET, …R&D Infrastructure: EUDETR&D Infrastructure: EUDETConclusionsConclusions


The ILCThe ILC(The next great project in HEPP)(The next great project in HEPP)

EEcmcm adjustable from 200 adjustable from 200 –– 500 500 GeVGeV

Luminosity Luminosity ∫∫LdtLdt = 500 fb= 500 fb--11 in 4 years in 4 years Ability to scan between 200 and 500 Ability to scan between 200 and 500 GeVGeVEnergy stability and precision below 0.1%Energy stability and precision below 0.1%Electron polarization of at least 80%Electron polarization of at least 80%The machine must be upThe machine must be up--gradeablegradeable to 1 to 1 TeVTeV


Physics Motivation, e. g. HiggsPhysics Motivation, e. g. Higgs


Tracking/Tracking/VertexingVertexing


R&D for Tracking/R&D for Tracking/VertexingVertexing


General ConsiderationsGeneral ConsiderationsImpact parameter:Impact parameter:Minimal material: Minimal material: Fast readoutFast readoutRadiation hardRadiation hard

1 train = ~ 3000 bunches in ~ 1 ms, 5Hz repetition rate1 train = ~ 3000 bunches in ~ 1 ms, 5Hz repetition rateOccupancy is too high to integrate over one trainOccupancy is too high to integrate over one train

ϑμμσ 23sin105 pmmip ⊕=

0%1.0 X≤

ReadoutReadout~ 20 x during train ~ 20 x during train (every 50 (every 50 µµs)s)Between trains Between trains (store info in sensors)(store info in sensors)Decrease pixel size + Decrease pixel size + time stampingtime stamping


Radiation and BackgroundsRadiation and Backgrounds

Operation at high background ratesOperation at high background rates: : 0.04 hits/mm0.04 hits/mm22/BX in the inner layer (1.5 cm)/BX in the inner layer (1.5 cm)

Occupancy of ~10% per Occupancy of ~10% per bunchtrainbunchtrain20 frames per train (1 ms)20 frames per train (1 ms)40 MHz line rate => ½% 40 MHz line rate => ½% OccupOccup. (4096 lines along a 10 cm module). (4096 lines along a 10 cm module)

Radiation Hard up to Radiation Hard up to 360 360 kRadkRad

and 10and 101212 n/cmn/cm2 2 (10 years)(10 years)


Technology OptionsTechnology Options

Readout every 50 Readout every 50 µµs:s:CCDsCCDs, MAPS, DEPFET, SOI, MAPS, DEPFET, SOI

InIn--pixel memory and R/O between trains:pixel memory and R/O between trains:ISIS, FAPSISIS, FAPS

Finer pixels and R/O between trains:Finer pixels and R/O between trains:FPCCD (no bunch id)FPCCD (no bunch id)ChronopixelsChronopixels (with bunch id)(with bunch id)


CCDsCCDs and and CPCCDsCPCCDs

CCD technology proven at SLD, but ILC CCD technology proven at SLD, but ILC sensors must be faster, more sensors must be faster, more radrad--hardhardReadout in parallel addresses speed Readout in parallel addresses speed concernsconcernsCPCCD’sCPCCD’s feature small pixels, can be feature small pixels, can be thinned, large area, and are fastthinned, large area, and are fastCPC1: twoCPC1: two--phase, 400 (V) x 750 (H) pixels, phase, 400 (V) x 750 (H) pixels, each 20 20 μm2each 20 20 μm2

“Classic CCD”Readout time ≈

N×M/Fout

N

M

N

Column Parallel CCD

Readout time = N/Fout

CPCCD1


ColumnColumn--Parallel Parallel CCDsCCDsFirstFirst--generation tests (CPC1):generation tests (CPC1):

Noise ~100 eNoise ~100 e−− (60 e(60 e−− after filter).after filter).Minimum clock potential ~1.9 V.Minimum clock potential ~1.9 V.Max clock frequency above 25 Max clock frequency above 25 MHz (design 1 MHz).MHz (design 1 MHz).Limitation caused by clock skewLimitation caused by clock skew

Next generation now available (CPC2):Next generation now available (CPC2):BuslineBusline free design (twofree design (two--level metal) level metal) Large area ‘stitched’ sensor, choice of Large area ‘stitched’ sensor, choice of epiepilayers for varying depletion depthlayers for varying depletion depthRange of device sizes for test of Range of device sizes for test of clock propagation (up to 50 MHz)clock propagation (up to 50 MHz)Large chips are nearly the right sizeLarge chips are nearly the right size

Level 1 metal

Polyimide

Level 2 metal

Φ2 Φ1

OAT & test field

2 x ISIS + top termination

Top & Bottom termination

PIXELSPIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS

PIXELS









OAT & test field

OAT & test field2 x ISIS + top

termination





Top & Bottomtermin



2 x ISIS + top termination AcCPC2

Wafer

CPC2-709.2 cm


CPC2: Next generation CCDCPC2: Next generation CCDCPC2: second generation ColumnCPC2: second generation Column--parallel CCDparallel CCD

SingleSingle--metal: (100 Ωcm @ 25 µm and 1.5 kΩcm @ 50 µm) metal: (100 Ωcm @ 25 µm and 1.5 kΩcm @ 50 µm) 2 more wafers received with 22 more wafers received with 2--level level metal (metal (buslinebusline--free) free) BuslineBusline--free variant designed for free variant designed for 50 MHz operation50 MHz operationAnother 10 wafers in pipelineAnother 10 wafers in pipeline

BuslineBusline--free design a big step!free design a big step!

CPC2-70

CPC2-40

CPC2-10

ISIS teststructures

Busline-free CPC2


InIn--Situ Storage Image SensorSitu Storage Image Sensor

ISIS Sensor details:ISIS Sensor details:CCDCCD--like charge storage cells in each pixel, CMOS or CCD technologylike charge storage cells in each pixel, CMOS or CCD technologyp+ shielding implant (or epi) forms reflective barrierp+ shielding implant (or epi) forms reflective barrier

Operational Principles:Operational Principles:Charge collected at photogate, transferred to storage pixel duriCharge collected at photogate, transferred to storage pixel during bunch trainng bunch train20 transfers per 1 ms bunch train20 transfers per 1 ms bunch trainReadout during 200 ms quiet period after bunch trainReadout during 200 ms quiet period after bunch train


ISIS Properties and StatusISIS Properties and Status

ISIS advantages:ISIS advantages:Low frequency clock Low frequency clock --> easy to drive> easy to drive20 kHz during capture, 1MHz readout20 kHz during capture, 1MHz readout≈100 times more radiation hard (fewer ≈100 times more radiation hard (fewer charge transfers)charge transfers)More robust to beamMore robust to beam--induced RF pickupinduced RF pickup

Process and Status:Process and Status:Combines CCD and active pixel Combines CCD and active pixel technologies technologies Deep implant or custom Deep implant or custom epiepi neededneededInvestigating CMOS and CCD vendorsInvestigating CMOS and CCD vendors

Proof of principle device (ISIS1) Proof of principle device (ISIS1) manufacturedmanufactured

RG RD OD RSEL

Column transistor

On-

chip

logi

c

On-

chip

sw

itche

s

Global Photogate and Transfer gate

ROW 1: CCD clocks

ROW 2: CCD clocks

ROW 3: CCD clocks

ROW 1: RSEL

Global RG, RD, OD

5 μm


MAPS/CMOS SensorsMAPS/CMOS Sensorspp--type lowtype low--resistivityresistivity SiSi hosting nhosting n--type ”charge collectors”type ”charge collectors”

signal created in signal created in epiepi layer (low doping):layer (low doping):Q ~ 80 Q ~ 80 ee--hh / / μmμm →→ signal ~1000 e−signal ~1000 e−charge sensing through charge sensing through nn--well/pwell/p--epiepi junctionjunctionexcess carriers propagate (thermally) to diodeexcess carriers propagate (thermally) to diodewith help of reflection on boundarieswith help of reflection on boundarieswith pwith p--well and substrate (high doping)well and substrate (high doping)

Specific advantages of CMOS sensors:Specific advantages of CMOS sensors:Signal processing μSignal processing μ--circuits integrated on sensor substrate (systemcircuits integrated on sensor substrate (system--onon--chip) chip)

compact, flexiblecompact, flexibleSensitive volume (~ Sensitive volume (~ epitaxialepitaxial layer) is ~ 10layer) is ~ 10––15 15 μmμm thickthick

thinning to .30 thinning to .30 μmμm possiblepossibleStandard, massive production, fabrication technology Standard, massive production, fabrication technology

cheap, fast turncheap, fast turn--overoverRoom temperature operationRoom temperature operation

Attractive balance between granularity, mat. budget, rad. tolerance, R/O speed and power dissipation


Monolithic Active Pixel SensorMonolithic Active Pixel Sensor

Standard VLSI chip, with thin (10~15 µm) low doped epi. sensitive layerIntensive R&D to develop working chip since 1999:

MIMOSA-5 (1 Mpix, 3.5 cm2)MIMOSA-20 (=M*3) (200 kpix, 1x2 cm2)MIMOSA-17 (65 kpix, 0.8 x 0.8 cm2)General performances well established

new generation of full scale sensors underway : EUDET, STAR demonstrator


MAPS StatusMAPS StatusCMOS sensors are developed for CMOS sensors are developed for running conditions with beam running conditions with beam backgroundbackgroundFast readFast read--out sensors progressing out sensors progressing steadilysteadily

ColCol--parallel architecture with discriminated parallel architecture with discriminated output operationaloutput operationalADCs are being ADCs are being develpeddevelped1st generation 01st generation 0--supp. μsupp. μ--circuits close to circuits close to fabricationfabrication

Mimosa22


ChronopixelsChronopixels (CMOS)(CMOS)

Buffer data during ~3000 bunches in a train and readout between Buffer data during ~3000 bunches in a train and readout between bunch bunch trainstrains

bunch number stored for up to 4 samplesbunch number stored for up to 4 samplessingle bunch cross taggingsingle bunch cross tagging

563 transistors [2 (4) buffers per pixel 563 transistors [2 (4) buffers per pixel with calibration] into 50 x 50 with calibration] into 50 x 50 µµmm22 pixel pixel (180 nm process)(180 nm process)demonstrated performancedemonstrated performanceready for 80 x 80 array submissionready for 80 x 80 array submission20 x 20 20 x 20 µµmm22 and 45 nm processand 45 nm process


DEPFETDEPFET• Each pixel is a p-FET on a completely depleted

bulk• A deep n-implant creates a potential minimum for

electrons under the gate• (“internal gate”)• Signal electrons accumulate in the internal gate

and modulate the transistor current (gq ~ 400 pA/e-)

• Accumulated charge can be removed by a clear contact (“reset”)

Fully depleted: ⇒large signal, fast signal collection

Low capacitance, internal amplification:=> low noise

Transistor on only during readout: => low power

Complete clear: => no reset noise

Compact layout:Two pixel share common source and clear

(“double pixel”)


DEPFET StatusDEPFET StatusFeasibility has been demonstrated Feasibility has been demonstrated with small devices:with small devices:

Test beam measurements with Test beam measurements with DEPFET based telescopeDEPFET based telescopeLow intrinsic noise at ILC bandwidthLow intrinsic noise at ILC bandwidthRadiation hardness demonstrated Radiation hardness demonstrated (Gamma, Proton & Neutron (Gamma, Proton & Neutron irradiations)irradiations)

Next Steps:Next Steps:New matrix production (large, ILC New matrix production (large, ILC scale matrices, various scale matrices, various improvements)improvements)Test new readout & control ASIC Test new readout & control ASIC (speed, noise, radiation hardness)(speed, noise, radiation hardness)Operate system at ILC speedOperate system at ILC speed

Future StepsFuture StepsProduce thinned matrices (2008/2009)Produce thinned matrices (2008/2009)

Depfet Telescope in DESY beam


SoISoIProperties

Non-standard processHandle wafer, normally passive is the detector Signal collected in fully depleted substrate, thus large signalsElectronics in the device layerShould be rad. hard; can have NMOS and PMOS transistors

Process Technology Allows for production of pixel sensors which are thin (<50 microns)Excellent and well controlled charge collection using fully depleted devicesUse full CMOS readout without parasitic charge collection High-resistivity handle wafer as detector

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EUDET:EUDET:Status and Perspectives Status and Perspectives

The EUDET initiative The EUDET initiative EUDET activitiesEUDET activities

Joint Research Joint Research ActivitiesActivitiesNetworkingNetworking

Summary and Summary and OutlookOutlook

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EUDETEUDET

INFN FerraraINFN FerraraINFN MilanINFN MilanINFN PaviaINFN PaviaINFN INFN RomeRome

NIKHEF AmsterdamNIKHEF Amsterdam

AGH AGH CracowCracowINPPAS INPPAS CracowCracow

CSIC SantanderCSIC Santander

LundLund UniversityUniversity

CERN CERN GenevaGenevaGenevaGeneva UniversityUniversity

Bristol UniversityBristol UniversityUCL LondonUCL London

Charles University Charles University PraguePragueIPASCR IPASCR PraguePrague

HIP HelsinkiHIP Helsinki

LPC LPC ClermontClermont--FerrandFerrandLPSC GrenobleLPSC GrenobleLPHNE ParisLPHNE ParisEcole Ecole PolytechniquePolytechnique PalaiseauPalaiseauLAL LAL OrsayOrsayIReSIReS StrasbourgStrasbourgCEA CEA SaclaySaclay

DESYDESYBonn UniversityBonn UniversityFreiburg UniversityFreiburg UniversityHamburg UniversityHamburg UniversityMannheim UniversityMannheim UniversityMPI MunichMPI MunichRostock UniversityRostock University

Tel Aviv UniversityTel Aviv University + 22 + 22 associatedassociated institutesinstitutes

EUDET Partner InstitutesEUDET Partner Institutes

EUDET is an “Integrated Infrastructure Initiative (I3)” within tEUDET is an “Integrated Infrastructure Initiative (I3)” within the EU funded he EU funded “6“6thth framework framework programmeprogramme” ” Support improvement of infrastructure for detector R&D with largSupport improvement of infrastructure for detector R&D with larger er prototypes prototypes -- but not the R&D itselfbut not the R&D itself

EUDET is not a EUDET is not a collaboration collaboration

Other institutes can Other institutes can contribute and exploit contribute and exploit the infrastructurethe infrastructureInfrastructure can be Infrastructure can be rere--locatedlocated

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2006 2007 2008 2009

Magnet & Magnet & Pixel Pixel

TelescopeTelescope18%18%

Management Management 4%4%

CalorimeterCalorimeter33%33%

NetworkingNetworking 9%9%

TA 2% TA 2%

TrackingTracking 33%33%

21.5 million EUR total21.5 million EUR total(7.0 million EU contribution)(7.0 million EU contribution)

ManpowerManpower≈ 57 FTE total≈ 57 FTE total≈ 17 FTE ≈ 17 FTE fundedfunded byby EUEU

mostmost of of thethe resourcesresourcesforfor thethe developmentdevelopment of of thethe infrastruturesinfrastrutures

Duration of 4 yearsDuration of 4 yearsRampRamp--upup firstfirst half 2006half 2006Full swing Full swing activitiesactivities forfor 2.5 2.5 yearsyearsLast Last yearyear: : phasephase--outout and and exploitationexploitation of of infrastruturesinfrastrutures

EUDET BudgetEUDET Budget

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EUDET EUDET

NetworkNetwork Transnational Transnational AccessAccess

Joint Research Joint Research ActivitiesActivities

ManagementManagement

Detector R&D Detector R&D NetworkNetwork

Access to Access to DESY Test BeamDESY Test Beam

Access to Detector Access to Detector R&D InfrastructuresR&D Infrastructures

Test Beam Test Beam InfrastructuresInfrastructures

TrackingTrackingDetectorsDetectors

CalorimeterCalorimeter

JRA1JRA1

JRA2JRA2

JRA3JRA3

I3 I3 projectsprojects basedbased on on threethree pilarspilars::

EUDET StructureEUDET Structure

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Test beam Infrastructure JRA1Test beam Infrastructure JRA1Provide test beam telescope with:Provide test beam telescope with:

Very high precision: <3 μm precision even at lower energiesVery high precision: <3 μm precision even at lower energiesHigh readout speed (frame rate >1kHz)High readout speed (frame rate >1kHz)Easy to use: well defined/described interfaceEasy to use: well defined/described interface

Large range of conditions: cooling, positioning, magnetic fieldLarge range of conditions: cooling, positioning, magnetic field

Suitable to different test beam Suitable to different test beam environments:environments:

construction & initial tests at construction & initial tests at DESY (EDESY (Eee-- up to 6 GeV) up to 6 GeV) exploitation at CERN, FNAL etc. exploitation at CERN, FNAL etc. possiblepossible

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JRA1 ScheduleJRA1 SchedulePhase1: “Demonstrator”Phase1: “Demonstrator”

Phase2: Final telescopePhase2: Final telescope

First test facility will be available quickly for the groups devFirst test facility will be available quickly for the groups developing pixels eloping pixels Use established pixel technology with analogue readout and no daUse established pixel technology with analogue readout and no data reductionta reduction

Use pixel sensor with fully digital Use pixel sensor with fully digital readout, integrated Correlated Double readout, integrated Correlated Double Sampling (CDS), and data sparsificationSampling (CDS), and data sparsificationThe beam telescope ready at the end of The beam telescope ready at the end of 20082008

+ Large bore magnet+ Large bore magnet

Detailed planning

constantly being

iterated

2006 2007 2008 2009

nowPCMAG @ DESY

DemonstratorIntegration Starts

PCMAGAvailable

DemonstratorAvailable

FinalTelescopeAvailable

PCMAGField

Mapping

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PCMAG Field MappingPCMAG Field Mapping

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((AnalogAnalog) Telescope) Telescope

Sensors with (analogue)Sensors with (analogue)outputoutput

ReadOutReadOut

Boards to carry theBoards to carry thesensorssensors

Mechanics to positionMechanics to positionthe sensors preciselythe sensors precisely

AUXboard

Ingredients needed for such a telescopeIngredients needed for such a telescope

Trigger LogicUnit

ee--

DUTDUT

EUDRBEUDRB

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Board StatusBoard Status

20 sets of boards 20 sets of boards AUX board as interface to VME boardAUX board as interface to VME boardProximity board housing the sensor Proximity board housing the sensor (two types)(two types)

AUX boardAUX board

Proximity boardProximity board

IPHC Strasbourg/DESYIPHC Strasbourg/DESY

AUXboard

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Reference Plane SensorsReference Plane Sensors

Demonstrator: MimoTelDemonstrator: MimoTeluse MimoTel prototypeuse MimoTel prototypeAMS 0.35 OPTO process with 14 and AMS 0.35 OPTO process with 14 and 20μm epitaxial layer20μm epitaxial layer4 sub4 sub--arrays (64 × 256 pixel)arrays (64 × 256 pixel)

30 × 30 μm30 × 30 μm22 pitch: active area: 7.7 pitch: active area: 7.7 × 7.7 mm× 7.7 mm22

readout : 1.6 ms (4 analog output readout : 1.6 ms (4 analog output nodes at 10 MHz)nodes at 10 MHz)pixel designed to stand >1 MRad at pixel designed to stand >1 MRad at room temperatureroom temperatureengineering run was in summer 06engineering run was in summer 06end of October, reception of end of October, reception of engineering runengineering run

MimoStar3

MimoTEL Imager10µ Imager12µ

Mimosa16 Mimosa16

Latchup ADC ADC MyMap

TestStruct

Layout of the reticle of the Layout of the reticle of the engineering run AMSengineering run AMS--035 OPTO 035 OPTO 07/2006 on 14 µm (standard) and 20 07/2006 on 14 µm (standard) and 20 µm epi substrateµm epi substrate

From November to end of 2006, two tests in parallelFrom November to end of 2006, two tests in parallelprobe station setup preparation for wafer with 14 µm EPIprobe station setup preparation for wafer with 14 µm EPIlaboratory test for circuits with 20 µm EPIlaboratory test for circuits with 20 µm EPI

IPHC StrasbourgIPHC Strasbourg

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MimoTelMimoTel

End of 2006 to Jan. 2007, dicing 14 µm EPI End of 2006 to Jan. 2007, dicing 14 µm EPI waferwaferLaboratory test for circuits with 14 µm EPILaboratory test for circuits with 14 µm EPI

AMS did not respect one of our specifications: AMS did not respect one of our specifications: highhigh--resistivity polyresistivity polyBiasing DACs out of rangeBiasing DACs out of range

No effect on Mimosa18 (High Resolution No effect on Mimosa18 (High Resolution Tracker)Tracker)Small modification on the PCB board: MimoTel Small modification on the PCB board: MimoTel can be set "near" nominal conditionscan be set "near" nominal conditions

The dark current on radThe dark current on rad--tol diodes (MimoTel) factor of 5 to 10 higher tol diodes (MimoTel) factor of 5 to 10 higher than expected than expected The dark current on non radThe dark current on non rad--tol diodes (Mimosa18) factor of 5 to 10 tol diodes (Mimosa18) factor of 5 to 10 lower than expectedlower than expected

IPHC StrasbourgIPHC Strasbourg

General remarks:General remarks:

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MimoTel ResultsMimoTel Results

MimoTel (20um EPI layer) MimoTel (20um EPI layer) Response to Fe55 source at 18Response to Fe55 source at 18ooCCNoise of 15 electrons in the range of Noise of 15 electrons in the range of what was expected what was expected KKββ line good visibleline good visible

IPHC/DESYIPHC/DESY

HitmapHitmap

columns

row

s

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Readout: Readout: EUEUDET DET DData ata RReduction eduction BBoardoard

Functionality of motherboard Functionality of motherboard onon--line calculation of pixel line calculation of pixel pedestal and noise, cluster pedestal and noise, cluster finding, ADCfinding, ADCremote configuration of the remote configuration of the FPGAFPGAonon--board diagnosticsboard diagnostics

4 independent signal processing and 4 independent signal processing and digitizing stagesdigitizing stagesImplementationImplementation

One analogue card One analogue card --> signal > signal processingprocessingOne digital card One digital card --> USB> USB

INFN FerraraINFN FerraraEUDRBEUDRB

Operational modesOperational modesZero SuppressionZero Suppression readout to minimize readout dead readout to minimize readout dead time while normal data takingtime while normal data takingFull FrameFull Frame readout mode for debugging or offreadout mode for debugging or off--line line pedestal and noise measurementspedestal and noise measurements

Boards tested and available for first test in beam June Boards tested and available for first test in beam June 20072007

ReadOutReadOut

EUDRBEUDRB

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DAQ Integration ConceptDAQ Integration ConceptHow to integrate the DUT hardware How to integrate the DUT hardware with the JRA1 beam telescope?with the JRA1 beam telescope?

different groups with different different groups with different detector technologies and different, detector technologies and different, prepre--existing DAQ systemsexisting DAQ systemsnobody has a large pool of effort to nobody has a large pool of effort to rewrite existing coderewrite existing code

Use completely different hardware and Use completely different hardware and DAQ for the DUTDAQ for the DUT

synchronize only with Trigger, Busy synchronize only with Trigger, Busy and Reset signalsand Reset signalsreadout software, DAQ and data readout software, DAQ and data storage is provided by the DUT userstorage is provided by the DUT userevents combined offevents combined off--lineline

Trigger Logic Unit (TLU)Trigger Logic Unit (TLU)receives trigger and passes it on to receives trigger and passes it on to telescope and DUTtelescope and DUTvetoes further triggers (BUSY)vetoes further triggers (BUSY)records timestamprecords timestamphardware availablehardware available

file

telescopetelescope

DUTDUT

DAQDAQ

tel. ctrl

intfc

DAQDAQ

DUT ctrl

intfcPCPC PCPC

file

Trigger LogicUnit

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Telescope DAQTelescope DAQHardwareHardware HardwareHardware HardwareHardware

Writer taskWriter task

telescopetelescope‘‘producerproducer’’

DUTDUT‘‘producerproducer’’

otherother‘‘producerproducer’’

Monitoring Monitoring task 1task 1

Monitoring Monitoring task 2task 2

DAQ buffersDAQ buffers

MonitoringMonitoringbuffersbuffers

filefile

DAQ Software is divided into DAQ Software is divided into many parallel tasks:many parallel tasks:

several Producerseveral Producer tasks read tasks read the hardwarethe hardwareone one FileWriterFileWriter task bundles task bundles events, writes to file and events, writes to file and sends subsets for monitoringsends subsets for monitoringThere can beThere can be severalseveral Online Online --MonitoringMonitoring taskstasksoneone Buffer MonitorBuffer Monitor task allows task allows to see what is going onto see what is going ona a FileReaderFileReader can recan re--inject inject data into the monitoringdata into the monitoring

StatusStatusCan have several producers (Dummy, Mimosa, DEPFET, TLU) all runnCan have several producers (Dummy, Mimosa, DEPFET, TLU) all running ing together.together.Data from all of them combined by Data from all of them combined by FileWriterFileWriter and written to binary file.and written to binary file.This can then be converted to a Root file for easier analysis.This can then be converted to a Root file for easier analysis.First version will be available for test beam in June 2007First version will be available for test beam in June 2007

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Telescope MechanicsTelescope MechanicsBox 1:Box 1:

fixed position, optical bench for three fixed position, optical bench for three reference planesreference planesWall to DUT can be removedWall to DUT can be removed

Box 2:Box 2:movable in zmovable in z--direction, optical bench for direction, optical bench for three reference planesthree reference planesWall to DUT can be removedWall to DUT can be removed

Box 3:Box 3:Gap between 2 and 3, closed by thermal Gap between 2 and 3, closed by thermal covercoverDUT positioned on XYDUT positioned on XYφφ--tabletable

XYXYφφ--table:table: external with “long” mechanical structure external with “long” mechanical structure to locate the DUT between the reference planesto locate the DUT between the reference planes

boxes can be placed into magnetic field, not the boxes can be placed into magnetic field, not the XYXYφφ--table (cost reasons)table (cost reasons)

Want to keep a lot of flexibility for different usersWant to keep a lot of flexibility for different users

Box 1Box 1

Box 3Box 3(DUT)(DUT)

ee--

Box 2Box 2

xx

yy

zz

x

y

φ

PI

DESYDESY

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Senor BoxesSenor Boxes

Mechanics design almost completedMechanics design almost completed3 planes on one main structure3 planes on one main structure

Minimal distance between Minimal distance between planes: 7mmplanes: 7mmMaximum level arm:200 mmMaximum level arm:200 mmMaterial: aluminumMaterial: aluminum

DESYDESY


Test Beam CampaignsTest Beam Campaigns

June 2007: DESYJune 2007: DESYCommissioning, First beamsCommissioning, First beams

August 2007: DESYAugust 2007: DESYFull system, First resultsFull system, First results

September 2007 (now): SPS @ CERNSeptember 2007 (now): SPS @ CERNDemonstrate the performance:Demonstrate the performance:

SpeedSpeedPrecisionPrecision


Sensors etc by IRES

Mechanics/Cooling by DESY

FE Boards by INFN

DAQ by Geneva


DESY Test beam IDESY Test beam I


DESY Test beam IIDESY Test beam II


Very Recent ResultsVery Recent Results

Fiducial area of trigger scintillators

Before / afteralignment

# tracks/trigger


Demonstrator Telescope is Demonstrator Telescope is operational operational →→ CERNCERN


Pixel Telescope on tourPixel Telescope on tour

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Telescope OutlookTelescope Outlook

The first version of the EUDET pixel telescope (“demonstrator”) The first version of the EUDET pixel telescope (“demonstrator”) is now is now available for usersavailable for usersFull telescope with digital readout and high resolution availablFull telescope with digital readout and high resolution available at the e at the end of 2008end of 2008

www.eudet.org

testbeam.desy.de

You can apply for travel money through You can apply for travel money through thethe Transnational AccessTransnational Access and use the and use the EUDET test beam infrastructureEUDET test beam infrastructure

You can apply for test beam time at DESY You can apply for test beam time at DESY (until end 2007 and after July 2008)(until end 2007 and after July 2008)

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ConclusionsConclusions

There is a rich R&D There is a rich R&D programmeprogramme for pixel sensors for a future for pixel sensors for a future vertex detector at an ILCvertex detector at an ILCFrom the large variety of options the community will have to picFrom the large variety of options the community will have to pick k ~ 2 solutions around 2009/2010 to converge on a detector design~ 2 solutions around 2009/2010 to converge on a detector design

Integration and DAQ issues should not be underestimated!Integration and DAQ issues should not be underestimated!There is an R&D review initiated by the ILC management at FNAL iThere is an R&D review initiated by the ILC management at FNAL in n OctoberOctober

In the meantime projects like EUDET try to help along the wayIn the meantime projects like EUDET try to help along the way

pixel detector r&d towards an ilc vertex detector€¦ · zstandard vlsi chip, with thin (10~15...

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