programmable logic circuits: introduction
DESCRIPTION
ELCT 903. Programmable Logic Circuits: Introduction. Dr. Eng. Amr T. Abdel-Hamid. Fall 2010. Course Contents. Introduction to Programmable Logic Devices Number systems and basic arithmetic operations Computer Arithmetic Basic Functions: Addition Multiplication Division - PowerPoint PPT PresentationTRANSCRIPT
Programmable Logic Circuits:
Introduction Dr. Eng. Amr T. Abdel-Hamid
ELCT 903
Fall 2010
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Course Contents Introduction to Programmable Logic Devices Number systems and basic arithmetic operations
Computer Arithmetic Basic Functions:
Addition
Multiplication
Division
Floating-point arithmetic
Special FP Functions Pipelining Basics Test Bench Generation
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Course Grading
ExamsQuizzes (10%) 3 Quizzes: best 2Midterm (20%)Final exam (40%)
Assignments (50%)
Project (25%)
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Project
Course Project: Building a Fast Floating Point MIPS Microprocessor
Other topics (after instructor approval) Mixed Signal Design IP Protection More in your master/graduation project topic to publish a paper?
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Project Phase 0: Select your partner (27/9/2010)
Submit list of your group members (2-4 per group)
Phase 1:
.
.
.
.
. Phase N: Finael Project Implementation + Report
(2 weeks before finals)
FINAL Non-Negotiable deadline
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In time & It is too LATE Policy In phases 0, & 1:
5% of project grade penalty per day for being late
In phase 2, to n: No late presentation is possible.
Honor code100% penalty for both copier and copy-giver of Any
Report/CODE.
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Why PLCs?
Main Design Goal: Construct an implementation with desired functionality.
Key design challenge: Simultaneously optimize numerous design metrics
Design metric: A measurable feature of a system’s implementationOptimizing design metrics is a key challenge
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Design Challenge
Size: the physical space required by the system
Performance: the execution time or throughput of the system
Power: the amount of power consumed by the system
Energy
What is the difference between power and Energy?
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Design Challenge
Time-to-prototype: the time needed to build a working version of the system
Time-to-market: the time required to develop a system to the point that it can be released and sold to customers
Maintainability: the ability to modify the system after its initial release
NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of designing the system
Flexibility: the ability to change the functionality of the system without incurring heavy NRE cost
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Time-to Market
Time required to develop a product to the point it can be sold to customers
Market window Period during which the product would have highest sales
Average time-to-market constraint is about 8 months Delays can be costly
Rev
enu
es (
$)
Time (months)
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Delayed Market Entry Simplified revenue model
Product life = 2W, peak at W
Time of market entry defines a triangle, representing market penetration
Triangle area equals revenue
Loss The difference between the
on-time and delayed triangle areas
On-time Delayedentry entry
Peak revenue
Peak revenue from delayed entry
Market rise Market
fall
W 2W
Time
D
On-time
DelayedRev
enu
es (
$)
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Design Productivity Gap
1981 leading edge chip required 100 designer months 10,000 transistors / 100 transistors/month
2002 leading edge chip requires 30,000 designer months 150,000,000 / 5000 transistors/month
Designer cost increase from $1M to $300M
10,000
1,000
100
10
1
0.1
0.01
0.001
Logic transistors per chip
(in millions)
100,000
10,000
1000
100
10
1
0.1
0.01
Productivity(K) Trans./Staff-Mo.
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
IC capacity
productivity
Gap
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The Mythical Man-Month
The situation is even worse than the productivity gap indicates In theory, adding designers to team reduces project completion time In reality, productivity per designer decreases due to complexities of team management and
communication In the software community, known as “the mythical man-month” (Brooks 1975) At some point, can actually lengthen project completion time! (“Too many cooks”)
10 20 30 400
10000
20000
30000
40000
50000
60000
43
24
1916 15 16
18
23
Team
Individual
Months until completion
Number of designers
1M transistors, 1 designer=5000 trans/month Each additional designer reduces for 100 trans/month So 2 designers produce 4900 trans/month each
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NRE and Unit Cost Metrics
Costs: Unit cost: the monetary cost of manufacturing each copy of the system,
excluding NRE cost NRE cost (Non-Recurring Engineering cost): the one-time monetary cost
of designing the system total cost = NRE cost + unit cost * # of units per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost
• Example– NRE=$2000, unit=$100– For 10 units
– total cost = $2000 + 10*$100 = $3000– per-product cost = $2000/10 + $100 = $300
Amortizing NRE cost over the units results in an additional $200 per unit
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NRE and unit cost metrics
Compare technologies by costs -- best depends on quantity Technology A: NRE=$2,000, unit=$100 Technology B: NRE=$30,000, unit=$30 Technology C: NRE=$100,000, unit=$2
• But, must also consider time-to-market
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Hardware Design Flow
BehavioralDescription
Logic Synthesis
Human
Gate LevelSynthesis
RTLImplementation
Layout(Masks)
Human
Layout Synthesis
Manufacturing
Product ASIC
Chip Programming
PLC
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Programmable Logic Many programmable logic devices are field- programmable, i.
e., can be programmed outside of the manufacturing environment
Most programmable logic devices are erasable and reprogrammable. Allows “updating” a device or correction of errors Allows reuse the device for a different design - the ultimate
in re-usability! Ideal for course laboratories
Programmable logic devices can be used to prototype design that will be implemented for sale in regular ICs. Complete Intel Pentium designs were actually prototyped
with specialized systems based on large numbers of VLSI programmable devices!
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Programmable Logic Circuits Facts:
It is most economical to produce an IC in large volumes Many designs required only small volumes of Ics
A programmable logic part can be: made in large volumes programmed to implement large numbers of different low-
volume designs
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Hierarchy of Logic Implementations
Logic
StandardLogic ASIC
ProgrammableLogic Devices(FPLDs)
GateArrays
Cell-BasedICs
Full CustomICs
CPLDsSPLDs(e.g., PALs) FPGA
s
TTL CMOS SemiCustomICs
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Programming Technologies
Programming technologies are used to:Control connections Build lookup tablesControl transistor switching
The technologiesControl connections
Mask programmingFuseAntifuseSingle-bit storage element
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Programming Technologies
The technologies (continued)Build lookup tables
Storage elements (as in a memory) Transistor Switching Control
Stored charge on a floating transistor gateErasable Electrically erasableFlash (as in Flash Memory)
Storage elements (as in a memory)
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Technology Characteristics Permanent - Cannot be erased and reprogrammed
Mask programmingFuseAntifuse
Reprogrammable Volatile - Programming lost if chip power lost
Single-bit storage element Non-Volatile
Erasable Electrically erasableFlash (as in Flash Memory)
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Field- Programmable Logic Devices• Component function is defined by
users program.• Logic Cells Fields are interconnected by programming.• Advantages:
- Flexible design that changes by reprogramming, ease of design changes- Reduce prototype-product time- Large scale integration (over 100 000 gates)- Reliability increased, low financial risk- Smaller device, low start-up cost
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Programmable Configurations Read Only Memory (ROM) - a fixed array of AND
gates and a programmable array of OR gates Programmable Array Logic (PAL) - a programmable
array of AND gates feeding a fixed array of OR gates. Programmable Logic Array (PLA) - a programmable
array of AND gates feeding a programmable array of OR gates.
Complex Programmable Logic Device (CPLD) /Field- Programmable Gate Array (FPGA) - complex enough to be called “architectures”
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ROM
• A special device (called a burner), used to put the information, supplies an electrical current to specific cells in the ROM that effectively blows a fuse in them = burning the PROM. From that point on, chip is read-only.
• PROM was the first type of user-programmable chip; address lines = logic circuit inputs data lines = logic circuit outputs
• PROMs are inefficient architecture for realizing logic circuit:
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Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) The fixed "AND" array is a
“decoder” with 3 inputs and 8outputs implementing minterms.
The programmable "OR“array uses a single line torepresent all inputs to anOR gate. An “X” in thearray corresponds to attaching theminterm to the OR
Read Example: For input (A2,A1,A0)= 011, output is (F3,F2,F1,F0 ) = 0011.
What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
Read Only Memory Example
D7D6D5D4D3D2D1D0
A2
A1A0
A
B
C
F0F1F2F3
X XX
XX
X
XX
XX
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PLA• PLA was the first device
developed for implementing
• Consist of two levels of logic gates - programmable “wired” AND-plane & OR-plane
),...,(),...,( 11 nn xxxxf
Note:
• Drawbacks:
• Expensive to manufacture
• Offered somewhat poor speed-performance
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Programmable Logic Array Example
3-input, 3-output PLA with 4 product terms
What are the equations for F1 and F2?
Could the PLA implement the functions without the XOR gates?
Fuse intact
Fuse blown
1
F1
F2
X
A
B
C
C C B B A A 0
1
2
3
4X
XX
X X
X
X
X
X
X
X
X
X
X A B
A C
B C
A B
X
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Programmable Logic Array (PLA) Compared to a ROM and a PAL, a PLA is the most flexible
having a programmable set of ANDs combined with a programmable set of ORs.
Advantages A PLA can have large N and M permitting implementation of
equations that are impractical for a ROM (because of the number of inputs, N, required
A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL Ors
Some PLAs have outputs that can be complemented, adding POS functions
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Programmable Logic Array (PLA) Disadvantages
Often, the product term count limits the application of a PLA.
Two-level multiple-output optimization is required to reduce the number of product terms in an implementation, helping to fit it into a PLA.
Multi-level circuit capability available in PAL not available in PLA. PLA requires external connections to do multi-level circuits.
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PAL• Overcame weaknesses
of PLA
•Single level of programmability - consists of a programmable “wired” AND-plane & fixed OR-gates
• Simpler to program and cheaper implementation
• Limited numbers of terms in each output
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Programmable Array Logic (PAL)
The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs.
Disadvantage ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates. Advantages
For given internal complexity, a PAL can have larger N and M Some PALs have outputs that can be complemented, adding
POS functions No multilevel circuit implementations in ROM (without external
connections from output to input). PAL hasoutputs from OR terms as internal inputs to all ANDterms, making implementation of multi-level circuits easier.
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Programmable Array Logic Example 4-input, 3-output PAL with
fixed, 3-input OR terms What are the equations for
F1 through F4?F1 =
F2 =
F3 =
F4 =
0 91 2 3 4 5 6 7 8
AND gates inputs0 9
Productterm
1
2
3
4
5
6
7
8
9
10
11
12
F1
F2
F3
F4
I35 C
I25 B
I 15 A
1 2 3 4 5 6 7 8
I4
X X
X X
X X X
X X
X
X
X
XX
X
X X
X
X X
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Programmable Logic Devices (PLD)
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Register PLA•Contain flip flops connected to the OR gate outputs
• Importance:
•Profound effect ondigital hardware design
•Basis for more sophisticated architectures
sequential circuits can be realized
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CPLD• Technology advanced
possibility to produce devices with higher capacity than SPLDs.
• Structure grows too quickly in size as the number of inputs is increased
• Integrating multiple SPLDs onto a single chip - the only feasible way to provide large capacity devices based on SPLD
• Programmably connect the SPLD blocks together
• Logic capacity up to the equivalent of about 50 typical SPLD devices
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Sequential PLD
Sequential Programmable Logic Device (SPLD)
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Basic Macrocell of Sequential PLD
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Complex PLD (CPLD)CPLD consists multiple
SPLD arrays and programmable interconnections. LAB = SPLD PIA: Programmable
Interconnect ArrayLAB & PIA are
programmed using software.
CPLD “density” is usually specified in terms of macrocells or LAB.
Altera & Xilinx are the major manufacturers.
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CPLD
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Altera CPLDsAltera produces three lines of
CPLDsEPLD seriesMAX seriesFLEX series
It also produces a completedesign toolMAX+PLUS 2Quartus II
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Altera MAX 7000 CPLD
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Xilinx CPLDs
CoolRunner II, XC9500 XC9500 is similar to MAX 7000, has PAL architecture CoolRunner II has PLA architecture
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FB = LABAIM
(Advanced Interconnect Matrix) = PIA
2~32 FBs
CoolRunner II Architecture
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FPGA
Provides logic blocks instead of AND or NAND planeTypical logic blocks is LUT
Volatile devicesProgrammable read-only memory (PROM) can be
used to make it nonvolatile
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FPGA• Difficult extending CPLDs architectures to higher
densities - a different approach is needed
• FPGAs comprise an array of uncommited circuit elements, called logic blocks, and interconnect resources
• FPGA configuration is performed through programming by the end user.
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FPGA
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LUT as Logic Block
(a) Circuit for a two-input LUT
x 1
x 2
f
0/1
0/1
0/1
0/1
0
0
1
1
0
1
0
1
1
0
0
1
x 1 x 2
(b) f 1 x 1 x 2 x 1 x 2 + =
(c) Storage cell contents in the LUT
x 1
x 2
1
0
0
1
f 1
f 1
f
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
x 2
x 3
x 1
3-input LUT
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FPGA concept Field Programmable
Gate Array Basic elements:
Configurable logic block (CLB)
I/O block interconnections
CLB is simpler than LAB or FB, but there are many more of them
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Configurable Logic Block (CLB) Many FPGAs
are volatile because their LUTs are based on SRAM.
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Which Way to Go?
Off-the-shelf
Low development cost
Short time to market
Reconfigurability
High performance
ASICs FPGAs
Low power
Low cost inhigh volumes