register clk - uniroma2.it

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Page 1: REGISTER CLK - uniroma2.it

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Page 2: REGISTER CLK - uniroma2.it

�� � � �� � � �

CLK

CLR (Clear)

LD (Load)

n

n

Data input x

Data output z

REGISTER

Control inputs

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Page 3: REGISTER CLK - uniroma2.it

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� ��� � � � � !!!!!!

" !!!!!!#� ��� � $% �� ��� � � � &' ( � � � ��� � � �

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)�* � � � * + $% � � � ��� � � �

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Page 4: REGISTER CLK - uniroma2.it

� � � � � � � � � � � � � � � � � � � � � � � �

z3

x3

z2

x2

z1

x1

z0

x0

CLR

CLK

LD

DQQ’

DQQ’

DQQ’

DQQ’

01MUX

01MUX

01MUX

01MUX

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Page 5: REGISTER CLK - uniroma2.it

�� � � � � � � � � � � � � � �� � �

Clock CLK

Input

Load LD

Output

tp

z

x

propagation delay

setup timetsu

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Page 6: REGISTER CLK - uniroma2.it

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* * * * * �

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Page 7: REGISTER CLK - uniroma2.it

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� � � ��� � � � � � ��� �� �

y’1y1x’x

CLK

y1

x’

y0

x

y0

x’

x

Y1

Y0

y1

y0

(a)

D flip-flops

y’1

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Page 8: REGISTER CLK - uniroma2.it

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� � � � � �� �� � �(b)

CLKCLR

LDY1

Y0

y1

y0

x

0

Reg

iste

r

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Page 9: REGISTER CLK - uniroma2.it

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CLK

CTRL

n

n

SHIFT REGISTER

Serial data input(left shift)

Serial data input(right shift)

xlxr

2

Parallel data input x

zParallel data output

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Page 10: REGISTER CLK - uniroma2.it

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CLK

CTRL

xr

2

xln-1

xn-1

zn-1

n-2

xn-2

zn-2

0

x0

z0

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Page 11: REGISTER CLK - uniroma2.it

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Page 12: REGISTER CLK - uniroma2.it

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Page 13: REGISTER CLK - uniroma2.it

� �

� � � � � � � � � � � � � �� � � �� � � �� � �

01

MUX

23 01

MUX

23 01

MUX

23 01

MUX

23

c1c0

DQ

DQ

DQ

DQ

xr

CK

x3 x2 x1 x0xl

z3 z2 z1 z0

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Page 14: REGISTER CLK - uniroma2.it

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CLK

CTRL

n-1 n-2 0

z

xr

(a)

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Page 15: REGISTER CLK - uniroma2.it

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�� � � � � � � � � � � � � � � �� � � � � � � � � �

CLK

CTRL2

n-1

xn-1

n-2

xn-2

0

x0

z(b)

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Page 16: REGISTER CLK - uniroma2.it

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CLKCTRL

n-1

zn-1

n-2

zn-2

0

z0

xr

(c)

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Page 17: REGISTER CLK - uniroma2.it

� �� � � �� � � �� � � �� � � �� � � � � � � �

CLK

CTRL2

n-1

xn-1

n-2

xn-2

0

x0

z

CLK

CTRL

n-1 n-2 0

z

xr

CLKCTRL

n-1

zn-1

n-2

zn-2

0

z0

xr

(a)

(b)

(c)

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�� � � � � � �� � �� � � � � � � � �

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Page 18: REGISTER CLK - uniroma2.it

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� �� � � � � � � � � � � � � � � � �� �� � � �

CLK

CTRL2

n-1

xn-1

n-2

xn-2

0

x0

System A

CLK

CTRL

n-1

zn-1

n-2

zn-2

0

z0

System B

xr

z

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� � � � �� � � � � � � � � � �

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Page 19: REGISTER CLK - uniroma2.it

� �

CLK

CTRL2

31

x31

30

x30

0

x0

FA

DQ

Q’

CLK

2

31

y31

30

y30

0

y0

CLK31

z31

30

z30

0

z0

carry-in

carry-out sum

Operand X

Operand Y

Result Z

ClockCycle Action

1 Load, clear carry FF

2-33 Add and shift

CTRL

CLR

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Page 20: REGISTER CLK - uniroma2.it

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Page 21: REGISTER CLK - uniroma2.it

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x(t) x(t-8)

z(t)

CLK

8-bit SHIFT REGISTERCTRL

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Page 22: REGISTER CLK - uniroma2.it

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" !!#� $% � ��� � � � � � � � � � � �� � � ��� � � �

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8-BIT SHIFT REGISTER

x

z

CTRL

CLK

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Page 23: REGISTER CLK - uniroma2.it

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8-BIT SHIFT REGISTER

07

8-BIT SHIFT REGISTER

07

8-BIT SHIFT REGISTER

07

8-BIT SHIFT REGISTER

07

CTRL

CLK

serial-in (right shift)

serial-in (left shift)

serial-out(left shift)

serial-out(right shift)

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Page 24: REGISTER CLK - uniroma2.it

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0/01/0

1/11/0

0/0

2/21/0

0/0

p-1/p-1

1/1

0/0x/TC = 0/0

s/z(state/output)

(input/terminal count)

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Page 25: REGISTER CLK - uniroma2.it

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