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Copyright © 2009 American Scientific PublishersAll rights reservedPrinted in the United States of America

Journal ofLow Power Electronics

Vol. 5, 1–12, 2009

Robust FinFET Memory Circuits with P-TypeData Access Transistors for Higher Integration

Density and Reduced Leakage Power

Sherif A. Tawfik1�∗ and Volkan Kursun21Department of Electrical and Computer Engineering, University of Wisconsin-Madison,

Madison, Wisconsin, USA2Department of Electronic and Computer Engineering, The Hong Kong University of

Science and Technology, Clear Water Bay, Kowloon, Hong Kong

(Received: xx Xxxx Xxxx; Accepted: xx Xxxx Xxxx)

A new six transistor (6T) SRAM cell with PMOS access transistors is proposed in this paper forreducing the leakage power consumption while enhancing the data stability and the integrationdensity of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance atthe data storage nodes during a read operation is reduced by utilizing PMOS access transistors.The read stability is enhanced by up to 62% while reducing the leakage power by up to 22% ascompared to a standard tied-gate FinFET SRAM cell with the same size transistors. One gate ofeach pull-up FinFET of the cross-coupled inverters is permanently disabled in order to achievewrite-ability with minimum sized transistors. The proposed independent-gate FinFET SRAM circuitwith P-type data access transistors reduces the idle mode leakage power, the write power, andthe cell area by up to 62%, 16.5%, and 25.53%, respectively, as compared to a standard tied-gateFinFET SRAM cell sized for similar data stability in a 32 nm FinFET technology.

Keywords: SRAM, Leakage Power, Enhanced Read Stability, Bitline Leakage, IndependentGate Bias.

1. INTRODUCTION

Scaling is the primary thrust behind the advancement ofCMOS technology. The increased sub-threshold and gate-dielectric leakage currents and the enhanced device sen-sitivity to process parameter fluctuations have becomethe primary barriers against further CMOS technologyscaling into the sub-45 nm regime. The FinFET offers dis-tinct advantages for simultaneously suppressing the sub-threshold and gate dielectric leakage currents as comparedto the traditional single-gate MOSFETs. The three elec-trically coupled gates and the thin silicon body suppressthe short-channel effects of a FinFET, thereby reducing thesub-threshold leakage current.1�13 The suppressed short-channel effects and the enhanced gate control over thechannel (lower sub-threshold swing) permit the use of athicker gate oxide in a FinFET as compared to a conven-tional single-gate transistor. The gate oxide leakage cur-rent of a FinFET is thereby significantly reduced. The thin

∗Author to whom correspondence should be addressed.Email: [email protected]

body of a FinFET is typically undoped or lightly doped.The carrier mobility is therefore enhanced and the devicevariations due to doping fluctuations are reduced in a Fin-FET as compared to a single-gate bulk transistor. Success-ful fabrication of tied-gate and independent-gate FinFETshave been demonstrated.2–4

The amount of embedded SRAM in modern micropro-cessors and systems-on-chips (SoCs) increases to meetthe performance requirements in each new technologygeneration.5 Lower voltages and smaller devices cause asignificant degradation in SRAM cell data stability withthe scaling of CMOS technology. Maintaining the datastability of SRAM cells is expected to become increas-ingly challenging as the device dimensions are scaled tothe sub-45 nm regime. In addition to the data stabilityissues, SRAM circuits are also important sources of leak-age due to the enormous number of transistors in thememory caches. The development of a robust SRAM cellthat can provide enhanced memory integration density andlower leakage power consumption with the emerging Fin-FET technologies is highly desirable.

J. Low Power Electronics 2009, Vol. 5, No. 4 1546-1998/2009/5/001/012 doi:10.1166/jolpe.2009.1048 1

Robust FinFET Memory Circuits with P-Type Data Access Transistors Tawfik and Kursun

In Ref. [15] a functional tied-gate FinFET SRAM cir-cuit is experimentally demonstrated. The sizes of the pull-down transistors are increased for data stability at theexpense of higher leakage power and cell area. In Ref. [17]asymmetric independent-gate FinFET SRAM cells are pre-sented. The back gate of the pull-down and access tran-sistors of the entire row are modulated with a specializedwordline driver. Multiple supply voltages are employed toreduce leakage and enhance stability. However, the circuitcomplexity increases and the supply voltages variationsbecome more significant when multiple supply voltagesare employed. In Refs. [14] and [16] a minimum sizedindependent-gate FinFET SRAM cell is presented. Theback gates of the access transistors are connected to thecorresponding storage nodes for dynamically enhancingboth read and write margins. With this SRAM cell, how-ever, the standby leakage power and the bitline leakage areincreased due to the lower threshold voltage of the accesstransistors with a turned on back gate. In Ref. [14], anotherSRAM cell is presented that is based on multiple fin orien-tations for achieving higher on current with the pull-downtransistors without increasing the sizes of these transistors.Having multiple fin orientations is, however, challengingfrom a manufacturing perspective with potentially highersusceptibility to process variations.

A new 6T independent-gate FinFET SRAM circuitwith PMOS access transistors is proposed in this paperfor simultaneously reducing the power consumption andthe circuit area while enhancing the data stability ofstatic memory circuits. All of the six transistors of anindependent-gate FinFET SRAM cell are sized minimumwithout sacrificing functionality and data stability with thenew technique. The voltage disturbances at the data storage

DrainSource

tsi

Hfin

L

Gate(a)

Drain

Back gate

Source

Front gate Insulator

(b)

Drain SourceFront gate

Back gate

L = 32 nm

25.6 nm

tsi = 8 nmtox = 1.6 nm

Heavily doped Si

GateOxide

Lightly doped Si

(c)

Fig. 1. FinFET structures. (a) 3D structure of a one-fin tied-gate FinFET. (b) 3D structure of a one-fin independent-gate FinFET. (c) Cross sectionaltop view of a FinFET with a drawn channel length of 32 nm.

nodes are reduced and the pull-up strengths of the cross-coupled inverters are enhanced during a read operationby employing PMOS access transistors. The data stabilityis thereby enhanced without the need for increasing thesizes of the transistors in the cross-coupled inverters. Onegate of each pull-up FinFET is permanently disabled forachieving write ability with the proposed technique. Theread static noise margin is enhanced by up to 62% withthe new SRAM cell while reducing the leakage power byup to 22% as compared to a standard tied-gate FinFETSRAM cell with the same size transistors. Furthermore,the leakage power, the write power, and the layout areaof the proposed SRAM cell are reduced by up to 62%,16.5%, and 25.53% respectively, as compared to a stan-dard FinFET SRAM cell sized for similar data stability ina 32 nm FinFET technology.

The paper is organized as follows. The FinFET technol-ogy is described in Section 2. The standard FinFET SRAMcircuits and the new independent-gate FinFET SRAM cir-cuit with P-type data access transistors are presented inSection 3. Data stability, power, delay, and area charac-teristics of the tied-gate and the independent-gate FinFETSRAM circuits are compared in Section 4. Finally, con-clusions are offered in Section 5.

2. FinFET TECHNOLOGY

In this section the device architectures for tied-gateand independent-gate FinFETs are presented. N-type andP-type FinFETs with a 32 nm gate length are designed andcharacterized using Taurus-Medici, a physics-based devicesimulator.9 The effect of different gate bias conditions onthe I–V characteristics of independent-gate FinFETs is

2 J. Low Power Electronics 5, 1–12, 2009

Tawfik and Kursun Robust FinFET Memory Circuits with P-Type Data Access Transistors

Table I. Device technology parameters.

Parameter Magnitude

Gate length (L) 32 nmEffective channel length (Leff ) 25.6 nmFin thickness (tsi) 8 nmFin height (Hfin) 32 nmOxide thickness (tox) 1.6 nmChannel doping 1015 cm−3

Source/drain doping 2×1020 cm−3

Gates work function (N-type FinFET) 4.5 eVGates work function (P-type FinFET) 4.9 eVMedici physical models AUGER, CONMOB SRFMOB,

FLDMOB, and DT.CUR

provided. The 3D architectures of the tied-gate and theindependent-gate FinFETs are shown in Figure 1. A topview of a FinFET indicating the critical physical dimen-sions is shown in Figure 1(c). The technology parame-ters of the FinFETs considered in this paper are listed inTable I.18

The width of a FinFET is quantized due to the verti-cal gate structure. The fin height determines the minimumtransistor width. Since the fin height is fixed in a FinFETtechnology, multiple parallel fins are utilized to increasethe width of a FinFET, as shown in Figure 2. The two ver-tical gates of a FinFET can be separated by an oxide ontop of the silicon fin, thereby forming an independent-gateFinFET as shown in Figure 1(b). An independent-gate Fin-FET provides two different active modes of operation withsignificantly different current characteristics determined bythe bias conditions of the two independent gates as shownin Figure 3.

In the dual-gate-mode, the two gates are biased withthe same signal to control the formation of a conductingchannel in an independent-gate FinFET. Alternatively, inthe single-gate-mode, one gate is biased with the inputsignal to induce channel inversion while the other gate isdisabled (disabled gate: biased with VGND in an N-typeFinFET and with VDD in a P-type FinFET). The two gatesare strongly coupled in the dual-gate-mode, thereby low-ering the threshold voltage (�Vth�� as compared to thesingle-gate-mode. The maximum drain current produced

Sourc

e Gate

Drain

Hfin

tsi

L

Fig. 2. Three-fin FET.

10–7

10–6

10–5

10–4

10–3

10–2

10–7

10–8

10–6

10–5

10–4

10–3

10–2

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Single-Gate-Mode

Dual-Gate-Mode

VGS (V)

Vth= 0.25 V Vth= 0.39 V

2.6X

(a)

I DS (

A/µ

m)

–0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0.0

Single-Gate-ModeDual-Gate-Mode

2.9X

VGS (V)

Vth= –0.5 V Vth= –0.3 V

(b)

I SD (

A/µ

m)

Fig. 3. Drain current characteristics of FinFETs. (a) N-FinFET.(b) P-FinFET. �VDS� = VDD = 0�8 V. T = 70 �C.

in the dual-gate-mode is therefore 2.6 (2.9) times higher ascompared to the single-gate-mode for an N-type (P-type)FinFET in a 32 nm FinFET technology, as shown inFigure 3. Furthermore, the switched gate capacitance ofa FinFET is halved in the single-gate-mode due to thedisabled back gate. The unique Vth modulation aspect ofindependent-gate FinFETs through selective gate bias isexploited in this paper to enhance the SRAM data stabil-ity and the integration density while lowering the staticand dynamic power consumption with minimum sizedtransistors.

3. FinFET SRAM CELLS

The design considerations for the reliable operation ofthe 6T FinFET SRAM circuits are provided in thissection. The tied-gate FinFET SRAM cells are discussedin Section 3.1. A previously published independent-gateFinFET SRAM circuit is described in Section 3.2. Thenew independent-gate FinFET SRAM circuit with PMOSaccess transistors is presented in Section 3.3.

3.1. Standard Tied-Gate FinFET SRAM Cells

The data stability of a memory circuit is most vulnerable toexternal noise during a read operation due to the intrinsic

J. Low Power Electronics 5, 1–12, 2009 3


disturbance produced by the direct data-read-access mech-anism of the standard 6T SRAM cells.10 In order tomaintain the read stability, the pull-down transistors mustbe stronger as compared to the bitline access transis-tors. Alternatively, for write ability, the bitline accesstransistors must be stronger as compared to the pull-uptransistors.5�10

Three tied-gate FinFET SRAM cells (SRAM-TG1,SRAM-TG2,15 and SRAM-TG3) with different sizes areconsidered in this paper, as shown in Figure 4. All of thesix transistors in SRAM-TG1 are sized minimum (one fin),as shown in Figure 4(a). A minimum sized SRAM cell ishighly desirable for maximizing the memory integrationdensity. The noise immunity of SRAM-TG1 is, however,weak. For sufficient noise immunity and read stability the

WL WL

BL BLBVDD VDD

Node1

Node2

1 fin

P1 P2

N1 N2

N3 N4

1 fin 1 fin

1 fin

1 fin 1 fin

(a)

WL WL

BL BLBVDD VDD

1 fin

P1 P2

N1 N2

N3 N4

2 fins 2 fins

1 fin

1 fin 1 fin

Node1

Node2

(b)

WL WL

BL BLBVDD VDD

1 fin

P1 P2

N1 N2

N3 N4

3 fins 3 fins

1 fin

1 fin 1 fin

Node1

Node2

(c)

Fig. 4. The tied-gate FinFET SRAM cells. (a) SRAM-TG1: All sixtransistors are sized minimum. (b) SRAM-TG2: The pull-down tran-sistors in the cross-coupled inverters have two fins. (c) SRAM-TG3:The pull-down transistors in the cross-coupled inverters have threefins.

pull-down transistors of the inverters in a tied-gate FinFETSRAM cell should have at least two fins, as illustrated inFigures 4(b and c). The standard approach of transistor siz-ing to enhance the cell stability unfortunately also causessignificantly higher leakage power consumption and largercell area. The power and area overheads of the transistorsizing based data stabilization techniques are high partic-ularly in a FinFET technology due to the quantized sizingof the transistors.

3.2. Previously Published Independent-GateFinFET SRAM Cell

A previously published independent-gate FinFET SRAMcell (SRAM-IG1)7�8�11 is described in this section. All ofthe transistors in the SRAM-IG1 have single fin (minimumwidth) as shown in Figure 5. The idle mode leakage powerconsumption is reduced with SRAM-IG1 while enhanc-ing the data stability as compared to the tied-gate FinFETSRAM circuits.

With SRAM-IG1, the pull-down transistors in the cross-coupled inverters are tied-gate FinFETs. Alternatively, thepull-up transistors in the cross-coupled inverters and thebitline access transistors are independent-gate FinFETsoperating in the single-gate-mode. The access transistorsact as weak high-Vth devices. The disturbance caused bythe direct-data-access mechanism during read operationsis thereby suppressed without the need for increasing thesizes of the pull-down transistors within the cross-coupledinverters. The data stability is therefore enhanced as com-pared to a tied-gate FinFET SRAM cell with the samesize transistors. A minimum sized NMOS access transistoroperating in the single-gate mode is significantly strongeras compared to a minimum sized PMOS pull-up transistoroperating in the single gate mode, as listed in Table II.Write ability is therefore achieved by permanently oper-ating the pull-up transistors in the single-gate-mode withSRAM-IG1.

VDD VDDBL BLB

Node1

Node2

WLWL

1 fin

P1 P2

N1 N2

N3N4

VDD

1 fin 1 fin

1 fin

1 fin 1fin

Fig. 5. A previously published independent-gate FinFET SRAM cell(SRAM-IG1).



Table II. DC characteristics of FinFETs (T = 70 �C).

Dual-gate mode Single-gate mode

Parameter N-type P-type N-type P-type

Ioff (nA/m) 255 64.7 255 64.7Ion (mA/m) 1.76 1.15 0.68 0.39Vth (V) 0.25 −0.3 0.39 −0.5

3.3. The New Independent-Gate FinFET SRAM Cellwith P-Type Data Access Transistors

The new independent-gate FinFET SRAM cell withP-channel access transistors (SRAM-IG2) is presented inthis section. All of the transistors in the SRAM-IG2have single fin (minimum width) as shown in Figure 6.The leakage power consumption is reduced with SRAM-IG2 while enhancing the data stability as compared toboth SRAM-TG1 and SRAM-IG1 with same size transis-tors. Furthermore, with SRAM-IG2, the leakage power isreduced and the integration density is enhanced while pro-viding similar data stability as compared to SRAM-TG2and SRAM-TG3.

With SRAM-IG2 the pull-down transistors in the cross-coupled inverters and the bitline access transistors are tied-gate FinFETs. Alternatively, the pull-up transistors withinthe cross-coupled inverters are independent-gate FinFETsoperating in the single-gate-mode. The bitline access tran-sistors are weak P-Type FinFETs as shown in Figure 6.The disturbance at the data storage nodes is therefore sup-pressed during a read operation thereby enhancing the datastability of SRAM-IG2. The bitline access transistors oper-ating in the dual-gate-mode are stronger as compared tothe pull-up transistors operating in the single-gate-mode(2.9 times higher on current in this 32 nm FinFET tech-nology). The write-ability is thereby achieved with a highwrite margin with the proposed circuit.

The operation of SRAM-IG2 is as follows. The word-line WL is maintained at VDD in an un-accessed SRAMcell. The bitline access transistors are turned off. Thedata in the SRAM cell is maintained by the cross-coupledinverters. The bitlines are periodically pre-charged to VDD.

VDD VDDBL BLB

Node1

Node2

P1 P2

N1 N2

VDD

1 fin 1 fin

1 fin 1finWL

1 fin

P3

1 fin

WL

1 fin

P4

Fig. 6. The new independent-gate FinFET SRAM cell (SRAM-IG2)with P-type tied-gate data access transistors.

WL transitions to VGND to initiate a read operation. Theaccess transistors P3 and P4 are turned on. Provided thatNode1 stores “0”, BL is discharged through P3 and N1.Alternatively, provided that Node2 stores “0”, BLB is dis-charged through P4 and N2. The P-type FinFETs P3 andP4 are weaker with significantly higher resistance as com-pared to the N-type FinFETs N1 and N2. The intrinsicdata disturbance that occurs due to the direct-data-read-access mechanism of the 6T SRAM cell topology is there-fore significantly suppressed with SRAM-IG2. The P-typeaccess transistors also enhance the pull-up strength onthe side that stores a “1”. The read stability is therebyenhanced with the proposed SRAM circuit (SRAM-IG2)as compared to both the standard minimum sized tied-gate FinFET SRAM circuit and the previously publishedindependent-gate FinFET SRAM circuit (SRAM-IG1).

The bitlines are periodically pre-charged to VDD. Priorto a write operation one of the bitlines is selectively dis-charged to VGND depending on the data to be written tothe SRAM cell. In order to write a “0” to Node1, the bit-line (BL) is selectively discharged. Alternatively, for writ-ing a “0” to Node2, the bitline-bar (BLB) is discharged.WL transitions to VGND to initiate the write operation. Thebitline access transistors are turned on. A “0” is forcedonto the data storage node that is connected to the dis-charged bitline. The two access transistors P3 and P4 act aslow-�Vth� devices operating in the dual-gate-mode. Alter-natively, the pull-up transistors of the cross-coupled invert-ers (P1 and P2) act as weaker high-�Vth� devices operatingin the single-gate-mode. Write ability is thereby achievedwith a high write margin with the proposed SRAM cell.Note that the P-type access transistor that is connected tothe discharged bitline can only discharge the data storagenode to �Vtp�. The transition to 0 V is completed by thepositive feedback provided by the cross-coupled inverterswith the assistance of the P-type access transistor that isconnected to the charged bitline. To write a “0” ontoNode1 BL is discharged to 0 V and BLB is charged toVDD as shown in Figure 7. The bitline access transistors

0.0

0.2

0.4

0.6

0.8

Time (ns)

Sig

nals

(V

)

WL Node2

Node1

VDD VDD

Node1

Node2

P1 P2

N1 N2

VDD

WLWL

0VVDD

P3P4

BL BLB

0.250.230.210.190.170.15

Fig. 7. Waveforms of the storage nodes of SRAM-IG2 during a writeoperation.



(P3 and P4) are turned on. Node1 is discharged to about�Vtp� before P3 is turned off (�Vtp� is about 0.3 V). WhenNode1 is at �Vtp� P2 and P4 are both strongly turned onproviding higher drain current as compared to N2. Node2is charged all the way up to VDD. N1 is turned on. Node1is thereby discharged all the way down to 0 V with theassistance of N1 after P3 is cut-off.

4. SIMULATION RESULTS

The read stability, the leakage power, the cell area, theactive mode power, and the access delays of the threetied-gate FinFET SRAM cells (SRAM-TG1, SRAM-TG2,and SRAM-TG3) and the two independent-gate FinFETSRAM cells (SRAM-IG1 and SRAM-IG2) are comparedin this section. The transistor sizing of the SRAM cells areas shown in Figures 4–6. The SRAM circuits are simulatedat the nominal design corner and under process parame-ter variations using mixed-mode simulations with Taurus-Medici.9 The SRAM cells are characterized for differentsupply voltages.

4.1. Read Stability

Static noise margin (SNM) is the metric used in this paperto characterize the read stability of the SRAM cells. TheSNM is the minimum DC noise voltage necessary to flipthe state of an SRAM cell.6 The data stability of a 6TSRAM circuit is most vulnerable to external noise duringa read operation due to the intrinsic disturbance producedby the direct data-read-access mechanism. It is assumedin this section, without loss of generality, that Node1 andNode2 store a “1” and a “0”, respectively. The read SNMsof the five SRAM cells are shown in Figure 8 with differ-ent supply voltages.

During a read operation with a 6T SRAM cell, the bit-line access transistors are turned on after the bitlines arepre-charged to VDD. The voltage of Node2 is raised dueto the voltage division between the access and the pull-down transistors. The increased voltage of Node2 can alsopotentially result in a voltage drop at Node1 if the pull-up

50

100

150

200

250

300

SRAM-TG1

SN

M (

mV

)

VDD = 0.6 V VDD = 0.8 V VDD = 1 V

SRAM-IG2SRAM-IG1SRAM-TG3SRAM-TG2

Fig. 8. The read SNMs of the FinFET SRAM cells. T = 70 �C.

strength of the corresponding inverter is weak. The voltagedisturbance at Node2 can be significantly suppressed eitherby employing stronger pull-down transistors (N1 and N2)with lower resistance as in SRAM-TG2 and SRAM-TG3or by employing weaker independent-gate bitline accesstransistors with higher resistance operating in the single-gate-mode as in SRAM-IG1. The enhancement in datastability by transistor sizing in SRAM-TG2 and SRAM-TG3, however, comes with a significant increase in leak-age power and area. Alternatively, with SRAM-IG1, theweaker bitline access transistors necessitate the utilizationof even weaker pull-up transistors for achieving write-ability. The weaker pull-up transistors with SRAM-IG1degrade the data stability at the node that stores a “1”.

With the proposed SRAM circuit technique, the bitlineaccess transistors are P-type tied-gate FinFETs. The tied-gate access transistors are intrinsically weaker with higherchannel resistance as compared to the tied-gate N-typepull-down transistors. The disturbance at Node2 is there-fore significantly suppressed during a read operation. Fur-thermore, with SRAM-IG2, the P-type access transistor P3enhances the pull-up strength at Node1 during a read oper-ation since P3 is in parallel with P1 (notice the shift in theDC transfer characteristics between the hold mode and theread mode in Fig. 9). Alternatively, with SRAM-TG1 andSRAM-IG1, the NMOS access transistor N3 does not playa significant role to strengthen the data storage at Node1.N3 is maintained cut-off until Node1 voltage is reducedsignificantly by a threshold voltage drop below VDD dueto noise in SRAM-TG1 and SRAM-IG1. The read SNMof SRAM-IG2 is enhanced by 59.7%, 60%, and 62.3%as compared to SRAM-TG1 for VDD = 0�6 V, 0.8 V, and1 V, respectively. The read SNM of SRAM-IG2 is alsoenhanced by 10%, 11% , and 15% as compared to SRAM-IG1 for VDD = 0�6 V, 0.8 V, and 1 V, respectively. The read

0

0.2

0.4

0.6

0.8

0 0.2 0.4 0.6 0.8

Node1

Nod

e2

SRAM-IG2Read SNM = 198 mV

SRAM-IG1/SRAM-IG2Hold SNM = 245 mV

SRAM-IG1Read SNM = 179 mV

Fig. 9. Butterfly curves of SRAM-IG1 and SRAM-IG2 during the holdmode and for a read operation. VDD = 0�8 V. T = 70 �C.



0

10

20

30

40

SRAM-TG1 SRAM-TG2 SRAM-TG3 SRAM-IG1 SRAM-IG2

Leak

age

pow

er (

nW) VDD = 0.6 V VDD = 0.8 V VDD = 1 V

Fig. 10. The leakage power consumptions of the FinFET SRAM cells.T = 70 �C.

SNMs of SRAM-IG2, SRAM-TG2, and SRAM-TG3 aresimilar.

4.2. Leakage Power Consumption

The leakage power consumption of the SRAM cells at70 �C is shown in Figure 10 for different supply volt-ages. The leakage power of an SRAM cell is determinedby the total effective transistor width that produces theleakage current. In SRAM-TG1, SRAM-IG1, and SRAM-IG2, all the transistors are sized minimum. Furthermore,with SRAM-IG2, the leakage current of the PMOS accesstransistors is lower as compared to the NMOS accesstransistors employed with the other SRAM cells. Notethat a minimum sized P-channel FinFET produces signif-icantly smaller sub-threshold and gate-oxide leakage cur-rents as compared to a minimum sized N-channel FinFETas listed in Table II. SRAM-IG2 therefore consumes thelowest leakage power among the memory circuits consid-ered in this paper. SRAM-IG2 consumes 21.3%, 21.4%,and 21.7% lower leakage power as compared to bothSRAM-TG1 and SRAM-IG1 for VDD = 0�6 V, 0.8 V, and1 V, respectively. Transistor sizing for enhanced data sta-bility comes at a significant cost of additional leakagepower with SRAM-TG2 and SRAM-TG3, as illustratedin Figure 10. The leakage power consumed by SRAM-IG2 is 61.8%, 61.5%, and 61.4% lower as compared toSRAM-TG3 for VDD = 0�6 V, 0.8 V, and 1 V, respectively.Furthermore, by utilizing minimum sized P-type accesstransistors, the bitline leakage current is reduced by 62%,61.2%, and 61% with SRAM-IG2 as compared to the otherSRAM circuits for VDD = 0�6 V, 0.8 V, and 1 V, respec-tively, as shown in Figure 11.

4.3. SRAM Cell Area

The thin-cell layouts of the SRAM cells are shown inFigure 12. The layout rules are listed in Table III. The finpitch is assumed to be 6 times the fin thickness in the lay-outs. SRAM-TG1 and SRAM-IG2 have the smallest areasince all six transistors are sized minimum with only onefin. SRAM-IG1 occupies a larger cell area (23% largeras compared to SRAM-IG2) due to the extra contacts.

1

2

3

4

5

6

7

SRAM-TG1 SRAM-TG2 SRAM-TG3 SRAM-IG1 SRAM-IG2

Bitl

ine

leak

age

curr

ent (

nA) VDD = 0.6 V VDD = 0.8 V VDD = 1 V

Fig. 11. The bitline leakage current of the FinFET SRAM cells.T = 70 �C.

SRAM-TG2 and SRAM-TG3 occupy a larger area as com-pared to SRAM-IG2 due to the larger pull-down tran-sistors. The areas of SRAM-TG2 and SRAM-TG3 are17% and 34% larger as compared to SRAM-IG2, respec-tively. Furthermore, only one metal layer is used within theSRAM-IG2 cell unlike SRAM-IG1 that requires the uti-lization of two metal layers, as shown in Figure 12. Notethat the extra contacts with SRAM-IG2 do not increase thecell area since these contacts are shared between neigh-boring cells in a memory array.

4.4. Active Mode Power and Access Speed

The junction and gate-oxide capacitances of the accesstransistors are extracted for each SRAM cell. The lengthsof the bitlines and the wordlines are estimated based onthe cell layout dimensions. �-type RC networks that rep-resent the bitline and the wordline parasitics of a 256 bit×128 bit memory array are attached to each SRAM cir-cuit. The normalized active mode power consumptions anddelays of the five FinFET SRAM circuits are shown inFigure 13 for different supply voltages (VDD = 0�6 V, 0.8 V,and 1 V). The read delay is the time period from the50% point of the WL low-to-high (high-to-low in case ofSRAM-IG2) transition until a 200 mV voltage differenceis developed between the bitlines. The write delay is thetime period from the 50% point of the WL low-to-high(high-to-low in case of SRAM-IG2) transition until thestorage node is discharged to VDD/2 (from an initial voltageof VDD�. The read and write power consumptions includethe power consumed to pre-charge the bitlines, the word-line driver power consumption, and the SRAM cell powerconsumption.

SRAM-IG1 consumes the lowest read and write powerand has the shortest write delay due to the smaller wordlineand internal node parasitic capacitances as compared tothe other SRAM cells. Alternatively, SRAM-IG1 has thelongest read delay due to the weaker access transistors.The read delay of SRAM-IG1 is 109%, 76%, and 59%longer as compared to SRAM-TG1 for VDD = 0�6 V, 0.8 V,and 1 V, respectively.



VDD BLBVGND

WL

BL

WL

VDD VGND

(a)

VDD BLBVGND

WL

BL

WL

VDD VGND

(b)

VDD BLBVGND

WL

BL

WL

VDD VGND

(c)

VDD BLBVGND

WL

BL

WL

VDD VGNDVGND

VGND

(d)

VGND BLBVDD

WL

BL

WL

VGND VDD

(e)

Fig. 12. Layouts of the FinFET SRAM cells. (a) SRAM-TG1. (b) SRAM-TG2. (c) SRAM-TG3. (d) SRAM-IG1. (e) SRAM-IG2. SRAM-TG1 andSRAM-IG2: 0.18 m2. SRAM-TG2: 0.21 m2. SRAM-TG3: 0.24 m2. SRAM-IG1: 0.22 m2.

The write power of SRAM-IG2 is lower than SRAM-TG2 and SRAM-TG3 due to the smaller wordline para-sitics and the smaller internal node capacitances. The writepower of SRAM-IG2 is also lower than SRAM-TG1 due

Table III. Layout rules.

Gate length 2�Fin thickness �/2Fin pitch (6× fin thickness) 3�Contact hole 2�×2�Contact size 4�×4�Metal1 and metal2 width 4�Contact–contact separation 2�Active to active separation (same type) 3�Active to active separation (opposite type) 4�Poly to active separation 2�Poly to poly separation 3�Metal to metal separation 2�

to the smaller internal node capacitances. The write powerof SRAM-IG2 is reduced by 16.52%, 9%, and 12% ascompared to SRAM-TG3 for VDD = 0�6 V, 0.8 V, and 1 V,respectively. The read delay of SRAM-IG2 is 85%, 43%,and 31% longer as compared to SRAM-TG1 for VDD =0�6 V, 0.8 V, and 1 V, respectively. The read delay penaltywith SRAM-IG2 is significantly lower as compared toSRAM-IG1 since a single fin PMOS access transistor oper-ating in the dual-gate-mode produces higher on current ascompared to a single fin NMOS transistors operating inthe single-gate-mode as listed in Table II.

Writing to an SRAM cell is achieved by discharging oneof the bitlines to ground and maintaining the other bitlineat VDD. Successful writing to an SRAM cell can also beachieved with a voltage higher than 0 V on the dischargedbitline (incomplete/partially discharged bitline). The writemargin is the maximum voltage of the partially discharged



0

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ay a

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ower

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ower

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Read delay Write delay

Read power Write power





(a)

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SRAM-IG2SRAM-IG1SRAM-TG3SRAM-TG2

SRAM-TG1 SRAM-IG2SRAM-IG1SRAM-TG3SRAM-TG2

SRAM-TG1 SRAM-IG2SRAM-IG1SRAM-TG3SRAM-TG2

Fig. 13. The active mode power consumption and propagation delaysof the SRAM circuits. For each SRAM circuit, the power and delay arenormalized with respect to SRAM-TG1. T = 70 �C. (a) VDD = 0�6 V.(b) VDD = 0�8 V. (c) VDD = 1 V.

bitline that achieves a successful transfer of a “0” into the6T SRAM cell.12�14 The write margin is measured differ-ently in this section as compared to Refs. [12] and [14]since the two bitlines assist in the writing of the proposedSRAM cell. The write margin is measured in this sectionas the maximum voltage amplitude of a DC noise sig-nal that is applied to the two bitlines with equal ampli-tudes and opposite polarity for which a successful writingis achieved. The polarity of the DC noise signal that isapplied to the discharged (charged) bitline is positive (neg-ative). The content of an SRAM cell with a higher writemargin is easier to be modified. The write margins for theSRAM circuits are listed in Table IV.

The write margin of the tied-gate FinFET SRAM cellsis reduced when the size of the pull-down transistors isincreased due to the reduced switching threshold voltageof the cross-coupled inverters and due to the increased

Table IV. The write margins of the SRAM cells (T = 70 �C).

Write margin (mV)

SRAM cell VDD = 0�6 V VDD = 0�8 V VDD = 1 V

SRAM-TG1 227 306 395SRAM-TG2 162 202 242SRAM-TG3 127 153 180SRAM-IG1 96 127 160SRAM-IG2 183 250 316

internal node capacitances. The write margin of the pro-posed SRAM-IG2 is enhanced by up to 30% and 76% ascompared to SRAM-TG2 and SRAM-TG3, respectively,due to the reduced internal node parasitic capacitances.Alternatively, the write margin of SRAM-IG2 is up to 98%higher as compared to SRAM-IG1 due to the strongeraccess transistors (refer to Table II).

From an application point of view, SRAM-IG2 is themost attractive choice at the higher levels of memorybanks for which the enhanced integration density and thelower leakage power consumption are the most importantdesign criteria. Alternatively, for a speed-critical first levelcache with a smaller amount of memory, the SRAM-TG2can be attractive despite the larger cell area, due to thehigher read speed with reasonable write speed and datastability. SRAM-TG1 is not a practical choice due to theunacceptably small read static noise margin.

4.5. Process Variations

The effect of process variations on the tied-gate andthe independent-gate FinFET SRAM cells is evaluatedin this section. 1500 Monte-Carlo simulations are runwith Taurus-Medici using a PERL script. The channellength, the fin height, the fin thickness, and the gate oxidethickness are assumed to have independent Gaussian distri-butions. The parameters of each transistor are varied inde-pendently except for the multi-fin FETs. For the multi-finFETs, full correlation between the fins is assumed. Thechannel length and the fin thickness have 3� variationsof 20%. The fin height has a 3� variation of 10%. Theoxide thickness has a 3� variation of 5%. The statisticaldistributions of the leakage power are shown in Figures 14and 15 for T = 27 �C and T = 70 �C, respectively. Thestatistical distributions of the SNM of the SRAM cells areshown in Figures 16 and 17 for T = 27 �C and T = 70 �C,respectively.

With the proposed independent-gate SRAM cell SRAM-IG2, the mean and the standard deviation (SD) of theleakage power are reduced by 64.5% and 66.4%, respec-tively, as compared to SRAM-TG3 at room temperature asshown in Figure 13. The mean and the standard deviation(SD) of the leakage power are reduced by 61% and 65%,respectively, with SRAM-IG2 as compared to SRAM-TG3at T = 70 �C as shown in Figure 15. Furthermore, with



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SRAM-TG2Mean = 4.8 nW. SD = 1.6 nW


SRAM-IG2Mean = 2.3 nW. SD = 0.8 nW

SRAM-TG1/ SRAM-IG1Mean = 3 nW. SD = 0.9 nW

Fig. 14. Statistical leakage power distributions of the FinFET SRAMcells. VDD = 0�8 V. T = 27 �C. SD: standard deviation.

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SRAM-TG3Mean = 27 nW. SD = 8.1 nW

SRAM-IG2Mean = 10.5 nW. SD = 2.8 nW

SRAM-TG1/ SRAM-IG1Mean = 13.2 nW. SD = 3.4 nW

Fig. 15. Statistical leakage power distributions of the FinFET SRAMcells. VDD = 0�8 V. T = 70 �C. SD: standard deviation.

SRAM-IG2 the mean SNM is enhanced by 55% and 60%as compared to SRAM-TG1 for T = 27 �C (shown inFig. 16) and T = 70 �C (shown in Fig. 17), respectively.

The write margin is evaluated under process parame-ter, supply voltage, and temperature variations. The Fin-FET on current distribution is generated with 1000 samples

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55% higher

SRAM-TG1Mean = 135 mV

SRAM-IG2Mean = 208 mV

SRAM-TG1SRAM-TG2SRAM-TG3SRAM-IG1SRAM-IG2

Fig. 16. Statistical SNM distributions of the FinFET SRAM cells.VDD = 0�8 V. T = 27 �C.

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75 95 115 135 155 175 195 215SNM (mV)

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SRAM-TG1SRAM-TG2SRAM-TG3SRAM-IG1SRAM-IG2

SRAM-TG1Mean = 124 mV

SRAM-IG2Mean = 198.4 mV

60% higher

Fig. 17. Statistical SNM distributions of the FinFET SRAM cells.VDD = 0�8 V. T = 70 �C.

assuming independent Gaussian distributions for the chan-nel length (20% 3� variation), the fin thickness (20%3� variation), the oxide thickness (5% 3� variation), andthe fin height (10% 3� variation). The parameters of thestrong and the weak devices are identified from the Fin-FET on current distributions. The on current of the weakdevice is lower than the mean on current by one sigma.Alternatively, the on current of the strong device is higherthan the mean on current by one sigma, as shown inFigure 18.

The worst case process corner for write margin is theprocess corner characterized by the weak bitline accesstransistors and the strong pull-up transistors. The writemargins of the SRAM cells at the worst case process cor-ner are listed in Table V for different temperatures andsupply voltages. As shown in Table V, SRAM-IG2 hashigher write margin as compared to SRAM-TG2, SRAM-TG3, and SRAM-IG1. The write margin of SRAM-IG2is enhanced by up to two-times (∼2X) as compared toSRAM-IG1 depending on the supply voltage and thetemperature.

σσσ σ

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P-type FinFET N-type FinFET

Strong deviceWeak device

Strong deviceWeak device

Fig. 18. 1000 samples Monte-Carlo statistical distributions of theon-current of the single-fin FinFETs operating in the dual-gate mode.VDD = 0�8 V. T = 70 �C.



Table V. The write margin of the SRAM cells at the worst-case processcorner.

Write margin (mV)

T VDD SRAM- SRAM- SRAM- SRAM- SRAM-(�C) (V) TG1 TG2 TG3 IG1 IG2

27 0.6 207 145 114 77 14327 0.8 278 178 138 106 18927 1.0 352 211 160 133 22770 0.6 209 142 108 76 15570 0.8 278 169 128 102 21670 1.0 352 211 148 129 258

5. CONCLUSIONS

A new independent-gate FinFET SRAM cell is proposedin this paper for simultaneously enhancing the read datastability and the memory integration density while reduc-ing the standby mode power consumption. All of the sixtransistors of the proposed SRAM cell are sized mini-mum. The voltage disturbance at the data storage nodesduring a read operation is reduced by employing P-typebitline access transistors. The pull-up FinFETs in thecross-coupled inverters are permanently operated in thesingle-gate-mode with the proposed SRAM cell, therebyachieving write-ability with minimum sized transistors.The read SNM is enhanced by up to 62% with the proposedindependent-gate FinFET SRAM cell while reducing theleakage power by up to 22% as compared to a tied-gateFinFET SRAM cell with the same size transistors. Alter-natively, as compared to a 6 T tied-gate FinFET SRAMcell that is sized for comparable read static noise margin,the leakage power, the write power, and the cell area arereduced by up to 62%, 16.5%, and 25.53%, respectively.

References

1. E. Nowak et al., Turning silicon on its edge. IEEE Circuits andDevices Magazine 20 (2004).

2. Y. Liu et al., Cointegration of high-performance tied-gate three-terminal FinFETs and variable threshold-voltage independent-gatefour-terminal FinFETs with asymmetric gate-oxide thicknesses.IEEE Electron Device Letters 28, 517 (2007).

3. Y. X. Liu et al., 4-Terminal FinFETs with high threshold voltagecontrollability, Proceedings of the IEEE Device Research Confer-ence, June (2004), Vol. 1, pp. 207–208.

4. J. Kedzierski et al., Metal-gate FinFET and fully-depleted SOIdevices using total gate silicidation, Proceedings of the IEEE Elec-tron Devices Meeting, December (2002), pp. 247–250.

5. V. Kursun, S. A. Tawfik, and Z. Liu, Leakage-aware design ofnanometer SoC, Proceedings of the IEEE International Symposiumon Circuits and Systems, May (2007), pp. 3231–3234.

6. E. Seevinck, F. J. List, and J. Lohstroh, Static-noise margin analysisof MOS SRAM cells. IEEE Journal of Solid-State Circuits 22, 748(1987).

7. M. Yamaoka et al., Low power SRAM menu for SOC applica-tion using Yin-Yang-feedback memory cell technology, Proceed-ings of the IEEE Symposium on VLSI Circuits, June (2004),pp. 288–291.

8. B. Giraud et al., A comparative study of 6T and 4T SRAM cellsin double-gate CMOS with statistical variation, Proceedings ofthe IEEE International Symposium on Circuits and Systems, May(2007), pp. 3022–3025.

9. Medici Device Simulator, Synopsys, Inc. (2006).10. Z. Liu and V. Kursun, High read stability and low leakage cache

memory cell, Proceedings of the IEEE International Symposium onCircuits and Systems, May (2007), pp. 2774–2777.

11. S. A. Tawfik and V. Kursun, Low power and stable FinFETSRAM with static independent gate bias for enhanced inte-gration density, Proceedings of the IEEE International Confer-ence on Electronics, Circuits, and Systems, December (2007),pp. 443–446.

12. K. Zhang et al., A 3-GHz 70-Mb SRAM in 65-nm CMOS tech-nology with integrated column-based dynamic power supply. IEEEJournal of Solid-State Circuits 41, 146 (2006).

13. S. A. Tawfik and V. Kursun, Low-power and compact sequential cir-cuits with independent-gate FinFETs. IEEE Transactions on ElectronDevices 55, 60 (2008).

14. Z. Guo et al., FinFET-Based SRAM design, Proceedings of the IEEEInternational Symposium on Low Power Electronics and Design,August (2005), pp. 2–7.

15. E. J. Nowak et al., A functional FinFET-DGCMOS SRAM cell,Proceedings of the IEEE International Electron Devices Meeting,December (2002), pp. 411–414.

16. A. Carlson et al., FinFET SRAM with enhanced read/write margins,Proceedings of the IEEE International SOI Conference, October(2006), pp. 105–106.

17. R. V. Joshi et al., A high-performance, low leakage, and sta-ble SRAM row-based back-gate biasing scheme in FinFET tech-nology, Proceedings of the IEEE VLSI Design, January (2007),pp. 665–672.

18. S. A. Tawfik and V. Kursun, Parameter space exploration for robustand high-performance n-channel and p-channel symmetric double-gate FinFETs, Proceedings of the IEEE Asia Symposium on QualityElectronic Design, July (2009), pp. 1–8.

19. S. A. Tawfik and V. Kursun, Compact FinFET memory circuits withP-type data access transistors for low leakage and robust operation,Proceedings of the IEEE/ACM International Symposium on QualityElectronic Design, March (2008), pp. 855–860.

Sherif A. TawfikSherif A. Tawfik received the B.S. and M.S. degrees in Electronics and Communications Engineering from Cairo University, Cairo,Egypt, in 2003 and 2005, respectively and the Ph.D. degree in Electrical and Computer Engineering at the University of Wisconsin-Madison, USA in 2009. His research interests are in the area of low-power and variations-tolerant integrated circuit design andemerging integrated circuit technologies.

Volkan KursunVolkan Kursun received the B.S. degree in Electrical and Electronics Engineering from the Middle East Technical University, Ankara,Turkey in 1999, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, New York,USA in 2001 and 2004, respectively. He performed research on mixed-signal thermal inkjet integrated circuits with Xerox Corporation,



Webster, New York, USA in 2000. During summers 2001 and 2002, he was with Intel Microprocessor Research Laboratories, Hillsboro,Oregon, USA responsible for the modeling and design of high frequency monolithic power supplies. During summer 2008, he wasa visiting professor at the Chuo University, Tokyo, Japan. He served as an assistant professor in the Department of Electrical andComputer Engineering at the University of Wisconsin-Madison, USA from August 2004 to August 2008. He has been an assistantprofessor in the Department of Electronic and Computer Engineering at the Hong Kong University of Science and Technology, People’sRepublic of China since August 2008. His current research interests are in the areas of low voltage, low power, and high performanceintegrated circuit design and emerging integrated circuit technologies. He has more than ninety publications and five issued andtwo pending patents in the areas of high performance integrated circuits and emerging semiconductor technologies. Dr. Kursun isthe author of the book Multi-Voltage CMOS Circuit Design (John Wiley & Sons Ltd., August 2006). He serves on the technicalprogram and organizing committees of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED),the ACM/SIGDA Great Lakes Symposium on VLSI (GLSVLSI), the IEEE International Symposium on Circuits and Systems (ISCAS),the IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), the IEEE Asia Pacific Conference on Circuits andSystems (APCCAS), the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), the IEEE/ACM Asia Symposiumon Quality Electronic Design (ASQED), and the IEEE Asian Solid-State Circuits Conference (A-SSCC). He served on the editorialboard of the IEEE Transactions on Circuits and Systems II (TCAS-II) from 2005 to 2008. Dr. Kursun is an Associate Editor of theJournal of Circuits, Systems, and Computers (JCSC), the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), andthe IEEE Transactions on Circuits and Systems I (TCAS-I).


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