scalable test pattern generator design method for bist petr fišer, hana kubátová czech technical...

Scalable Test Pattern Scalable Test Pattern Generator Design Method for Generator Design Method for

BISTBISTPetr FiPetr Fiššer, Hana Kuber, Hana KubátováátováCzech Technical University in PragueCzech Technical University in Prague

Faculty of Electrical EngineeringFaculty of Electrical EngineeringDept. of Computer Science & EngineeringDept. of Computer Science & Engineering

LATW 2008, 17. – 20.2., PueblaLATW 2008, 17. – 20.2., Puebla 22

OutlineOutline

• Motivation

• Proposed BIST scheme

• The Column-Matching algorithm

• Customizing the design process

• Experimental results

• Conclusions


MotivationMotivation

Four important aspects in BIST: Fault coverage

Test time

BIST area overhead

BIST design time



Different ASIC designers have different requirements for BIST

Design the BIST equipment as fast as possible, regardless the area overhead and the fault coverage (no time to wait, the deadline is approaching!)

Design the BIST equipment to be as small as possible, regardless the time it takes (low power)

High fault coverage is the most important aspect, the area overhead is next. The design time is not that important (common practice)



We propose a method offering a bigtrade-off between all these criteria:

Fault coverage

Test time

BIST area overhead

BIST design time



We propose a method offering a bigtrade-off between all these criteria:

Fault coverage

Test time

BIST area overhead

BIST design time

Given by ATPG100% fault coverage will be

considered


The Proposed BISTThe Proposed BIST

• Mixed-Mode (Hybrid) BIST

• Two separated phases: pseudorandom and deterministic

LFSR

Decoder

Sw itch

CUT

M ISR

TPG

mode

m

m

m


The Decoder DesignThe Decoder Design

The Column-Matching method

Deterministic BIST:LFSR produces pseudo-random code words(C-matrix)

These are then transformed into deterministic tests computed by ATPG(T-matrix)



The Column-Matching method – basic principles

Try to reorder test patterns, so that most of the Decoder outputs will be implemented as wires – a Match

This will be accomplished when two particular columns of the LFSR and test matrices will be equal

Combinational logic – the order is insignificant

Unmatched outputs have to by synthesized by a Boolean minimizer



The Column-Matching method – example

y0 = x0y1 = x1y2 = x2’y3 = x1y4 = x0’ + x1

a 10001b 11100c 01110d 00111e 10111

A 1X000B 1010XC 11011

0001D X

y - y0 4x - x0 4

LFSR patterns= matrixC

ATPG vectors= matrixT

?a 10001b 11100c 01110d 00111e 10111

A 1X000B 1010XC 11011

0001D X

y - y0 4x - x0 4

e 10111 A

d 00111 D

1 000a 10001 B 1010Xb 11100 C 11011

0001

0


Mixed-Mode BISTMixed-Mode BIST

1. Simulate several LFSR patterns

2. Determine undetected faults

3. Compute a test for them (ATPG)

4. Design a decoder generating vectors for this test and following LFSR patterns



10100010100010110110010111000111100011100011110111

Pseudo-randomsequence }Simulate Non-covered

faultsATPG Test

Vectors

1X0001010X110110001X

101001101101011 0000110000

(non-det)Deterministicsequence

} }

x-x0 4 y-y0 4

LFSR

10100010100010110110010111010011011010110000110000

Final test sequence

ColumnMatching



LFSR

CUT

1

x0 x1 x2 x3 x4

y0 y1 y2 y3 y4

Deterministicmode

y = x0 0

’

’

y = xy = xy = xy = x +x

1 1

2 2

3 1

4 0 1+

Decoder

Switch


Scaling the Lengths of the PhasesScaling the Lengths of the Phases

Pseudorandom phaseTo detect easily detectable faults

Deterministic phaseTo generate deterministic vectors

Longer PR phase Longer Det. phase

BIST design time Decreased Increased

BIST area overhead Decreased Decreased

BIST run length Increased Increased


Reducing the LFSR WidthReducing the LFSR Width

By weighted pattern testing3-weight logic

The weights are computed for RPRFs

The LFSR inputs are AND-ed and OR-ed to produce weights

Decoder

Switch

CUT

MISR

TPG

mode

m

m

m

LFSR

r<mWeighting logic


Reducing the LFSR WidthReducing the LFSR Width

ISCAS’89 s13207.1 benchmark (700 inputs)

LFSR (r) w. gates Design time [s] GEs

700 (no weights) - 4720 2975

700 (3 weights) 518 245 3361

200 (3 weights) 365 653 1231

50 (3 weights) 365 2835 671

45 (3 weights) 365 3423 693

40 (3 weights) 365 29434 1288

30 (3 weights) 365 - -


Experimental Results – Area Experimental Results – Area Overhead ComparisonOverhead Comparison

Comparison with state-of-the-art methods. Equal test lengths, the area overhead is compared

• Compared with:Bit-Fixing[N.A. Touba, E.J. McCluskey: Bit-Fixing in Pseudorandom Sequences for Scan BIST, IEEE Transactions on CAD, Vol. 20, No. 4, April 2001, pp. 545-555]Weighted-pattern BIST[S. Wang: Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST. Proc. 2001 IEEE International Test Conference]Row Matching[M. Chatterjee, D.K. Pradhan: A BIST Pattern Generator Design for Near-Perfect Fault Coverage, IEEE Transactions on Computers, vol. 52, no. 12, December 2003, pp. 1543-1558]

CM always better

CM better in 71%

CM better in 60%


Experimental ResultsExperimental Results

Hard-to-test (and “big”) benchmarks

Bench PR testability

Test length Time [s] Overhead

c2670 4.5 M 5 K 437 15 %

c7552 > 100 M 10 K 887 16 %

s9234.1 10 M 200 K 3500 5 %

s13207.1 100 K 50 K 13 0.6 %

s15850.1 > 10 M 100 K 1200 5 %

s38417 > 10 M 100 K 4600 14 %

s35841.1 > 1 G 100 K 34 1 %

b12 5 M 10 K 1080 7 %

b15 > 100 M 1 M 4800 17 %


ConclusionsConclusions

The Column-Matching principle proposedInfluence of the lengths of the phases is studiedVery scalable, many design parameters freely adjustableThe results obtained by CM are mostly better (wrt. the area overhead) than those obtained by state-of-the-art methodsThe method should serve as a basic guideline how to design more complex BIST designs, i.e., the multiple‑scan chain based BIST, the STUMPS architecture, etc.It can be very advantageously used to test SoCs, since the LFSR may be reused for more cores.

scalable test pattern generator design method for bist petr fišer, hana kubátová czech technical...

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