sdss7 - dsp and backends intro, 12 jul 2013 digital signal processing basics and ao back-ends luis...

SDSS7 - DSP and Backends Intro, 12 Jul 2013

Digital Signal Processing Basics and AO Back-Ends

Luis A. QuinteroDigital Section Head

Electronics DepartmentArecibo Observatory


Introduction to Digital Signal Processing


System - World

time

Quantity

Transducer

ELECTRICAL VARIABLEResistance, Capacitance,Voltage, etc

time

Voltage

SignalConditioning

Continuous Signal Acquisition - Transducers


Continuous-time Signal (real signal)

time

Amplitude

time

Discrete-time SignalAmplitude

Sampling


Signal Storage in Computers

time

1V

-1V

+ 0.40

- 0.90

…

- 0.45

+ 0.70

- 0.47

- 0.82

+ 0.30http://www.iusb.edu/


Analog to Digital Converter – Quantization

time

+ 0.40

- 0.90

…

- 0.45

+ 0.70

- 0.47

- 0.82

+ 0.30

4

6

…

1

4

01234567

2

5

2

A/D …


Analog to Digital Converter – Quantization

time

4

6

…

1

4

2

5

2

Digital-to-AnalogConverter

D/A…

http://www.iusb.edu/


Digital Signal Processing System

Digital-to-AnalogConverter

D/A…A/D

Analog-to-Digital Converter

…

Computer

Data StorageData Processing - Math Operations - Filters - Fourier Transform - Data Format

Computer (Digital System) - Micro Processor - DSP (MAC) - Logic Circuit - ASIC - PAL/CPLD - FPGA


Sampling Rate – Analog to Digital

time

time

1 Second

Fs = 9 samples/second = 9Hz

Fs = 19 samples/second = 19Hz

Better signal reconstructionMore computer memory / BW and $$


Analog to Digital Converter - Clock Input

A/D …

clk

ANALOG DIGITAL

Clock for digital circuit

Stable – jitter


Resolution

time

time

Resolution: 3bits, 23 = 8 combinations

Resolution: 4bits, 24 = 16 combinations

Values from 0to 7

Values from 0to 15

Better signal quantizationMore computer memory and $$

0

7

0

15


Saturation

• Resolution: 3bits, 23 = 8 combinations • Too much power to the ADC• Saturation caused by interference (RFI)

time0

7


Sampling – FT, Nyquist and Aliasing


Sampling – FT, Nyquist and Aliasing

Fs = 200Hz, Ts = 5ms, Fs/2 = 100Hz


Signal Processing – Adder

=

1bit adder

4bit adder

4

4

5


Signal Processing – Multiplier

4

4

8

• Multiplication by a Constant – Gain• Multiplication by -1, Sign change• Multiplication by a function – e.g. sin/cos - up/down conv.

Things to consider• Bit growing• Precision – Approximation Errors


Signal Processing – Functions, e.g. sin/cos

x[n]

sin[n]

x[n] * sin[n]

n

Phase Increment

ADDR

Mem - LUT

DATA

…

DDS


Signal Processing – Synchronization

clk

latency


Filtering – e.g. Finite Impulse Response (FIR)


Auto Correlation


Discrete Fourier Transform - DFT

X[k] =FNx[n]

FFT – Fast Fourier Transform, optimized DFT (butterflies)


Examples with Signals

• Fourier Transform• Saturation• Averaging• Clock Jitter


Fourier Transform, one tone


Fourier Transform, two tones


Fourier Transform, noise effect


Fourier Transform, averaging


Fourier Transform, longer transf.


Fourier Transform, Saturation


Fourier Transform, Clock Jitter

0% Jitter

40% Jitter


Applications in Radio Astronomy


Gregorian Dome Receivers

Ganesan, R. “Telescope Electronics”, May 2006


Radio Frequency Signal Path

SIGNAL IN

FRONT END

IF/LO

DIGITIZERCOMPUTER

BACK-END

DETECTOR


Signal Transport – Intermediate Freq.


Final Stage – Data Acquisition

SIGNAL IN

FRONT END

IF/LO

DIGITIZERCOMPUTER

BACK-END

DETECTOR

Data Sampling and Storage


Bandpass Signals in IF


Sampling - Nyquist Zones & Analog BW


Wideband Arecibo Pulsar Processor (WAPP)

• 4 WAPPs• 1 WAPP = 2 IF Channels 2 Correlators 1 Multiplexer• 50/100 MHz BW• auto / crosscorrelations• Step attenuators• Technical issues: Difficult to troubleshoot Obsolete parts


Wideband Arecibo Pulsar Processor (WAPP)


WAPP Correlators (~1995)

High Performance CMOS Correlator Chip (ASIC)

• 16 Chips per board • Autocorrelation / Crosscorrelation• 1024 Lags / chip• 100MSPS each• “Low Power”• TTL compatible

http://www.naic.edu/~astro/general_info/correlator/cmos.html


Complex Sampling


Arecibo L-band Feed Array

• 7 Receivers• Dual Polarization• 14 analog signals• 1225 – 1525MHz 300MHz BW• Designed by Germán Cortés Medellín (Cornell)

Ganesan, R. “Telescope Electronics”, May 2006


Complex Sampling Example: ALFA

1225 1525


Mock Spectrometer / PDEV (~2007)

Designed and developed by Jeff Mock• 8 x AD9430, 12bits ADCs• 2 x Xilinx Virtex II Pro FPGA• 2 QDR Mem, 2M x 36• 1x PowerPC Processor• Flash & SRAM mems• 2 x GbE, 2 x RS232• 5 x SMA (clk, PPS, etc)• LCD 128x64 pixels

Digital BoardDigitizers


PDEV – Architecture

ADCADCADCADC GX2VP70

PPC440GX

GX2VP70

QDR2Mx36

QDR2Mx36

2 x GbE

2 x RS232

4 x SMA

Flash /SRAM

ADCADCADCADC

PCIe x8MGT

PCIe x8MGT


PDEV – Mock Spectrometer

PF

B/F

FT

16

-8k

ADC0

ADC0

ADC0

ADC0

GA

IN/O

FF

SE

T

SW

ITC

H

TEST SIGNAL

12

12

12

12 DD

C (

DD

S,

LPF

)

ST

OK

ES

AC

CU

MU

LAT

OR

PA

CK

ET

IZE

CONFIGURATION REGISTERS

PR

OC

. IN

T.

CW, Noise,CW + Noise


EALFA / PALFA Backend

14 PDEVs*

7 for 7 ALFA pixels (primary) 7 for 7 ALFA pixels (commensal)

14 File servers (4TB)We own in total 24 PDEVs

DDC (DDS, Mixer, DLPF)PFB (up to 8192 channels)Stokes parametersAccumulation, Packing* http://www.naic.edu/~phil/talks/vc09/tel_Perf_datatking_09.ppt


GALFA Spectrometer / GALSPECT (~2004)

• Backend for theArecibo L-band Feed Array (ALFA) multibeam receiver • 7 beams, dual polarization• Outputs*: Narrowband: 8192channels, 7MHz BW Wideband: 512 channels, 100MHz BW


PR Ultimate Pulsar Processing Instrument ( PUPPI)

• 100/200/400/800MHz BW • Polyphase Filter Bank• Dual Pol. 8 bit ADC• Full Stokes• 200MB per second recording (10GbE)• 0-15.5dB Level Control• PSRFITS data format• 1xBee2 + 2xiBOB


Recording Systems – Mark IV / 5A / 5C / RDBE

• Mark IV + Mark 5A: 1Gbps (125MB every second)• RDBE + Mark5C: 4Gbps (500MB every second)•eVLBI, AO-UPR-Centenial link: 155Mbps all time512Mbps 24h-6h


Roach Radar Backend – RRB• Complex Baseband -

Digital Down Converter (DDC)• 50MHz bandwidth max.• 2 x IF channels (polA/polB)• Bit selection, 8/4bits• 1.6Gbps max. data rate• Doppler correction• Programmable digital filter• Hardware (three systems):

ROACH – Signal Proc.katADC – 2x1.5Gsps@8bitRAID Server, dual 10GbE

• Fixed parameters: Summer 2012


Analog v.s. Digital


Down Conversion


Digital Down Conversion


Questions?

sdss7 - dsp and backends intro, 12 jul 2013 digital signal processing basics and ao back-ends luis...

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